1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2013 Freescale Semiconductor, Inc.
4 * Copyright (C) 2014 O.S. Systems Software LTDA.
6 * Author: Fabio Estevam <fabio.estevam@freescale.com>
9 #include <asm/arch/clock.h>
10 #include <asm/arch/crm_regs.h>
11 #include <asm/arch/iomux.h>
12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/mx6-pins.h>
14 #include <asm/arch/mxc_hdmi.h>
15 #include <asm/arch/sys_proto.h>
17 #include <asm/mach-imx/iomux-v3.h>
18 #include <asm/mach-imx/mxc_i2c.h>
19 #include <asm/mach-imx/boot_mode.h>
20 #include <asm/mach-imx/video.h>
21 #include <asm/mach-imx/sata.h>
24 #include <linux/sizes.h>
30 #include <power/pmic.h>
31 #include <power/pfuze100_pmic.h>
33 DECLARE_GLOBAL_DATA_PTR;
35 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
36 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
37 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
39 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
40 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
42 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
43 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
44 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
46 #define ETH_PHY_RESET IMX_GPIO_NR(3, 29)
47 #define ETH_PHY_AR8035_POWER IMX_GPIO_NR(7, 13)
48 #define REV_DETECTION IMX_GPIO_NR(2, 28)
50 /* Speed defined in Kconfig is only applicable when not using DM_I2C. */
52 #define I2C1_SPEED_NON_DM 0
53 #define I2C2_SPEED_NON_DM 0
55 #define I2C1_SPEED_NON_DM CONFIG_SYS_MXC_I2C1_SPEED
56 #define I2C2_SPEED_NON_DM CONFIG_SYS_MXC_I2C2_SPEED
59 static bool with_pmic;
63 gd->ram_size = imx_ddr_size();
68 static iomux_v3_cfg_t const uart1_pads[] = {
69 IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
70 IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
73 static iomux_v3_cfg_t const enet_pads[] = {
74 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
75 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
76 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
77 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
78 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
79 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
80 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
81 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
82 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
83 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
84 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
85 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
86 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
87 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
88 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
89 /* AR8031 PHY Reset */
90 IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
93 static iomux_v3_cfg_t const enet_ar8035_power_pads[] = {
95 IOMUX_PADS(PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)),
98 static iomux_v3_cfg_t const rev_detection_pad[] = {
99 IOMUX_PADS(PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
102 static void setup_iomux_uart(void)
104 SETUP_IOMUX_PADS(uart1_pads);
107 static void setup_iomux_enet(void)
109 SETUP_IOMUX_PADS(enet_pads);
112 SETUP_IOMUX_PADS(enet_ar8035_power_pads);
113 /* enable AR8035 POWER */
114 gpio_request(ETH_PHY_AR8035_POWER, "PHY_POWER");
115 gpio_direction_output(ETH_PHY_AR8035_POWER, 0);
117 /* wait until 3.3V of PHY and clock become stable */
120 /* Reset AR8031 PHY */
121 gpio_request(ETH_PHY_RESET, "PHY_RESET");
122 gpio_direction_output(ETH_PHY_RESET, 0);
124 gpio_set_value(ETH_PHY_RESET, 1);
128 static int ar8031_phy_fixup(struct phy_device *phydev)
133 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
134 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
135 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
136 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
138 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
140 mask = 0xffe7; /* AR8035 */
142 mask = 0xffe3; /* AR8031 */
146 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
148 /* introduce tx clock delay */
149 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
150 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
152 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
157 int board_phy_config(struct phy_device *phydev)
159 ar8031_phy_fixup(phydev);
161 if (phydev->drv->config)
162 phydev->drv->config(phydev);
167 #if defined(CONFIG_VIDEO_IPUV3)
168 struct i2c_pads_info mx6q_i2c2_pad_info = {
170 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL
171 | MUX_PAD_CTRL(I2C_PAD_CTRL),
172 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12
173 | MUX_PAD_CTRL(I2C_PAD_CTRL),
174 .gp = IMX_GPIO_NR(4, 12)
177 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA
178 | MUX_PAD_CTRL(I2C_PAD_CTRL),
179 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13
180 | MUX_PAD_CTRL(I2C_PAD_CTRL),
181 .gp = IMX_GPIO_NR(4, 13)
185 struct i2c_pads_info mx6dl_i2c2_pad_info = {
187 .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL
188 | MUX_PAD_CTRL(I2C_PAD_CTRL),
189 .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12
190 | MUX_PAD_CTRL(I2C_PAD_CTRL),
191 .gp = IMX_GPIO_NR(4, 12)
194 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA
195 | MUX_PAD_CTRL(I2C_PAD_CTRL),
196 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13
197 | MUX_PAD_CTRL(I2C_PAD_CTRL),
198 .gp = IMX_GPIO_NR(4, 13)
202 struct i2c_pads_info mx6q_i2c3_pad_info = {
204 .i2c_mode = MX6Q_PAD_GPIO_5__I2C3_SCL
205 | MUX_PAD_CTRL(I2C_PAD_CTRL),
206 .gpio_mode = MX6Q_PAD_GPIO_5__GPIO1_IO05
207 | MUX_PAD_CTRL(I2C_PAD_CTRL),
208 .gp = IMX_GPIO_NR(1, 5)
211 .i2c_mode = MX6Q_PAD_GPIO_16__I2C3_SDA
212 | MUX_PAD_CTRL(I2C_PAD_CTRL),
213 .gpio_mode = MX6Q_PAD_GPIO_16__GPIO7_IO11
214 | MUX_PAD_CTRL(I2C_PAD_CTRL),
215 .gp = IMX_GPIO_NR(7, 11)
219 struct i2c_pads_info mx6dl_i2c3_pad_info = {
221 .i2c_mode = MX6DL_PAD_GPIO_5__I2C3_SCL
222 | MUX_PAD_CTRL(I2C_PAD_CTRL),
223 .gpio_mode = MX6DL_PAD_GPIO_5__GPIO1_IO05
224 | MUX_PAD_CTRL(I2C_PAD_CTRL),
225 .gp = IMX_GPIO_NR(1, 5)
228 .i2c_mode = MX6DL_PAD_GPIO_16__I2C3_SDA
229 | MUX_PAD_CTRL(I2C_PAD_CTRL),
230 .gpio_mode = MX6DL_PAD_GPIO_16__GPIO7_IO11
231 | MUX_PAD_CTRL(I2C_PAD_CTRL),
232 .gp = IMX_GPIO_NR(7, 11)
236 static iomux_v3_cfg_t const fwadapt_7wvga_pads[] = {
237 IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
238 IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* HSync */
239 IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* VSync */
240 IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm)), /* Contrast */
241 IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15), /* DISP0_DRDY */
242 IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00),
243 IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01),
244 IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02),
245 IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03),
246 IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04),
247 IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05),
248 IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06),
249 IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07),
250 IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08),
251 IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09),
252 IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10),
253 IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11),
254 IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12),
255 IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13),
256 IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14),
257 IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15),
258 IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16),
259 IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17),
260 IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_BKLEN */
261 IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_VDDEN */
264 static void do_enable_hdmi(struct display_info_t const *dev)
266 imx_enable_hdmi_phy();
269 static int detect_i2c(struct display_info_t const *dev)
272 struct udevice *bus, *udev;
275 rc = uclass_get_device_by_seq(UCLASS_I2C, dev->bus, &bus);
278 rc = dm_i2c_probe(bus, dev->addr, 0, &udev);
283 return (0 == i2c_set_bus_num(dev->bus)) &&
284 (0 == i2c_probe(dev->addr));
288 static void enable_fwadapt_7wvga(struct display_info_t const *dev)
290 SETUP_IOMUX_PADS(fwadapt_7wvga_pads);
292 gpio_request(IMX_GPIO_NR(2, 10), "DISP0_BKLEN");
293 gpio_request(IMX_GPIO_NR(2, 11), "DISP0_VDDEN");
294 gpio_direction_output(IMX_GPIO_NR(2, 10), 1);
295 gpio_direction_output(IMX_GPIO_NR(2, 11), 1);
298 struct display_info_t const displays[] = {{
301 .pixfmt = IPU_PIX_FMT_RGB24,
302 .detect = detect_hdmi,
303 .enable = do_enable_hdmi,
317 .vmode = FB_VMODE_NONINTERLACED
321 .pixfmt = IPU_PIX_FMT_RGB666,
322 .detect = detect_i2c,
323 .enable = enable_fwadapt_7wvga,
325 .name = "FWBADAPT-LCD-F07A-0102",
337 .vmode = FB_VMODE_NONINTERLACED
339 size_t display_count = ARRAY_SIZE(displays);
341 static void setup_display(void)
343 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
349 reg = readl(&mxc_ccm->chsccdr);
350 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
351 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
352 writel(reg, &mxc_ccm->chsccdr);
354 /* Disable LCD backlight */
355 SETUP_IOMUX_PAD(PAD_DI0_PIN4__GPIO4_IO20);
356 gpio_request(IMX_GPIO_NR(4, 20), "LCD_BKLEN");
357 gpio_direction_input(IMX_GPIO_NR(4, 20));
359 #endif /* CONFIG_VIDEO_IPUV3 */
361 int board_eth_init(bd_t *bis)
365 return cpu_eth_init(bis);
368 int board_early_init_f(void)
378 #define PMIC_I2C_BUS 2
380 int power_init_board(void)
387 ret = pmic_get("pfuze100", &dev);
389 printf("pmic_get() ret %d\n", ret);
393 reg = pmic_reg_read(dev, PFUZE100_DEVICEID);
395 printf("pmic_reg_read() ret %d\n", reg);
398 printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
401 /* Set VGEN2 to 1.5V and enable */
402 reg = pmic_reg_read(dev, PFUZE100_VGEN2VOL);
403 reg &= ~(LDO_VOL_MASK);
404 reg |= (LDOA_1_50V | (1 << (LDO_EN)));
405 pmic_reg_write(dev, PFUZE100_VGEN2VOL, reg);
410 * Do not overwrite the console
411 * Use always serial for U-Boot console
413 int overwrite_console(void)
418 #ifdef CONFIG_CMD_BMODE
419 static const struct boot_mode board_boot_modes[] = {
420 /* 4 bit bus width */
421 {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
422 {"mmc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
427 static bool is_revc1(void)
429 SETUP_IOMUX_PADS(rev_detection_pad);
430 gpio_direction_input(REV_DETECTION);
432 if (gpio_get_value(REV_DETECTION))
438 static bool is_revd1(void)
446 int board_late_init(void)
448 #ifdef CONFIG_CMD_BMODE
449 add_board_boot_modes(board_boot_modes);
452 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
454 env_set("board_rev", "MX6QP");
456 env_set("board_rev", "MX6Q");
458 env_set("board_rev", "MX6DL");
461 env_set("board_name", "D1");
463 env_set("board_name", "C1");
465 env_set("board_name", "B1");
472 /* address of boot parameters */
473 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
475 #if defined(CONFIG_VIDEO_IPUV3)
476 setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6dl_i2c2_pad_info);
477 if (is_mx6dq() || is_mx6dqp()) {
478 setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6q_i2c2_pad_info);
479 setup_i2c(2, I2C2_SPEED_NON_DM, 0x7f, &mx6q_i2c3_pad_info);
481 setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6dl_i2c2_pad_info);
482 setup_i2c(2, I2C2_SPEED_NON_DM, 0x7f, &mx6dl_i2c3_pad_info);
493 gpio_request(REV_DETECTION, "REV_DETECT");
496 puts("Board: Wandboard rev D1\n");
498 puts("Board: Wandboard rev C1\n");
500 puts("Board: Wandboard rev B1\n");
505 #ifdef CONFIG_SPL_LOAD_FIT
506 int board_fit_config_name_match(const char *name)
509 if (!strcmp(name, "imx6q-wandboard-revb1"))
511 } else if (is_mx6dqp()) {
512 if (!strcmp(name, "imx6qp-wandboard-revd1"))
514 } else if (is_mx6dl() || is_mx6solo()) {
515 if (!strcmp(name, "imx6dl-wandboard-revb1"))