2 * Copyright (C) 2013 Freescale Semiconductor, Inc.
3 * Copyright (C) 2014 O.S. Systems Software LTDA.
5 * Author: Fabio Estevam <fabio.estevam@freescale.com>
7 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/clock.h>
11 #include <asm/arch/crm_regs.h>
12 #include <asm/arch/iomux.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/mx6-pins.h>
15 #include <asm/arch/mxc_hdmi.h>
16 #include <asm/arch/sys_proto.h>
18 #include <asm/imx-common/iomux-v3.h>
19 #include <asm/imx-common/mxc_i2c.h>
20 #include <asm/imx-common/boot_mode.h>
21 #include <asm/imx-common/video.h>
23 #include <linux/sizes.h>
25 #include <fsl_esdhc.h>
33 DECLARE_GLOBAL_DATA_PTR;
35 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
36 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
37 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
39 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
40 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
41 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
43 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
44 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
46 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
47 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
48 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
50 #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 2)
51 #define USDHC3_CD_GPIO IMX_GPIO_NR(3, 9)
52 #define ETH_PHY_RESET IMX_GPIO_NR(3, 29)
53 #define REV_DETECTION IMX_GPIO_NR(2, 28)
57 gd->ram_size = imx_ddr_size();
62 static iomux_v3_cfg_t const uart1_pads[] = {
63 IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
64 IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
67 static iomux_v3_cfg_t const usdhc1_pads[] = {
68 IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
69 IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
70 IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
71 IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
72 IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
73 IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
74 /* Carrier MicroSD Card Detect */
75 IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
78 static iomux_v3_cfg_t const usdhc3_pads[] = {
79 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
80 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
81 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
82 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
83 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
84 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
85 /* SOM MicroSD Card Detect */
86 IOMUX_PADS(PAD_EIM_DA9__GPIO3_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
89 static iomux_v3_cfg_t const enet_pads[] = {
90 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
91 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
92 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
93 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
94 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
95 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
96 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
97 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
98 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
99 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
100 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
101 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
102 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
103 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
104 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
105 /* AR8031 PHY Reset */
106 IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
109 static iomux_v3_cfg_t const rev_detection_pad[] = {
110 IOMUX_PADS(PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
113 static void setup_iomux_uart(void)
115 SETUP_IOMUX_PADS(uart1_pads);
118 static void setup_iomux_enet(void)
120 SETUP_IOMUX_PADS(enet_pads);
122 /* Reset AR8031 PHY */
123 gpio_direction_output(ETH_PHY_RESET, 0);
125 gpio_set_value(ETH_PHY_RESET, 1);
128 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
133 int board_mmc_getcd(struct mmc *mmc)
135 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
138 switch (cfg->esdhc_base) {
139 case USDHC1_BASE_ADDR:
140 ret = !gpio_get_value(USDHC1_CD_GPIO);
142 case USDHC3_BASE_ADDR:
143 ret = !gpio_get_value(USDHC3_CD_GPIO);
150 int board_mmc_init(bd_t *bis)
156 * Following map is done:
157 * (U-boot device node) (Physical Port)
159 * mmc1 Carrier board MicroSD
161 for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
164 SETUP_IOMUX_PADS(usdhc3_pads);
165 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
166 usdhc_cfg[0].max_bus_width = 4;
167 gpio_direction_input(USDHC3_CD_GPIO);
170 SETUP_IOMUX_PADS(usdhc1_pads);
171 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
172 usdhc_cfg[1].max_bus_width = 4;
173 gpio_direction_input(USDHC1_CD_GPIO);
176 printf("Warning: you configured more USDHC controllers"
177 "(%d) then supported by the board (%d)\n",
178 index + 1, CONFIG_SYS_FSL_USDHC_NUM);
182 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
190 static int mx6_rgmii_rework(struct phy_device *phydev)
194 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
195 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
196 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
197 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
199 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
202 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
204 /* introduce tx clock delay */
205 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
206 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
208 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
213 int board_phy_config(struct phy_device *phydev)
215 mx6_rgmii_rework(phydev);
217 if (phydev->drv->config)
218 phydev->drv->config(phydev);
223 #if defined(CONFIG_VIDEO_IPUV3)
224 struct i2c_pads_info mx6q_i2c2_pad_info = {
226 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL
227 | MUX_PAD_CTRL(I2C_PAD_CTRL),
228 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12
229 | MUX_PAD_CTRL(I2C_PAD_CTRL),
230 .gp = IMX_GPIO_NR(4, 12)
233 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA
234 | MUX_PAD_CTRL(I2C_PAD_CTRL),
235 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13
236 | MUX_PAD_CTRL(I2C_PAD_CTRL),
237 .gp = IMX_GPIO_NR(4, 13)
241 struct i2c_pads_info mx6dl_i2c2_pad_info = {
243 .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL
244 | MUX_PAD_CTRL(I2C_PAD_CTRL),
245 .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12
246 | MUX_PAD_CTRL(I2C_PAD_CTRL),
247 .gp = IMX_GPIO_NR(4, 12)
250 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA
251 | MUX_PAD_CTRL(I2C_PAD_CTRL),
252 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13
253 | MUX_PAD_CTRL(I2C_PAD_CTRL),
254 .gp = IMX_GPIO_NR(4, 13)
258 static iomux_v3_cfg_t const fwadapt_7wvga_pads[] = {
259 IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
260 IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* HSync */
261 IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* VSync */
262 IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm)), /* Contrast */
263 IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15), /* DISP0_DRDY */
264 IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00),
265 IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01),
266 IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02),
267 IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03),
268 IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04),
269 IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05),
270 IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06),
271 IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07),
272 IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08),
273 IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09),
274 IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10),
275 IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11),
276 IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12),
277 IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13),
278 IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14),
279 IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15),
280 IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16),
281 IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17),
282 IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_BKLEN */
283 IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_VDDEN */
286 static void do_enable_hdmi(struct display_info_t const *dev)
288 imx_enable_hdmi_phy();
291 static int detect_i2c(struct display_info_t const *dev)
293 return (0 == i2c_set_bus_num(dev->bus)) &&
294 (0 == i2c_probe(dev->addr));
297 static void enable_fwadapt_7wvga(struct display_info_t const *dev)
299 SETUP_IOMUX_PADS(fwadapt_7wvga_pads);
301 gpio_direction_output(IMX_GPIO_NR(2, 10), 1);
302 gpio_direction_output(IMX_GPIO_NR(2, 11), 1);
305 struct display_info_t const displays[] = {{
308 .pixfmt = IPU_PIX_FMT_RGB24,
309 .detect = detect_hdmi,
310 .enable = do_enable_hdmi,
324 .vmode = FB_VMODE_NONINTERLACED
328 .pixfmt = IPU_PIX_FMT_RGB666,
329 .detect = detect_i2c,
330 .enable = enable_fwadapt_7wvga,
332 .name = "FWBADAPT-LCD-F07A-0102",
344 .vmode = FB_VMODE_NONINTERLACED
346 size_t display_count = ARRAY_SIZE(displays);
348 static void setup_display(void)
350 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
356 reg = readl(&mxc_ccm->chsccdr);
357 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
358 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
359 writel(reg, &mxc_ccm->chsccdr);
361 /* Disable LCD backlight */
362 SETUP_IOMUX_PAD(PAD_DI0_PIN4__GPIO4_IO20);
363 gpio_direction_input(IMX_GPIO_NR(4, 20));
365 #endif /* CONFIG_VIDEO_IPUV3 */
367 int board_eth_init(bd_t *bis)
371 return cpu_eth_init(bis);
374 int board_early_init_f(void)
377 #if defined(CONFIG_VIDEO_IPUV3)
384 * Do not overwrite the console
385 * Use always serial for U-Boot console
387 int overwrite_console(void)
392 #ifdef CONFIG_CMD_BMODE
393 static const struct boot_mode board_boot_modes[] = {
394 /* 4 bit bus width */
395 {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
396 {"mmc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
401 static bool is_revc1(void)
403 SETUP_IOMUX_PADS(rev_detection_pad);
404 gpio_direction_input(REV_DETECTION);
406 if (gpio_get_value(REV_DETECTION))
412 int board_late_init(void)
414 #ifdef CONFIG_CMD_BMODE
415 add_board_boot_modes(board_boot_modes);
418 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
419 if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
420 setenv("board_rev", "MX6Q");
422 setenv("board_rev", "MX6DL");
425 setenv("board_name", "C1");
427 setenv("board_name", "B1");
434 /* address of boot parameters */
435 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
437 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
438 if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
439 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c2_pad_info);
441 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
449 puts("Board: Wandboard rev C1\n");
451 puts("Board: Wandboard rev B1\n");