3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include "walnut405.h"
26 #include <asm/processor.h>
27 #include <spd_sdram.h>
29 int board_pre_init (void)
31 /*-------------------------------------------------------------------------+
32 | Interrupt controller setup for the Walnut board.
33 | Note: IRQ 0-15 405GP internally generated; active high; level sensitive
34 | IRQ 16 405GP internally generated; active low; level sensitive
36 | IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive
37 | IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive
38 | IRQ 27 (EXT IRQ 2) Not Used
39 | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
40 | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
41 | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
42 | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
43 | Note for Walnut board:
44 | An interrupt taken for the FPGA (IRQ 25) indicates that either
45 | the Mouse, Keyboard, IRDA, or External Expansion caused the
46 | interrupt. The FPGA must be read to determine which device
47 | caused the interrupt. The default setting of the FPGA clears
49 +-------------------------------------------------------------------------*/
51 mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
52 mtdcr (uicer, 0x00000000); /* disable all ints */
53 mtdcr (uiccr, 0x00000020); /* set all but FPGA SMI to be non-critical */
54 mtdcr (uicpr, 0xFFFFFFE0); /* set int polarities */
55 mtdcr (uictr, 0x10000000); /* set int trigger levels */
56 mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
57 mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
59 #define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
60 /* BAS=0xF00,BS=0x0(1MB),BU=0x3(R/W),BW=0x0( 8 bits) */
61 mtebc (pb1ap, 0x02815480);
62 mtebc (pb1cr, 0xF0018000);
64 /* BAS=0xF01,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */
65 mtebc (pb2ap, 0x04815A80);
66 mtebc (pb2cr, 0xF0118000);
68 /* BAS=0xF02,BS=0x0(1MB),BU=0x3(R/W),BW=0x0( 8 bits) */
69 mtebc (pb3ap, 0x01815280);
70 mtebc (pb3cr, 0xF0218000);
72 /* BAS=0xF03,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */
73 mtebc (pb7ap, 0x01815280);
74 mtebc (pb7cr, 0xF0318000);
76 /* set UART1 control to select CTS/RTS */
77 #define FPGA_BRDC 0xF0300004
78 *(volatile char *) (FPGA_BRDC) |= 0x1;
84 /* ------------------------------------------------------------------------- */
87 * Check Board Identity:
92 unsigned char *s = getenv ("serial#");
97 if (!s || strncmp (s, "WALNUT405", 9)) {
98 puts ("### No HW ID - assuming WALNUT405");
100 for (e = s; *e; ++e) {
114 /* -------------------------------------------------------------------------
115 initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
116 the necessary info for SDRAM controller configuration
117 ------------------------------------------------------------------------- */
118 long int initdram (int board_type)
120 return spd_sdram (0);
123 /* ------------------------------------------------------------------------- */
127 /* TODO: XXX XXX XXX */
128 printf ("test: xxx MB - ok\n");
133 /* ------------------------------------------------------------------------- */