3 * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com
5 * Bill Hunter, Wave 7 Optics, william.hunter@mediaone.net
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/processor.h>
29 #include <linux/compiler.h>
33 fpga_img_write(unsigned long *src, unsigned long len, unsigned short *daddr)
36 volatile unsigned long val;
37 volatile unsigned short *dest = daddr; /* volatile-bypass optimizer */
39 for (i = 0; i < len; i++, src++) {
41 *dest = (unsigned short) ((val & 0xff000000L) >> 16);
42 *dest = (unsigned short) ((val & 0x00ff0000L) >> 8);
43 *dest = (unsigned short) (val & 0x0000ff00L);
44 *dest = (unsigned short) ((val & 0x000000ffL) << 8);
47 /* Terminate programming with 4 C clocks */
49 val = *(unsigned short *) dest;
50 val = *(unsigned short *) dest;
51 val = *(unsigned short *) dest;
52 val = *(unsigned short *) dest;
58 fpgaDownload(unsigned char *saddr, unsigned long size, unsigned short *daddr)
60 int i; /* index, intr disable flag */
61 int start; /* timer */
62 unsigned long greg, grego; /* GPIO & output register */
63 unsigned long length; /* image size in words */
64 unsigned long *source; /* image source addr */
65 unsigned short *dest; /* destination FPGA addr */
66 volatile unsigned short *ndest; /* temp dest FPGA addr */
67 unsigned long cnfg = GPIO_XCV_CNFG; /* FPGA CNFG */
68 unsigned long eirq = GPIO_XCV_IRQ;
69 int retval = -1; /* Function return value */
70 __maybe_unused volatile unsigned short val; /* temp val */
72 /* Setup some basic values */
73 length = (size / 4) + 1; /* size in words, rounding UP
75 source = (unsigned long *) saddr;
76 dest = (unsigned short *) daddr;
78 /* Get DCR output register */
79 grego = in32(PPC405GP_GPIO0_OR);
82 grego &= ~GPIO_XCV_PROG; /* PROG line low */
83 out32(PPC405GP_GPIO0_OR, grego);
85 /* Setup timeout timer */
88 /* Wait for FPGA init line to go low */
89 while (in32(PPC405GP_GPIO0_IR) & GPIO_XCV_INIT) {
90 /* Check for timeout - 100us max, so use 3ms */
91 if (get_timer(start) > 3) {
92 printf(" failed to start init.\n");
93 log_warn(ERR_XINIT0); /* Don't halt */
95 /* Reset line stays low */
96 goto done; /* I like gotos... */
101 grego |= GPIO_XCV_PROG; /* PROG line high */
102 out32(PPC405GP_GPIO0_OR, grego);
104 /* Wait for FPGA end of init period = init line go hi */
105 while (!(in32(PPC405GP_GPIO0_IR) & GPIO_XCV_INIT)) {
107 /* Check for timeout */
108 if (get_timer(start) > 3) {
109 printf(" failed to exit init.\n");
110 log_warn(ERR_XINIT1);
113 grego &= ~GPIO_XCV_PROG; /* PROG line low */
114 out32(PPC405GP_GPIO0_OR, grego);
120 /* Now program FPGA ... */
122 for (i = 0; i < CONFIG_NUM_FPGAS; i++) {
123 /* Toggle IRQ/GPIO */
124 greg = mfdcr(CPC0_CR0); /* get chip ctrl register */
125 greg |= eirq; /* toggle irq/gpio */
126 mtdcr(CPC0_CR0, greg); /* ... just do it */
128 /* turn on open drain for CNFG */
129 greg = in32(PPC405GP_GPIO0_ODR); /* get open drain register */
130 greg |= cnfg; /* CNFG open drain */
131 out32(PPC405GP_GPIO0_ODR, greg); /* .. just do it */
133 /* Turn output enable on for CNFG */
134 greg = in32(PPC405GP_GPIO0_TCR); /* get tristate register */
135 greg |= cnfg; /* CNFG tristate inactive */
136 out32(PPC405GP_GPIO0_TCR, greg); /* ... just do it */
138 /* Setup FPGA for programming */
139 grego &= ~cnfg; /* CONFIG line low */
140 out32(PPC405GP_GPIO0_OR, grego);
145 printf("\n destination: 0x%lx ", (unsigned long) ndest);
147 fpga_img_write(source, length, (unsigned short *) ndest);
149 /* Done programming */
150 grego |= cnfg; /* CONFIG line high */
151 out32(PPC405GP_GPIO0_OR, grego);
153 /* Turn output enable OFF for CNFG */
154 greg = in32(PPC405GP_GPIO0_TCR); /* get tristate register */
155 greg &= ~cnfg; /* CNFG tristate inactive */
156 out32(PPC405GP_GPIO0_TCR, greg); /* ... just do it */
158 /* Toggle IRQ/GPIO */
159 greg = mfdcr(CPC0_CR0); /* get chip ctrl register */
160 greg &= ~eirq; /* toggle irq/gpio */
161 mtdcr(CPC0_CR0, greg); /* ... just do it */
163 /* XXX - Next FPGA addr */
164 ndest = (unsigned short *) ((char *) ndest + 0x00100000L);
165 cnfg >>= 1; /* XXX - Next */
169 /* Terminate programming with 4 C clocks */
171 for (i = 0; i < CONFIG_NUM_FPGAS; i++) {
176 ndest = (unsigned short *) ((char *) ndest + 0x00100000L);
180 start = get_timer(0);
182 /* Wait for FPGA end of programming period = Test DONE low */
183 while (!(in32(PPC405GP_GPIO0_IR) & GPIO_XCV_DONE)) {
185 /* Check for timeout */
186 if (get_timer(start) > 3) {
187 printf(" done failed to come high.\n");
188 log_warn(ERR_XDONE1);
191 grego &= ~GPIO_XCV_PROG; /* PROG line low */
192 out32(PPC405GP_GPIO0_OR, grego);
198 printf("\n FPGA load succeeded\n");
199 retval = 0; /* Program OK */
205 /* FPGA image is stored in flash */
206 extern flash_info_t flash_info[];
210 unsigned int i, j, ptr; /* General purpose */
211 unsigned char bufchar; /* General purpose character */
212 unsigned char *buf; /* Start of image pointer */
213 unsigned long len; /* Length of image */
214 unsigned char *fn_buf; /* Start of filename string */
215 unsigned int fn_len; /* Length of filename string */
216 unsigned char *xcv_buf; /* Pointer to start of image */
217 unsigned long xcv_len; /* Length of image */
218 unsigned long crc; /* 30bit crc in image */
219 unsigned long calc_crc; /* Calc'd 30bit crc */
222 /* Tell the world what we are doing */
226 * Get address of first sector where the FPGA
229 buf = (unsigned char *) flash_info[1].start[0];
232 * Get the stored image's CRC & length.
234 crc = *(unsigned long *) (buf + 4); /* CRC is first long word */
235 len = *(unsigned long *) (buf + 8); /* Image len is next long */
238 if ((len < 0x133A4) || (len > 0x80000))
242 * Get the file name pointer and length.
243 * filename length is next short
245 fn_len = (*(unsigned short *) (buf + 12) & 0xff);
249 * Get the FPGA image pointer and length length.
251 xcv_buf = fn_buf + fn_len; /* pointer to fpga image */
252 xcv_len = len - 14 - fn_len; /* fpga image length */
254 /* Check for uninitialized FLASH */
255 if ((strncmp((char *) buf, "w7o", 3) != 0) || (len > 0x0007ffffL)
260 * Calculate and Check the image's CRC.
262 calc_crc = crc32(0, xcv_buf, xcv_len);
263 if (crc != calc_crc) {
264 printf("\nfailed - bad CRC\n");
268 /* Output the file name */
269 printf("file name : ");
270 for (i = 0; i < fn_len; i++) {
271 bufchar = fn_buf[+i];
272 if (bufchar < ' ' || bufchar > '~')
278 * find rest of display data
280 ptr = 15; /* Offset to ncd filename
281 length in fpga image */
282 j = xcv_buf[ptr]; /* Get len of ncd filename */
285 ptr = ptr + j + 3; /* skip ncd filename string +
286 3 bytes more bytes */
289 * output target device string
291 j = xcv_buf[ptr++] - 1; /* len of targ str less term */
294 printf("\n target : ");
295 for (i = 0; i < j; i++) {
296 bufchar = (xcv_buf[ptr++]);
297 if (bufchar < ' ' || bufchar > '~')
303 * output compilation date string and time string
305 ptr += 3; /* skip 2 bytes */
306 printf("\n synth time : ");
307 j = (xcv_buf[ptr++] - 1); /* len of date str less term */
310 for (i = 0; i < j; i++) {
311 bufchar = (xcv_buf[ptr++]);
312 if (bufchar < ' ' || bufchar > '~')
317 ptr += 3; /* Skip 2 bytes */
319 j = (xcv_buf[ptr++] - 1); /* slen = targ dev str len */
322 for (i = 0; i < j; i++) {
323 bufchar = (xcv_buf[ptr++]);
324 if (bufchar < ' ' || bufchar > '~')
330 * output crc and length strings
332 printf("\n len & crc : 0x%lx 0x%lx", len, crc);
337 retval = fpgaDownload((unsigned char *) xcv_buf, xcv_len,
338 (unsigned short *) 0xfd000000L);
342 printf("\n BAD FPGA image format @ %lx\n",
343 flash_info[1].start[0]);
344 log_warn(ERR_XIMAGE);
349 void test_fpga(unsigned short *daddr)
352 volatile unsigned short *ndest = daddr;
354 for (i = 0; i < CONFIG_NUM_FPGAS; i++) {
355 #if defined(CONFIG_W7OLMG)
356 ndest[0x7e] = 0x55aa;
357 if (ndest[0x7e] != 0x55aa)
358 log_warn(ERR_XRW1 + i);
359 ndest[0x7e] = 0xaa55;
360 if (ndest[0x7e] != 0xaa55)
361 log_warn(ERR_XRW1 + i);
362 ndest[0x7e] = 0xc318;
363 if (ndest[0x7e] != 0xc318)
364 log_warn(ERR_XRW1 + i);
366 #elif defined(CONFIG_W7OLMC)
367 ndest[0x800] = 0x55aa;
368 ndest[0x801] = 0xaa55;
369 ndest[0x802] = 0xc318;
370 ndest[0x4800] = 0x55aa;
371 ndest[0x4801] = 0xaa55;
372 ndest[0x4802] = 0xc318;
373 if ((ndest[0x800] != 0x55aa) ||
374 (ndest[0x801] != 0xaa55) || (ndest[0x802] != 0xc318))
375 log_warn(ERR_XRW1 + (2 * i)); /* Auto gen error code */
376 if ((ndest[0x4800] != 0x55aa) ||
377 (ndest[0x4801] != 0xaa55) || (ndest[0x4802] != 0xc318))
378 log_warn(ERR_XRW2 + (2 * i)); /* Auto gen error code */
381 #error "Unknown W7O board configuration"
385 printf(" FPGA ready\n");