3 * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
6 * Gregory E. Allen, gallen@arlut.utexas.edu
7 * Matthew E. Karger, karger@arlut.utexas.edu
8 * Applied Research Laboratories, The University of Texas at Austin
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/processor.h>
41 ulong busfreq = get_bus_freq(0);
44 printf("Board: UTX8245 Local Bus at %s MHz\n", strmhz(buf, busfreq));
49 long int initdram(int board_type)
57 size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
59 new_bank0_end = size/2 - 1;
60 new_bank1_end = size - 1;
61 mear1 = mpc824x_mpc107_getreg(MEAR1);
62 emear1 = mpc824x_mpc107_getreg(EMEAR1);
64 mear1 = (mear1 & 0xFFFF0000) |
65 ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
66 ((new_bank1_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT << 8);
67 emear1 = (emear1 & 0xFFFF0000) |
68 ((new_bank0_end & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
69 ((new_bank1_end & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT << 8);
71 mpc824x_mpc107_setreg(MEAR1, mear1);
72 mpc824x_mpc107_setreg(EMEAR1, emear1);
79 * Initialize PCI Devices, report devices found.
82 static struct pci_config_table pci_utx8245_config_table[] = {
83 #ifndef CONFIG_PCI_PNP
84 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0C, PCI_ANY_ID,
85 pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
87 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
88 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0B, PCI_ANY_ID,
89 pci_cfgfunc_config_device, { PCI_FIREWIRE_IOADDR,
91 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
92 #endif /*CONFIG_PCI_PNP*/
97 static void pci_utx8245_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
99 if (PCI_DEV(dev) == 11)
100 /* assign serial interrupt line 9 (int25) to FireWire */
101 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 25);
103 else if (PCI_DEV(dev) == 12)
104 /* assign serial interrupt line 8 (int24) to Ethernet */
105 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 24);
107 else if (PCI_DEV(dev) == 14)
108 /* assign serial interrupt line 0 (int16) to PMC slot 0 */
109 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 16);
111 else if (PCI_DEV(dev) == 15)
112 /* assign serial interrupt line 1 (int17) to PMC slot 1 */
113 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 17);
116 static struct pci_controller utx8245_hose = {
117 #ifndef CONFIG_PCI_PNP
118 config_table: pci_utx8245_config_table,
119 fixup_irq: pci_utx8245_fixup_irq,
120 write_byte: pci_hose_write_config_byte
121 #endif /*CONFIG_PCI_PNP*/
124 void pci_init_board (void)
126 pci_mpc824x_init(&utx8245_hose);