3 * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
6 * Gregory E. Allen, gallen@arlut.utexas.edu
7 * Matthew E. Karger, karger@arlut.utexas.edu
8 * Applied Research Laboratories, The University of Texas at Austin
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/processor.h>
41 ulong busfreq = get_bus_freq(0);
44 printf("Board: UTX8245 Local Bus at %s MHz\n", strmhz(buf, busfreq));
49 long int initdram(int board_type)
53 volatile uchar *base = CFG_SDRAM_BASE;
58 write_bat(IBAT1, ((CFG_MAX_RAM_SIZE/2) | BATU_BL_256M | BATU_VS | BATU_VP),
59 ( (CFG_MAX_RAM_SIZE/2)| BATL_PP_10 | BATL_MEMCOHERENCE));
61 write_bat(DBAT1, ((CFG_MAX_RAM_SIZE/2) | BATU_BL_256M | BATU_VS | BATU_VP),
62 ( (CFG_MAX_RAM_SIZE/2)| BATL_PP_10 | BATL_MEMCOHERENCE));
64 for (i=0; i<SAVE_SZ; i++) {
65 save[i] = 0; /* clear table */
68 for (i=0, cnt=(CFG_MAX_RAM_SIZE / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) {
69 addr = (volatile ulong *)base + cnt;
74 addr = (volatile ulong *)base;
83 for (cnt = 1; cnt < CFG_MAX_RAM_SIZE / sizeof(long); cnt <<= 1) {
84 addr = (volatile ulong *)base + cnt;
88 ulong new_bank0_end = cnt * sizeof(long) - 1;
89 ulong mear1 = mpc824x_mpc107_getreg(MEAR1);
90 ulong emear1 = mpc824x_mpc107_getreg(EMEAR1);
91 mear1 = (mear1 & 0xFFFFFF00) |
92 ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
93 emear1 = (emear1 & 0xFFFFFF00) |
94 ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
95 mpc824x_mpc107_setreg(MEAR1, mear1);
96 mpc824x_mpc107_setreg(EMEAR1, emear1);
98 ret = cnt * sizeof(long);
103 ret = CFG_MAX_RAM_SIZE;
107 return (CFG_MAX_RAM_SIZE);
114 * Initialize PCI Devices, report devices found.
117 static struct pci_config_table pci_utx8245_config_table[] = {
118 #ifndef CONFIG_PCI_PNP
119 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0C, PCI_ANY_ID,
120 pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
122 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
123 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0B, PCI_ANY_ID,
124 pci_cfgfunc_config_device, { PCI_FIREWIRE_IOADDR,
125 PCI_FIREWIRE_MEMADDR,
126 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
127 #endif /*CONFIG_PCI_PNP*/
132 static void pci_utx8245_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
134 if (PCI_DEV(dev) == 11)
135 /* assign serial interrupt line 9 (int25) to FireWire */
136 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 25);
138 else if (PCI_DEV(dev) == 12)
139 /* assign serial interrupt line 8 (int24) to Ethernet */
140 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 24);
142 else if (PCI_DEV(dev) == 14)
143 /* assign serial interrupt line 0 (int16) to PMC slot 0 */
144 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 16);
146 else if (PCI_DEV(dev) == 15)
147 /* assign serial interrupt line 1 (int17) to PMC slot 1 */
148 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 17);
151 static struct pci_controller utx8245_hose = {
152 #ifndef CONFIG_PCI_PNP
153 config_table: pci_utx8245_config_table,
154 fixup_irq: pci_utx8245_fixup_irq,
155 write_byte: pci_hose_write_config_byte
156 #endif /*CONFIG_PCI_PNP*/
159 void pci_init_board (void)
161 pci_mpc824x_init(&utx8245_hose);