1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2013 Freescale Semiconductor, Inc.
5 * Author: Fabio Estevam <fabio.estevam@freescale.com>
9 #include <asm/arch/clock.h>
10 #include <asm/arch/imx-regs.h>
11 #include <asm/arch/iomux.h>
14 #include <asm/arch/mx6-pins.h>
15 #include <linux/errno.h>
17 #include <asm/mach-imx/iomux-v3.h>
18 #include <asm/mach-imx/sata.h>
20 #include <fsl_esdhc_imx.h>
21 #include <asm/arch/crm_regs.h>
23 #include <asm/arch/sys_proto.h>
28 DECLARE_GLOBAL_DATA_PTR;
30 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
31 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
32 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
34 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
35 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
37 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
38 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
39 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
41 #define WDT_EN IMX_GPIO_NR(5, 4)
42 #define WDT_TRG IMX_GPIO_NR(3, 19)
46 gd->ram_size = imx_ddr_size();
51 static iomux_v3_cfg_t const uart2_pads[] = {
52 IOMUX_PADS(PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
53 IOMUX_PADS(PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
56 static iomux_v3_cfg_t const usdhc3_pads[] = {
57 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
58 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
59 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
60 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
61 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
62 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
65 static iomux_v3_cfg_t const wdog_pads[] = {
66 IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
67 IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19),
70 int mx6_rgmii_rework(struct phy_device *phydev)
73 * Bug: Apparently uDoo does not works with Gigabit switches...
74 * Limiting speed to 10/100Mbps, and setting master mode, seems to
75 * be the only way to have a successfull PHY auto negotiation.
76 * How to fix: Understand why Linux kernel do not have this issue.
78 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0x1c00);
80 /* control data pad skew - devaddr = 0x02, register = 0x04 */
81 ksz9031_phy_extended_write(phydev, 0x02,
82 MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
83 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
84 /* rx data pad skew - devaddr = 0x02, register = 0x05 */
85 ksz9031_phy_extended_write(phydev, 0x02,
86 MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
87 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
88 /* tx data pad skew - devaddr = 0x02, register = 0x05 */
89 ksz9031_phy_extended_write(phydev, 0x02,
90 MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
91 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
92 /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
93 ksz9031_phy_extended_write(phydev, 0x02,
94 MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
95 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
99 static iomux_v3_cfg_t const enet_pads1[] = {
100 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
101 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
102 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
103 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
104 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
105 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
106 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
107 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
108 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
109 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
111 IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL)),
112 /* Ethernet power supply */
113 IOMUX_PADS(PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
114 /* pin 32 - 1 - (MODE0) all */
115 IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
116 /* pin 31 - 1 - (MODE1) all */
117 IOMUX_PADS(PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)),
118 /* pin 28 - 1 - (MODE2) all */
119 IOMUX_PADS(PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
120 /* pin 27 - 1 - (MODE3) all */
121 IOMUX_PADS(PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
122 /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
123 IOMUX_PADS(PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)),
126 static iomux_v3_cfg_t const enet_pads2[] = {
127 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
128 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
129 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
130 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
131 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
134 static void setup_iomux_enet(void)
136 SETUP_IOMUX_PADS(enet_pads1);
138 gpio_direction_output(IMX_GPIO_NR(2, 31), 1); /* Power supply on */
140 gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* assert PHY rst */
142 gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
143 gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
144 gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
145 gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
146 gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
149 gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* deassert PHY rst */
151 /* Need 100ms delay to exit from reset. */
154 gpio_free(IMX_GPIO_NR(6, 24));
155 gpio_free(IMX_GPIO_NR(6, 25));
156 gpio_free(IMX_GPIO_NR(6, 27));
157 gpio_free(IMX_GPIO_NR(6, 28));
158 gpio_free(IMX_GPIO_NR(6, 29));
160 SETUP_IOMUX_PADS(enet_pads2);
163 static void setup_iomux_uart(void)
165 SETUP_IOMUX_PADS(uart2_pads);
168 static void setup_iomux_wdog(void)
170 SETUP_IOMUX_PADS(wdog_pads);
171 gpio_direction_output(WDT_TRG, 0);
172 gpio_direction_output(WDT_EN, 1);
173 gpio_direction_input(WDT_TRG);
176 static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
178 int board_mmc_getcd(struct mmc *mmc)
180 return 1; /* Always present */
183 int board_eth_init(bd_t *bis)
185 uint32_t base = IMX_FEC_BASE;
186 struct mii_dev *bus = NULL;
187 struct phy_device *phydev = NULL;
192 #ifdef CONFIG_FEC_MXC
193 bus = fec_get_miibus(base, -1);
196 /* scan phy 4,5,6,7 */
197 phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
203 printf("using phy at %d\n", phydev->addr);
204 ret = fec_probe(bis, -1, base, bus, phydev);
217 int board_mmc_init(bd_t *bis)
219 SETUP_IOMUX_PADS(usdhc3_pads);
220 usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
221 usdhc_cfg.max_bus_width = 4;
223 return fsl_esdhc_initialize(bis, &usdhc_cfg);
226 int board_early_init_f(void)
234 int board_phy_config(struct phy_device *phydev)
236 mx6_rgmii_rework(phydev);
237 if (phydev->drv->config)
238 phydev->drv->config(phydev);
245 /* address of boot parameters */
246 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
254 int board_late_init(void)
256 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
257 if (is_cpu_type(MXC_CPU_MX6Q))
258 env_set("board_rev", "MX6Q");
260 env_set("board_rev", "MX6DL");
267 if (is_cpu_type(MXC_CPU_MX6Q))
268 puts("Board: Udoo Quad\n");
270 puts("Board: Udoo DualLite\n");