3 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/arch/imx-regs.h>
29 #include <asm/arch/crm_regs.h>
30 #include <asm/arch/clock.h>
31 #include <asm/arch/iomux-mx51.h>
33 #include <asm/arch/sys_proto.h>
36 #include <power/pmic.h>
37 #include <fsl_esdhc.h>
42 #include <ipu_pixfmt.h>
44 DECLARE_GLOBAL_DATA_PTR;
46 static struct fb_videomode const nec_nl6448bc26_09c = {
51 37650, /* pixclock = 26.56Mhz */
53 16, /* right margin */
54 31, /* upper margin */
55 12, /* lower margin */
59 FB_VMODE_NONINTERLACED, /* vmode */
63 #ifdef CONFIG_HW_WATCHDOG
65 void hw_watchdog_reset(void)
69 /* toggle watchdog trigger pin */
70 val = gpio_get_value(IMX_GPIO_NR(3, 2));
72 gpio_set_value(IMX_GPIO_NR(3, 2), val);
76 static void init_drive_strength(void)
78 static const iomux_v3_cfg_t ddr_pads[] = {
79 NEW_PAD_CTRL(MX51_GRP_PKEDDR, 0),
80 NEW_PAD_CTRL(MX51_GRP_PKEADDR, PAD_CTL_PKE),
81 NEW_PAD_CTRL(MX51_GRP_DDRAPKS, 0),
82 NEW_PAD_CTRL(MX51_GRP_DDRAPUS, PAD_CTL_PUS_100K_UP),
83 NEW_PAD_CTRL(MX51_GRP_DDR_SR_A1, PAD_CTL_SRE_FAST),
84 NEW_PAD_CTRL(MX51_GRP_DDR_A0, PAD_CTL_DSE_HIGH),
85 NEW_PAD_CTRL(MX51_GRP_DDR_A1, PAD_CTL_DSE_HIGH),
86 NEW_PAD_CTRL(MX51_PAD_DRAM_RAS__DRAM_RAS,
87 PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
88 NEW_PAD_CTRL(MX51_PAD_DRAM_CAS__DRAM_CAS,
89 PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
90 NEW_PAD_CTRL(MX51_GRP_PKEDDR, PAD_CTL_PKE),
91 NEW_PAD_CTRL(MX51_GRP_DDRPKS, 0),
92 NEW_PAD_CTRL(MX51_GRP_HYSDDR0, 0),
93 NEW_PAD_CTRL(MX51_GRP_HYSDDR1, 0),
94 NEW_PAD_CTRL(MX51_GRP_HYSDDR2, 0),
95 NEW_PAD_CTRL(MX51_GRP_HYSDDR3, 0),
96 NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B0, PAD_CTL_SRE_FAST),
97 NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B1, PAD_CTL_SRE_FAST),
98 NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B2, PAD_CTL_SRE_FAST),
99 NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B4, PAD_CTL_SRE_FAST),
100 NEW_PAD_CTRL(MX51_GRP_DDRPUS, PAD_CTL_PUS_100K_UP),
101 NEW_PAD_CTRL(MX51_GRP_INMODE1, 0),
102 NEW_PAD_CTRL(MX51_GRP_DRAM_B0, PAD_CTL_DSE_MED),
103 NEW_PAD_CTRL(MX51_GRP_DRAM_B1, PAD_CTL_DSE_MED),
104 NEW_PAD_CTRL(MX51_GRP_DRAM_B2, PAD_CTL_DSE_MED),
105 NEW_PAD_CTRL(MX51_GRP_DRAM_B4, PAD_CTL_DSE_MED),
107 NEW_PAD_CTRL(MX51_PAD_DRAM_SDWE__DRAM_SDWE, MX51_GPIO_PAD_CTRL),
108 NEW_PAD_CTRL(MX51_PAD_DRAM_SDCKE0__DRAM_SDCKE0,
110 NEW_PAD_CTRL(MX51_PAD_DRAM_SDCKE1__DRAM_SDCKE1,
112 NEW_PAD_CTRL(MX51_PAD_DRAM_SDCLK__DRAM_SDCLK,
114 NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS0__DRAM_SDQS0,
116 NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS1__DRAM_SDQS1,
118 NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS2__DRAM_SDQS2,
120 NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS3__DRAM_SDQS3,
122 NEW_PAD_CTRL(MX51_PAD_DRAM_CS0__DRAM_CS0, MX51_GPIO_PAD_CTRL),
123 NEW_PAD_CTRL(MX51_PAD_DRAM_CS1__DRAM_CS1, MX51_GPIO_PAD_CTRL),
124 NEW_PAD_CTRL(MX51_PAD_DRAM_DQM0__DRAM_DQM0, MX51_GPIO_PAD_CTRL),
125 NEW_PAD_CTRL(MX51_PAD_DRAM_DQM1__DRAM_DQM1, MX51_GPIO_PAD_CTRL),
126 NEW_PAD_CTRL(MX51_PAD_DRAM_DQM2__DRAM_DQM2, MX51_GPIO_PAD_CTRL),
127 NEW_PAD_CTRL(MX51_PAD_DRAM_DQM3__DRAM_DQM3, MX51_GPIO_PAD_CTRL),
130 imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads));
135 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
141 static void setup_weim(void)
143 struct weim *pweim = (struct weim *)WEIM_BASE_ADDR;
145 pweim->cs0gcr1 = 0x004100b9;
146 pweim->cs0gcr2 = 0x00000001;
147 pweim->cs0rcr1 = 0x0a018000;
149 pweim->cs0wcr1 = 0x0704a240;
152 static void setup_uart(void)
154 static const iomux_v3_cfg_t uart_pads[] = {
155 MX51_PAD_EIM_D25__UART3_RXD, /* console RX */
156 MX51_PAD_EIM_D26__UART3_TXD, /* console TX */
159 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
162 #ifdef CONFIG_MXC_SPI
163 void spi_io_init(void)
165 static const iomux_v3_cfg_t spi_pads[] = {
166 NEW_PAD_CTRL(MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, PAD_CTL_HYS |
167 PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
168 NEW_PAD_CTRL(MX51_PAD_CSPI1_MISO__ECSPI1_MISO, PAD_CTL_HYS |
169 PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
170 NEW_PAD_CTRL(MX51_PAD_CSPI1_SS0__ECSPI1_SS0, PAD_CTL_HYS |
171 PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
172 NEW_PAD_CTRL(MX51_PAD_CSPI1_SS1__ECSPI1_SS1, PAD_CTL_HYS |
173 PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
174 NEW_PAD_CTRL(MX51_PAD_DI1_PIN11__ECSPI1_SS2, PAD_CTL_HYS |
175 PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
176 NEW_PAD_CTRL(MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, PAD_CTL_HYS |
177 PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
180 imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
183 static void reset_peripherals(int reset)
185 #ifdef CONFIG_VISION2_HW_1_0
186 static const iomux_v3_cfg_t fec_cfg_pads[] = {
188 NEW_PAD_CTRL(MX51_PAD_EIM_EB3__GPIO2_23, NO_PAD_CTRL),
190 NEW_PAD_CTRL(MX51_PAD_EIM_CS2__GPIO2_27, NO_PAD_CTRL),
192 NEW_PAD_CTRL(MX51_PAD_EIM_CS3__GPIO2_28, NO_PAD_CTRL),
194 NEW_PAD_CTRL(MX51_PAD_EIM_CS4__GPIO2_29, NO_PAD_CTRL),
196 NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__GPIO3_10, NO_PAD_CTRL),
198 NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__GPIO3_11, NO_PAD_CTRL),
200 NEW_PAD_CTRL(MX51_PAD_NANDF_D9__GPIO3_31, NO_PAD_CTRL),
203 static const iomux_v3_cfg_t fec_pads[] = {
204 NEW_PAD_CTRL(MX51_PAD_EIM_CS3__FEC_RDATA3, MX51_PAD_CTRL_2),
205 NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, MX51_PAD_CTRL_2),
206 NEW_PAD_CTRL(MX51_PAD_EIM_EB3__FEC_RDATA1, MX51_PAD_CTRL_2),
207 MX51_PAD_NANDF_D9__FEC_RDATA0,
208 NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__FEC_RX_CLK, MX51_PAD_CTRL_4),
209 MX51_PAD_EIM_CS4__FEC_RX_ER,
210 NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__FEC_COL, MX51_PAD_CTRL_4),
216 /* reset_n is on NANDF_D15 */
217 gpio_direction_output(IMX_GPIO_NR(3, 25), 0);
219 #ifdef CONFIG_VISION2_HW_1_0
221 * set FEC Configuration lines
222 * set levels of FEC config lines
224 gpio_direction_output(IMX_GPIO_NR(3, 11), 0);
225 gpio_direction_output(IMX_GPIO_NR(3, 10), 1);
226 gpio_direction_output(IMX_GPIO_NR(3, 31), 1);
228 /* set direction of FEC config lines */
229 gpio_direction_output(IMX_GPIO_NR(2, 27), 0);
230 gpio_direction_output(IMX_GPIO_NR(2, 28), 0);
231 gpio_direction_output(IMX_GPIO_NR(2, 29), 0);
232 gpio_direction_output(IMX_GPIO_NR(2, 23), 1);
234 imx_iomux_v3_setup_multiple_pads(fec_cfg_pads,
235 ARRAY_SIZE(fec_cfg_pads));
238 /* activate reset_n pin */
239 imx_iomux_v3_setup_pad(
240 NEW_PAD_CTRL(MX51_PAD_NANDF_D15__GPIO3_25,
243 /* set FEC Control lines */
244 gpio_direction_input(IMX_GPIO_NR(3, 25));
247 #ifdef CONFIG_VISION2_HW_1_0
248 imx_iomux_v3_setup_multiple_pads(fec_pads,
249 ARRAY_SIZE(fec_pads));
254 static void power_init_mx51(void)
260 ret = pmic_init(I2C_PMIC);
264 p = pmic_get("FSL_PMIC");
268 /* Write needed to Power Gate 2 register */
269 pmic_reg_read(p, REG_POWER_MISC, &val);
271 /* enable VCAM with 2.775V to enable read from PMIC */
272 val = VCAMCONFIG | VCAMEN;
273 pmic_reg_write(p, REG_MODE_1, val);
276 * Set switchers in Auto in NORMAL mode & STANDBY mode
277 * Setup the switcher mode for SW1 & SW2
279 pmic_reg_read(p, REG_SW_4, &val);
280 val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
281 (SWMODE_MASK << SWMODE2_SHIFT)));
282 val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
283 (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
284 pmic_reg_write(p, REG_SW_4, val);
286 /* Setup the switcher mode for SW3 & SW4 */
287 pmic_reg_read(p, REG_SW_5, &val);
288 val &= ~((SWMODE_MASK << SWMODE4_SHIFT) |
289 (SWMODE_MASK << SWMODE3_SHIFT));
290 val |= (SWMODE_AUTO_AUTO << SWMODE4_SHIFT) |
291 (SWMODE_AUTO_AUTO << SWMODE3_SHIFT);
292 pmic_reg_write(p, REG_SW_5, val);
295 /* Set VGEN3 to 1.8V, VCAM to 3.0V */
296 pmic_reg_read(p, REG_SETTING_0, &val);
297 val &= ~(VCAM_MASK | VGEN3_MASK);
299 pmic_reg_write(p, REG_SETTING_0, val);
301 /* Set VVIDEO to 2.775V, VAUDIO to 3V0, VSD to 1.8V */
302 pmic_reg_read(p, REG_SETTING_1, &val);
303 val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
304 val |= VVIDEO_2_775 | VAUDIO_3_0 | VSD_1_8;
305 pmic_reg_write(p, REG_SETTING_1, val);
307 /* Configure VGEN3 and VCAM regulators to use external PNP */
308 val = VGEN3CONFIG | VCAMCONFIG;
309 pmic_reg_write(p, REG_MODE_1, val);
312 /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
313 val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
314 VVIDEOEN | VAUDIOEN | VSDEN;
315 pmic_reg_write(p, REG_MODE_1, val);
317 pmic_reg_read(p, REG_POWER_CTL2, &val);
319 pmic_reg_write(p, REG_POWER_CTL2, val);
326 static void setup_gpios(void)
328 static const iomux_v3_cfg_t gpio_pads_1[] = {
329 NEW_PAD_CTRL(MX51_PAD_GPIO1_7__GPIO1_7, PAD_CTL_PKE |
330 PAD_CTL_DSE_MED), /* CAM_SUP_DISn */
331 NEW_PAD_CTRL(MX51_PAD_DI1_PIN12__GPIO3_1, PAD_CTL_PKE |
332 PAD_CTL_DSE_MED), /* DAB Display EN */
333 NEW_PAD_CTRL(MX51_PAD_DI1_PIN13__GPIO3_2, PAD_CTL_PKE |
334 PAD_CTL_DSE_MED), /* WDOG_TRIGGER */
337 static const iomux_v3_cfg_t gpio_pads_2[] = {
338 NEW_PAD_CTRL(MX51_PAD_DI1_D0_CS__GPIO3_3, PAD_CTL_PKE |
339 PAD_CTL_DSE_MED), /* Display2 TxEN */
340 NEW_PAD_CTRL(MX51_PAD_DI1_D1_CS__GPIO3_4, PAD_CTL_PKE |
341 PAD_CTL_DSE_MED), /* DAB Light EN */
342 NEW_PAD_CTRL(MX51_PAD_DISPB2_SER_DIN__GPIO3_5, PAD_CTL_PKE |
343 PAD_CTL_DSE_MED), /* AUDIO_MUTE */
344 NEW_PAD_CTRL(MX51_PAD_DISPB2_SER_DIO__GPIO3_6, PAD_CTL_PKE |
345 PAD_CTL_DSE_MED), /* SPARE_OUT */
346 NEW_PAD_CTRL(MX51_PAD_NANDF_D14__GPIO3_26, PAD_CTL_PKE |
347 PAD_CTL_DSE_MED), /* BEEPER_EN */
348 NEW_PAD_CTRL(MX51_PAD_NANDF_D13__GPIO3_27, PAD_CTL_PKE |
349 PAD_CTL_DSE_MED), /* POWER_OFF */
350 NEW_PAD_CTRL(MX51_PAD_NANDF_D10__GPIO3_30, PAD_CTL_PKE |
351 PAD_CTL_DSE_MED), /* FRAM_WE */
352 NEW_PAD_CTRL(MX51_PAD_CSPI1_RDY__GPIO4_26, PAD_CTL_PKE |
353 PAD_CTL_DSE_MED), /* EXPANSION_EN */
354 MX51_PAD_GPIO1_2__PWM1_PWMO,
359 imx_iomux_v3_setup_multiple_pads(gpio_pads_1, ARRAY_SIZE(gpio_pads_1));
361 /* Now we need to trigger the watchdog */
364 imx_iomux_v3_setup_multiple_pads(gpio_pads_2, ARRAY_SIZE(gpio_pads_2));
367 * Set GPIO1_4 to high and output; it is used to reset
368 * the system on reboot
370 gpio_direction_output(IMX_GPIO_NR(1, 4), 1);
372 gpio_direction_output(IMX_GPIO_NR(1, 7), 0);
373 for (i = IMX_GPIO_NR(3, 1); i < IMX_GPIO_NR(3, 7); i++)
374 gpio_direction_output(i, 0);
376 gpio_direction_output(IMX_GPIO_NR(3, 30), 0);
378 /* Set POWER_OFF high */
379 gpio_direction_output(IMX_GPIO_NR(3, 27), 1);
381 gpio_direction_output(IMX_GPIO_NR(3, 26), 0);
383 gpio_direction_output(IMX_GPIO_NR(4, 26), 0);
385 gpio_direction_output(IMX_GPIO_NR(4, 25), 1);
390 static void setup_fec(void)
392 static const iomux_v3_cfg_t fec_pads[] = {
393 NEW_PAD_CTRL(MX51_PAD_EIM_EB2__FEC_MDIO, PAD_CTL_HYS |
394 PAD_CTL_PUS_22K_UP | PAD_CTL_ODE |
395 PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
396 MX51_PAD_NANDF_CS3__FEC_MDC,
397 NEW_PAD_CTRL(MX51_PAD_EIM_CS3__FEC_RDATA3, MX51_PAD_CTRL_2),
398 NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, MX51_PAD_CTRL_2),
399 NEW_PAD_CTRL(MX51_PAD_EIM_EB3__FEC_RDATA1, MX51_PAD_CTRL_2),
400 MX51_PAD_NANDF_D9__FEC_RDATA0,
401 MX51_PAD_NANDF_CS6__FEC_TDATA3,
402 MX51_PAD_NANDF_CS5__FEC_TDATA2,
403 MX51_PAD_NANDF_CS4__FEC_TDATA1,
404 MX51_PAD_NANDF_D8__FEC_TDATA0,
405 MX51_PAD_NANDF_CS7__FEC_TX_EN,
406 MX51_PAD_NANDF_CS2__FEC_TX_ER,
407 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
408 NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__FEC_COL, MX51_PAD_CTRL_4),
409 NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__FEC_RX_CLK, MX51_PAD_CTRL_4),
410 MX51_PAD_EIM_CS5__FEC_CRS,
411 MX51_PAD_EIM_CS4__FEC_RX_ER,
412 NEW_PAD_CTRL(MX51_PAD_NANDF_D11__FEC_RX_DV, MX51_PAD_CTRL_4),
415 imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
418 struct fsl_esdhc_cfg esdhc_cfg[1] = {
419 {MMC_SDHC1_BASE_ADDR},
422 int get_mmc_getcd(u8 *cd, struct mmc *mmc)
424 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
426 if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
427 *cd = gpio_get_value(IMX_GPIO_NR(1, 0));
434 #ifdef CONFIG_FSL_ESDHC
435 int board_mmc_init(bd_t *bis)
437 static const iomux_v3_cfg_t sd1_pads[] = {
438 NEW_PAD_CTRL(MX51_PAD_SD1_CMD__SD1_CMD, PAD_CTL_DSE_MAX |
439 PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
440 NEW_PAD_CTRL(MX51_PAD_SD1_CLK__SD1_CLK, PAD_CTL_DSE_MAX |
441 PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
442 NEW_PAD_CTRL(MX51_PAD_SD1_DATA0__SD1_DATA0, PAD_CTL_DSE_MAX |
443 PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
444 NEW_PAD_CTRL(MX51_PAD_SD1_DATA1__SD1_DATA1, PAD_CTL_DSE_MAX |
445 PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
446 NEW_PAD_CTRL(MX51_PAD_SD1_DATA2__SD1_DATA2, PAD_CTL_DSE_MAX |
447 PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
448 NEW_PAD_CTRL(MX51_PAD_SD1_DATA3__SD1_DATA3, PAD_CTL_DSE_MAX |
449 PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SRE_FAST),
450 NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_HYS),
451 NEW_PAD_CTRL(MX51_PAD_GPIO1_1__SD1_WP, PAD_CTL_HYS),
454 imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
456 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
457 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
461 void lcd_enable(void)
463 static const iomux_v3_cfg_t lcd_pads[] = {
464 MX51_PAD_DI1_PIN2__DI1_PIN2,
465 MX51_PAD_DI1_PIN3__DI1_PIN3,
470 imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
472 gpio_set_value(IMX_GPIO_NR(1, 2), 1);
473 imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_2__GPIO1_2,
476 ret = ipuv3_fb_init(&nec_nl6448bc26_09c, 0, IPU_PIX_FMT_RGB666);
478 puts("LCD cannot be configured\n");
481 int board_early_init_f(void)
485 init_drive_strength();
487 /* Setup debug led */
488 gpio_direction_output(IMX_GPIO_NR(1, 6), 0);
489 imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6,
490 PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST));
492 /* wait a little while to give the pll time to settle */
505 static void backlight(int on)
508 gpio_set_value(IMX_GPIO_NR(3, 1), 1);
510 gpio_set_value(IMX_GPIO_NR(3, 4), 1);
512 gpio_set_value(IMX_GPIO_NR(3, 1), 0);
513 gpio_set_value(IMX_GPIO_NR(3, 4), 0);
519 /* address of boot parameters */
520 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
529 int board_late_init(void)
533 reset_peripherals(1);
535 reset_peripherals(0);
538 /* Early revisions require a second reset */
539 #ifdef CONFIG_VISION2_HW_1_0
540 reset_peripherals(1);
542 reset_peripherals(0);
550 * Do not overwrite the console
551 * Use always serial for U-Boot console
553 int overwrite_console(void)
560 puts("Board: TTControl Vision II CPU V\n");
565 int do_vision_lcd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
570 return cmd_usage(cmdtp);
572 on = (strcmp(argv[1], "on") == 0);
579 lcdbl, CONFIG_SYS_MAXARGS, 1, do_vision_lcd,