3 * Stefano Babic DENX Software Engineering sbabic@denx.de.
6 * Klaus Steinhammer TTECH Control Gmbh kst@tttech.com
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not write to the Free Software
23 * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
26 * Refer doc/README.imximage for more details about how-to configure
27 * and create imximage boot image
29 * The syntax is taken as close as possible with the kwbimage
33 * Boot Device : one of
34 * spi, nand, onenand, sd
39 * Device Configuration Data (DCD)
41 * Each entry must have the format:
42 * Addr-type Address Value
45 * Addr-type register length (1,2 or 4 bytes)
46 * Address absolute address of the register
47 * value value to be stored in the register
51 * #######################
52 * ### Disable WDOG ###
53 * #######################
55 DATA 2 0x73f98000 0x30
58 * #######################
60 * #######################
62 /* CCM: CBMCR - ddr_clk_sel: axi_b (133MHz) */
63 DATA 4 0x73FD4018 0x000024C0
65 /* DOUBLE SPI CLK (13MHz->26 MHz Clock) */
66 DATA 4 0x73FD4038 0x2010241
68 /* IOMUXC_SW_PAD_CTL_PAD_CSPI1_MOSI HYS_ENABLE | DRV_MAX | SRE_FAST */
69 DATA 4 0x73fa8600 0x00000107
70 /* IOMUXC_SW_PAD_CTL_PAD_CSPI1_MISO HYS_ENABLE | DRV_MAX | SRE_FAST */
71 DATA 4 0x73fa8604 0x00000107
72 /* IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS0 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST */
73 DATA 4 0x73fa8608 0x00000187
74 /* IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS1 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST */
75 DATA 4 0x73fa860c 0x00000187
76 /* IOMUXC_SW_PAD_CTL_PAD_CSPI1_SCLK HYS_ENABLE | DRV_MAX | SRE_FAST */
77 DATA 4 0x73fa8614 0x00000107
78 /* IOMUXC_SW_PAD_CTL_PAD_DI1_PIN11 HYS_ENABLE | DRV_MAX | SRE_FAST (CSPI1_SS2) */
79 DATA 4 0x73fa86a8 0x00000187
82 * #######################
83 * ### Settings IOMUXC ###
84 * #######################
87 * DDR IOMUX configuration
88 * Control, Data, Address pads are in their default state: HIGH DS, FAST SR.
89 * IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK MAX DS
91 DATA 4 0x73fa84b8 0x000000e7
92 /* PVTC MAX (at GPC, PGR reg) */
93 /* DATA 4 0x73FD8004 0x1fc00000 */
95 /* DQM0 DS high slew rate slow */
96 DATA 4 0x73fa84d4 0x000000e4
97 /* DQM1 DS high slew rate slow */
98 DATA 4 0x73fa84d8 0x000000e4
99 /* DQM2 DS high slew rate slow */
100 DATA 4 0x73fa84dc 0x000000e4
101 /* DQM3 DS high slew rate slow */
102 DATA 4 0x73fa84e0 0x000000e4
104 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 DS high & SLEW slow */
105 DATA 4 0x73fa84bc 0x000000c4
106 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 DS high & SLEW slow */
107 DATA 4 0x73fa84c0 0x000000c4
108 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 DS high & SLEW slow */
109 DATA 4 0x73fa84c4 0x000000c4
110 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 DS high & SLEW slow */
111 DATA 4 0x73fa84c8 0x000000c4
114 DATA 4 0x73fa88a4 0x00000004
116 DATA 4 0x73fa88ac 0x00000004
118 DATA 4 0x73fa88b8 0x00000004
120 DATA 4 0x73fa882c 0x00000004
122 /* DRAM_DATA B0 slew rate */
123 DATA 4 0x73fa8878 0x00000000
124 /* DRAM_DATA B1 slew rate */
125 DATA 4 0x73fa8880 0x00000000
126 /* DRAM_DATA B2 slew rate */
127 DATA 4 0x73fa888c 0x00000000
128 /* DRAM_DATA B3 slew rate */
129 DATA 4 0x73fa889c 0x00000000
132 * #######################
133 * ### Configure SDRAM ###
134 * #######################
138 /* ####################### */
140 /* ESDCTL0: Enable controller */
141 DATA 4 0x83fd9000 0x83220000
143 /* Init DRAM on CS0 /
144 /* ESDSCR: Precharge command */
145 DATA 4 0x83fd9014 0x04008008
146 /* ESDSCR: Refresh command */
147 DATA 4 0x83fd9014 0x00008010
148 /* ESDSCR: Refresh command */
149 DATA 4 0x83fd9014 0x00008010
150 /* ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8) */
151 DATA 4 0x83fd9014 0x00338018
152 /* ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51) */
153 DATA 4 0x83fd9014 0x0020801a
155 DATA 4 0x83fd9014 0x00008000
157 /* ESDSCR: EMR with full Drive strength */
158 /* DATA 4 0x83fd9014 0x0000801a */
160 /* ESDCTL0: 14 ROW, 10 COL, 32Bit, SREF=8 */
161 DATA 4 0x83fd9000 0xC3220000
164 * ESDCFG0: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks
165 * tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks
166 * DATA 4 0x83fd9004 0xC33574AA
170 * ESDCFG0: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks
171 * tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
172 * DATA 4 0x83FD9004 0x101564a8
176 * ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks
177 * tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
179 DATA 4 0x83FD9004 0x704564a8
181 /* ESDMISC: AP=10, Bank interleaving on, MIF3 en, RALAT=2 */
182 DATA 4 0x83fd9010 0x000a1700
185 /* ####################### */
187 /* ESDCTL1: Enable controller */
188 DATA 4 0x83fd9008 0x83220000
190 /* Init DRAM on CS1 */
191 /* ESDSCR: Precharge command */
192 DATA 4 0x83fd9014 0x0400800c
193 /* ESDSCR: Refresh command */
194 DATA 4 0x83fd9014 0x00008014
195 /* ESDSCR: Refresh command */
196 DATA 4 0x83fd9014 0x00008014
197 /* ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8) */
198 DATA 4 0x83fd9014 0x0033801c
199 /* ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51) */
200 DATA 4 0x83fd9014 0x0020801e
202 DATA 4 0x83fd9014 0x00008004
204 /* ESDCTL1: 14 ROW, 10 COL, 32Bit, SREF=8 */
205 DATA 4 0x83fd9008 0xC3220000
207 * ESDCFG1: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks
208 * tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks
209 * DATA 4 0x83fd900c 0xC33574AA
213 * ESDCFG1: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks
214 * tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
215 * DATA 4 0x83FD900C 0x101564a8
219 * ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks
220 * tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
222 DATA 4 0x83FD900C 0x704564a8
224 /* ESDSCR (mDRAM configuration finished) */
225 DATA 4 0x83FD9014 0x00000004
227 /* ESDSCR - clear "configuration request" bit */
228 DATA 4 0x83fd9014 0x00000000