3 * Stefano Babic DENX Software Engineering sbabic@denx.de.
6 * Klaus Steinhammer TTECH Control Gmbh kst@tttech.com
8 * SPDX-License-Identifier: GPL-2.0+
10 * Refer doc/README.imximage for more details about how-to configure
11 * and create imximage boot image
13 * The syntax is taken as close as possible with the kwbimage
17 * Boot Device : one of
18 * spi, nand, onenand, sd
23 * Device Configuration Data (DCD)
25 * Each entry must have the format:
26 * Addr-type Address Value
29 * Addr-type register length (1,2 or 4 bytes)
30 * Address absolute address of the register
31 * value value to be stored in the register
35 * #######################
36 * ### Disable WDOG ###
37 * #######################
39 DATA 2 0x73f98000 0x30
42 * #######################
44 * #######################
46 /* CCM: CBMCR - ddr_clk_sel: axi_b (133MHz) */
47 DATA 4 0x73FD4018 0x000024C0
49 /* DOUBLE SPI CLK (13MHz->26 MHz Clock) */
50 DATA 4 0x73FD4038 0x2010241
52 /* IOMUXC_SW_PAD_CTL_PAD_CSPI1_MOSI HYS_ENABLE | DRV_MAX | SRE_FAST */
53 DATA 4 0x73fa8600 0x00000107
54 /* IOMUXC_SW_PAD_CTL_PAD_CSPI1_MISO HYS_ENABLE | DRV_MAX | SRE_FAST */
55 DATA 4 0x73fa8604 0x00000107
56 /* IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS0 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST */
57 DATA 4 0x73fa8608 0x00000187
58 /* IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS1 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST */
59 DATA 4 0x73fa860c 0x00000187
60 /* IOMUXC_SW_PAD_CTL_PAD_CSPI1_SCLK HYS_ENABLE | DRV_MAX | SRE_FAST */
61 DATA 4 0x73fa8614 0x00000107
62 /* IOMUXC_SW_PAD_CTL_PAD_DI1_PIN11 HYS_ENABLE | DRV_MAX | SRE_FAST (CSPI1_SS2) */
63 DATA 4 0x73fa86a8 0x00000187
66 * #######################
67 * ### Settings IOMUXC ###
68 * #######################
71 * DDR IOMUX configuration
72 * Control, Data, Address pads are in their default state: HIGH DS, FAST SR.
73 * IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK MAX DS
75 DATA 4 0x73fa84b8 0x000000e7
76 /* PVTC MAX (at GPC, PGR reg) */
77 /* DATA 4 0x73FD8004 0x1fc00000 */
79 /* DQM0 DS high slew rate slow */
80 DATA 4 0x73fa84d4 0x000000e4
81 /* DQM1 DS high slew rate slow */
82 DATA 4 0x73fa84d8 0x000000e4
83 /* DQM2 DS high slew rate slow */
84 DATA 4 0x73fa84dc 0x000000e4
85 /* DQM3 DS high slew rate slow */
86 DATA 4 0x73fa84e0 0x000000e4
88 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 DS high & SLEW slow */
89 DATA 4 0x73fa84bc 0x000000c4
90 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 DS high & SLEW slow */
91 DATA 4 0x73fa84c0 0x000000c4
92 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 DS high & SLEW slow */
93 DATA 4 0x73fa84c4 0x000000c4
94 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 DS high & SLEW slow */
95 DATA 4 0x73fa84c8 0x000000c4
98 DATA 4 0x73fa88a4 0x00000004
100 DATA 4 0x73fa88ac 0x00000004
102 DATA 4 0x73fa88b8 0x00000004
104 DATA 4 0x73fa882c 0x00000004
106 /* DRAM_DATA B0 slew rate */
107 DATA 4 0x73fa8878 0x00000000
108 /* DRAM_DATA B1 slew rate */
109 DATA 4 0x73fa8880 0x00000000
110 /* DRAM_DATA B2 slew rate */
111 DATA 4 0x73fa888c 0x00000000
112 /* DRAM_DATA B3 slew rate */
113 DATA 4 0x73fa889c 0x00000000
116 * #######################
117 * ### Configure SDRAM ###
118 * #######################
122 /* ####################### */
124 /* ESDCTL0: Enable controller */
125 DATA 4 0x83fd9000 0x83220000
127 /* Init DRAM on CS0 /
128 /* ESDSCR: Precharge command */
129 DATA 4 0x83fd9014 0x04008008
130 /* ESDSCR: Refresh command */
131 DATA 4 0x83fd9014 0x00008010
132 /* ESDSCR: Refresh command */
133 DATA 4 0x83fd9014 0x00008010
134 /* ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8) */
135 DATA 4 0x83fd9014 0x00338018
136 /* ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51) */
137 DATA 4 0x83fd9014 0x0020801a
139 DATA 4 0x83fd9014 0x00008000
141 /* ESDSCR: EMR with full Drive strength */
142 /* DATA 4 0x83fd9014 0x0000801a */
144 /* ESDCTL0: 14 ROW, 10 COL, 32Bit, SREF=8 */
145 DATA 4 0x83fd9000 0xC3220000
148 * ESDCFG0: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks
149 * tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks
150 * DATA 4 0x83fd9004 0xC33574AA
154 * ESDCFG0: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks
155 * tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
156 * DATA 4 0x83FD9004 0x101564a8
160 * ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks
161 * tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
163 DATA 4 0x83FD9004 0x704564a8
165 /* ESDMISC: AP=10, Bank interleaving on, MIF3 en, RALAT=2 */
166 DATA 4 0x83fd9010 0x000a1700
169 /* ####################### */
171 /* ESDCTL1: Enable controller */
172 DATA 4 0x83fd9008 0x83220000
174 /* Init DRAM on CS1 */
175 /* ESDSCR: Precharge command */
176 DATA 4 0x83fd9014 0x0400800c
177 /* ESDSCR: Refresh command */
178 DATA 4 0x83fd9014 0x00008014
179 /* ESDSCR: Refresh command */
180 DATA 4 0x83fd9014 0x00008014
181 /* ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8) */
182 DATA 4 0x83fd9014 0x0033801c
183 /* ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51) */
184 DATA 4 0x83fd9014 0x0020801e
186 DATA 4 0x83fd9014 0x00008004
188 /* ESDCTL1: 14 ROW, 10 COL, 32Bit, SREF=8 */
189 DATA 4 0x83fd9008 0xC3220000
191 * ESDCFG1: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks
192 * tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks
193 * DATA 4 0x83fd900c 0xC33574AA
197 * ESDCFG1: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks
198 * tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
199 * DATA 4 0x83FD900C 0x101564a8
203 * ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks
204 * tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
206 DATA 4 0x83FD900C 0x704564a8
208 /* ESDSCR (mDRAM configuration finished) */
209 DATA 4 0x83FD9014 0x00000004
211 /* ESDSCR - clear "configuration request" bit */
212 DATA 4 0x83fd9014 0x00000000