2 * (C) Copyright 2000-2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 DECLARE_GLOBAL_DATA_PTR;
36 static long int dram_size (long int, long int *, long int);
38 #define _NOT_USED_ 0xFFFFFFFF
40 /* UPM initialization table for SDRAM: 40, 50, 66 MHz CLKOUT @ CAS latency 2, tWR=2 */
41 const uint sdram_table[] =
44 * Single Read. (Offset 0 in UPMA RAM)
46 0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00,
47 0x1FF5FC47, /* last */
49 * SDRAM Initialization (offset 5 in UPMA RAM)
51 * This is no UPM entry point. The following definition uses
52 * the remaining space to establish an initialization
53 * sequence, which is executed by a RUN command.
56 0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */
58 * Burst Read. (Offset 8 in UPMA RAM)
60 0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00,
61 0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */
62 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
63 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
65 * Single Write. (Offset 18 in UPMA RAM)
67 0x1F0DFC04, 0xEEABBC00, 0x11B77C04, 0xEFFAFC44,
68 0x1FF5FC47, /* last */
69 _NOT_USED_, _NOT_USED_, _NOT_USED_,
71 * Burst Write. (Offset 20 in UPMA RAM)
73 0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
74 0xF0AFFC00, 0xF0AFFC04, 0xE1BAFC44, 0x1FF5FC47, /* last */
75 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
76 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
78 * Refresh (Offset 30 in UPMA RAM)
80 0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
81 0xFFFFFC84, 0xFFFFFC07, /* last */
82 _NOT_USED_, _NOT_USED_,
83 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
85 * Exception. (Offset 3c in UPMA RAM)
87 0xFFFFFC07, /* last */
88 _NOT_USED_, _NOT_USED_, _NOT_USED_,
91 /* ------------------------------------------------------------------------- */
95 * Check Board Identity:
97 * Test TQ ID string (TQM8xx...)
98 * If present, check for "L" type (no second DRAM bank),
99 * otherwise "L" type is assumed as default.
101 * Set board_type to 'L' for "L" type, 'M' for "M" type, 0 else.
104 int checkboard (void)
106 char *s = getenv ("serial#");
110 if (!s || strncmp (s, "TQM8", 4)) {
111 puts ("### No HW ID - assuming TQM8xxL\n");
115 if ((*(s + 6) == 'L')) { /* a TQM8xxL type */
116 gd->board_type = 'L';
119 if ((*(s + 6) == 'M')) { /* a TQM8xxM type */
120 gd->board_type = 'M';
123 if ((*(s + 6) == 'D')) { /* a TQM885D type */
124 gd->board_type = 'D';
132 #ifdef CONFIG_VIRTLAB2
133 puts (" (Virtlab2)");
140 /* ------------------------------------------------------------------------- */
142 long int initdram (int board_type)
144 volatile immap_t *immap = (immap_t *) CFG_IMMR;
145 volatile memctl8xx_t *memctl = &immap->im_memctl;
146 long int size8, size9, size10;
147 long int size_b0 = 0;
148 long int size_b1 = 0;
150 upmconfig (UPMA, (uint *) sdram_table,
151 sizeof (sdram_table) / sizeof (uint));
154 * Preliminary prescaler for refresh (depends on number of
155 * banks): This value is selected for four cycles every 62.4 us
156 * with two SDRAM banks or four cycles every 31.2 us with one
157 * bank. It will be adjusted after memory sizing.
159 memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
162 * The following value is used as an address (i.e. opcode) for
163 * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
164 * the port size is 32bit the SDRAM does NOT "see" the lower two
165 * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
168 * | | | | +- Burst Length = 4
169 * | | | +----- Burst Type = Sequential
170 * | | +------- CAS Latency = 2
171 * | +----------- Operating Mode = Standard
172 * +-------------- Write Burst Mode = Programmed Burst Length
174 memctl->memc_mar = 0x00000088;
177 * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
178 * preliminary addresses - these have to be modified after the
179 * SDRAM size has been determined.
181 memctl->memc_or2 = CFG_OR2_PRELIM;
182 memctl->memc_br2 = CFG_BR2_PRELIM;
184 #ifndef CONFIG_CAN_DRIVER
185 if ((board_type != 'L') &&
186 (board_type != 'M') &&
187 (board_type != 'D') ) { /* only one SDRAM bank on L, M and D modules */
188 memctl->memc_or3 = CFG_OR3_PRELIM;
189 memctl->memc_br3 = CFG_BR3_PRELIM;
191 #endif /* CONFIG_CAN_DRIVER */
193 memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
197 /* perform SDRAM initializsation sequence */
199 memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */
201 memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */
204 #ifndef CONFIG_CAN_DRIVER
205 if ((board_type != 'L') &&
206 (board_type != 'M') &&
207 (board_type != 'D') ) { /* only one SDRAM bank on L, M and D modules */
208 memctl->memc_mcr = 0x80006105; /* SDRAM bank 1 */
210 memctl->memc_mcr = 0x80006230; /* SDRAM bank 1 - execute twice */
213 #endif /* CONFIG_CAN_DRIVER */
215 memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
220 * Check Bank 0 Memory Size for re-configuration
224 size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
225 debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size8 >> 20);
232 size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
233 debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size9 >> 20);
237 #if defined(CFG_MAMR_10COL)
241 size10 = dram_size (CFG_MAMR_10COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
242 debug ("SDRAM Bank 0 in 10 column mode: %ld MB\n", size10 >> 20);
245 #endif /* CFG_MAMR_10COL */
247 if ((size8 < size10) && (size9 < size10)) {
249 } else if ((size8 < size9) && (size10 < size9)) {
251 memctl->memc_mamr = CFG_MAMR_9COL;
255 memctl->memc_mamr = CFG_MAMR_8COL;
258 debug ("SDRAM Bank 0: %ld MB\n", size_b0 >> 20);
260 #ifndef CONFIG_CAN_DRIVER
261 if ((board_type != 'L') &&
262 (board_type != 'M') &&
263 (board_type != 'D') ) { /* only one SDRAM bank on L, M and D modules */
265 * Check Bank 1 Memory Size
266 * use current column settings
267 * [9 column SDRAM may also be used in 8 column mode,
268 * but then only half the real size will be used.]
270 size_b1 = dram_size (memctl->memc_mamr, (long int *)SDRAM_BASE3_PRELIM,
272 debug ("SDRAM Bank 1: %ld MB\n", size_b1 >> 20);
276 #endif /* CONFIG_CAN_DRIVER */
281 * Adjust refresh rate depending on SDRAM type, both banks
282 * For types > 128 MBit leave it at the current (fast) rate
284 if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) {
285 /* reduce to 15.6 us (62.4 us / quad) */
286 memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
291 * Final mapping: map bigger bank first
293 if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */
295 memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
296 memctl->memc_br3 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
300 * Position Bank 0 immediately above Bank 1
302 memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
303 memctl->memc_br2 = ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
313 memctl->memc_br2 = 0;
315 /* adjust refresh rate depending on SDRAM type, one bank */
316 reg = memctl->memc_mptpr;
317 reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
318 memctl->memc_mptpr = reg;
321 } else { /* SDRAM Bank 0 is bigger - map first */
323 memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
325 (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
329 * Position Bank 1 immediately above Bank 0
332 ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
334 ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
339 #ifndef CONFIG_CAN_DRIVER
345 memctl->memc_br3 = 0;
346 #endif /* CONFIG_CAN_DRIVER */
348 /* adjust refresh rate depending on SDRAM type, one bank */
349 reg = memctl->memc_mptpr;
350 reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
351 memctl->memc_mptpr = reg;
357 #ifdef CONFIG_CAN_DRIVER
358 /* UPM initialization for CAN @ CLKOUT <= 66 MHz */
360 /* Initialize OR3 / BR3 */
361 memctl->memc_or3 = CFG_OR3_CAN;
362 memctl->memc_br3 = CFG_BR3_CAN;
364 /* Initialize MBMR */
365 memctl->memc_mbmr = MBMR_GPL_B4DIS; /* GPL_B4 ouput line Disable */
367 /* Initialize UPMB for CAN: single read */
368 memctl->memc_mdr = 0xFFFFCC04;
369 memctl->memc_mcr = 0x0100 | UPMB;
371 memctl->memc_mdr = 0x0FFFD004;
372 memctl->memc_mcr = 0x0101 | UPMB;
374 memctl->memc_mdr = 0x0FFFC000;
375 memctl->memc_mcr = 0x0102 | UPMB;
377 memctl->memc_mdr = 0x3FFFC004;
378 memctl->memc_mcr = 0x0103 | UPMB;
380 memctl->memc_mdr = 0xFFFFDC07;
381 memctl->memc_mcr = 0x0104 | UPMB;
383 /* Initialize UPMB for CAN: single write */
384 memctl->memc_mdr = 0xFFFCCC04;
385 memctl->memc_mcr = 0x0118 | UPMB;
387 memctl->memc_mdr = 0xCFFCDC04;
388 memctl->memc_mcr = 0x0119 | UPMB;
390 memctl->memc_mdr = 0x3FFCC000;
391 memctl->memc_mcr = 0x011A | UPMB;
393 memctl->memc_mdr = 0xFFFCC004;
394 memctl->memc_mcr = 0x011B | UPMB;
396 memctl->memc_mdr = 0xFFFDC405;
397 memctl->memc_mcr = 0x011C | UPMB;
398 #endif /* CONFIG_CAN_DRIVER */
400 #ifdef CONFIG_ISP1362_USB
401 /* Initialize OR5 / BR5 */
402 memctl->memc_or5 = CFG_OR5_ISP1362;
403 memctl->memc_br5 = CFG_BR5_ISP1362;
404 #endif /* CONFIG_ISP1362_USB */
407 return (size_b0 + size_b1);
410 /* ------------------------------------------------------------------------- */
413 * Check memory range for valid RAM. A simple memory test determines
414 * the actually available RAM size between addresses `base' and
415 * `base + maxsize'. Some (not all) hardware errors are detected:
416 * - short between address lines
417 * - short between data lines
420 static long int dram_size (long int mamr_value, long int *base, long int maxsize)
422 volatile immap_t *immap = (immap_t *) CFG_IMMR;
423 volatile memctl8xx_t *memctl = &immap->im_memctl;
425 memctl->memc_mamr = mamr_value;
427 return (get_ram_size(base, maxsize));
430 /* ------------------------------------------------------------------------- */
432 #ifdef CONFIG_PS2MULT
435 #define BASE_BAUD ( 1843200 / 16 )
436 struct serial_state rs_table[] = {
437 { BASE_BAUD, 4, (void*)0xec140000 },
438 { BASE_BAUD, 2, (void*)0xec150000 },
439 { BASE_BAUD, 6, (void*)0xec160000 },
440 { BASE_BAUD, 10, (void*)0xec170000 },
443 #ifdef CONFIG_BOARD_EARLY_INIT_R
444 int board_early_init_r (void)
446 ps2mult_early_init();
450 #endif /* CONFIG_HMI10 */
452 #endif /* CONFIG_PS2MULT */
454 /* ---------------------------------------------------------------------------- */
455 /* HMI10 specific stuff */
456 /* ---------------------------------------------------------------------------- */
459 int misc_init_r (void)
461 # ifdef CONFIG_IDE_LED
462 volatile immap_t *immap = (immap_t *) CFG_IMMR;
464 /* Configure PA15 as output port */
465 immap->im_ioport.iop_padir |= 0x0001;
466 immap->im_ioport.iop_paodr |= 0x0001;
467 immap->im_ioport.iop_papar &= ~0x0001;
468 immap->im_ioport.iop_padat &= ~0x0001; /* turn it off */
473 # ifdef CONFIG_IDE_LED
474 void ide_led (uchar led, uchar status)
476 volatile immap_t *immap = (immap_t *) CFG_IMMR;
478 /* We have one led for both pcmcia slots */
479 if (status) { /* led on */
480 immap->im_ioport.iop_padat |= 0x0001;
482 immap->im_ioport.iop_padat &= ~0x0001;
486 #endif /* CONFIG_HMI10 */
488 /* ---------------------------------------------------------------------------- */
489 /* NSCU specific stuff */
490 /* ---------------------------------------------------------------------------- */
493 int misc_init_r (void)
495 volatile immap_t *immr = (immap_t *) CFG_IMMR;
497 /* wake up ethernet module */
498 immr->im_ioport.iop_pcpar &= ~0x0004; /* GPIO pin */
499 immr->im_ioport.iop_pcdir |= 0x0004; /* output */
500 immr->im_ioport.iop_pcso &= ~0x0004; /* for clarity */
501 immr->im_ioport.iop_pcdat |= 0x0004; /* enable */
505 #endif /* CONFIG_NSCU */
507 /* ---------------------------------------------------------------------------- */
508 /* TK885D specific initializaion */
509 /* ---------------------------------------------------------------------------- */
512 int last_stage_init(void)
514 const unsigned char phy[] = {CONFIG_FEC1_PHY, CONFIG_FEC2_PHY};
520 /* Without this delay 0xff is read from the UART buffer later in
521 * abortboot() and autoboot is aborted */
523 while (tstc() && i--)
526 /* Check if auto-negotiation is prohibited */
527 s = getenv("phy_auto_nego");
529 if (!s || !strcmp(s, "on"))
530 /* Nothing to do - autonegotiation by default */
533 for (i = 0; i < 2; i++) {
534 ret = miiphy_read("FEC ETHERNET", phy[i], PHY_BMCR, ®);
536 printf("Cannot read BMCR on PHY %d\n", phy[i]);
539 /* Auto-negotiation off, hard set full duplex, 100Mbps */
540 ret = miiphy_write("FEC ETHERNET", phy[i],
541 PHY_BMCR, (reg | PHY_BMCR_100MB |
542 PHY_BMCR_DPLX) & ~PHY_BMCR_AUTON);
544 printf("Cannot write BMCR on PHY %d\n", phy[i]);
554 /* ------------------------------------------------------------------------- */