2 * (C) Copyright 2000, 2001, 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 /* ------------------------------------------------------------------------- */
29 static long int dram_size (long int, long int *, long int);
31 /* ------------------------------------------------------------------------- */
33 #define _NOT_USED_ 0xFFFFFFFF
35 const uint sdram_table[] =
38 * Single Read. (Offset 0 in UPMA RAM)
40 0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00,
41 0x1FF5FC47, /* last */
43 * SDRAM Initialization (offset 5 in UPMA RAM)
45 * This is no UPM entry point. The following definition uses
46 * the remaining space to establish an initialization
47 * sequence, which is executed by a RUN command.
50 0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */
52 * Burst Read. (Offset 8 in UPMA RAM)
54 0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00,
55 0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */
56 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
57 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
59 * Single Write. (Offset 18 in UPMA RAM)
61 0x1F0DFC04, 0xEEABBC00, 0x01B27C04, 0x1FF5FC47, /* last */
62 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
64 * Burst Write. (Offset 20 in UPMA RAM)
66 0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
67 0xF0AFFC00, 0xE1BAFC04, 0x1FF5FC47, /* last */
69 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
70 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
72 * Refresh (Offset 30 in UPMA RAM)
74 0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
75 0xFFFFFC84, 0xFFFFFC07, /* last */
76 _NOT_USED_, _NOT_USED_,
77 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
79 * Exception. (Offset 3c in UPMA RAM)
81 0x7FFFFC07, /* last */
82 _NOT_USED_, _NOT_USED_, _NOT_USED_,
85 /* ------------------------------------------------------------------------- */
89 * Check Board Identity:
91 * Test TQ ID string (TQM8xx...)
92 * If present, check for "L" type (no second DRAM bank),
93 * otherwise "L" type is assumed as default.
95 * Set board_type to 'L' for "L" type, 0 else.
100 DECLARE_GLOBAL_DATA_PTR;
102 unsigned char *s = getenv ("serial#");
106 if (!s || strncmp (s, "TQM8", 4)) {
107 puts ("### No HW ID - assuming TQM8xxL\n");
111 if ((*(s + 6) == 'L')) { /* a TQM8xxL type */
112 gd->board_type = 'L';
125 /* ------------------------------------------------------------------------- */
127 long int initdram (int board_type)
129 volatile immap_t *immap = (immap_t *) CFG_IMMR;
130 volatile memctl8xx_t *memctl = &immap->im_memctl;
131 long int size8, size9;
132 long int size_b0 = 0;
133 long int size_b1 = 0;
135 upmconfig (UPMA, (uint *) sdram_table,
136 sizeof (sdram_table) / sizeof (uint));
139 * Preliminary prescaler for refresh (depends on number of
140 * banks): This value is selected for four cycles every 62.4 us
141 * with two SDRAM banks or four cycles every 31.2 us with one
142 * bank. It will be adjusted after memory sizing.
144 memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
147 * The following value is used as an address (i.e. opcode) for
148 * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
149 * the port size is 32bit the SDRAM does NOT "see" the lower two
150 * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
153 * | | | | +- Burst Length = 4
154 * | | | +----- Burst Type = Sequential
155 * | | +------- CAS Latency = 2
156 * | +----------- Operating Mode = Standard
157 * +-------------- Write Burst Mode = Programmed Burst Length
159 memctl->memc_mar = 0x00000088;
162 * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
163 * preliminary addresses - these have to be modified after the
164 * SDRAM size has been determined.
166 memctl->memc_or2 = CFG_OR2_PRELIM;
167 memctl->memc_br2 = CFG_BR2_PRELIM;
169 #ifndef CONFIG_CAN_DRIVER
170 if (board_type != 'L') { /* "L" type boards have only one bank SDRAM */
171 memctl->memc_or3 = CFG_OR3_PRELIM;
172 memctl->memc_br3 = CFG_BR3_PRELIM;
174 #endif /* CONFIG_CAN_DRIVER */
176 memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
180 /* perform SDRAM initializsation sequence */
182 memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */
184 memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */
187 #ifndef CONFIG_CAN_DRIVER
188 if (board_type != 'L') { /* "L" type boards have only one bank SDRAM */
189 memctl->memc_mcr = 0x80006105; /* SDRAM bank 1 */
191 memctl->memc_mcr = 0x80006230; /* SDRAM bank 1 - execute twice */
194 #endif /* CONFIG_CAN_DRIVER */
196 memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
201 * Check Bank 0 Memory Size for re-configuration
205 size8 = dram_size (CFG_MAMR_8COL, (ulong *) SDRAM_BASE2_PRELIM,
213 size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE2_PRELIM,
216 if (size8 < size9) { /* leave configuration at 9 columns */
218 /* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
219 } else { /* back to 8 columns */
221 memctl->memc_mamr = CFG_MAMR_8COL;
223 /* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
226 #ifndef CONFIG_CAN_DRIVER
227 if (board_type != 'L') { /* "L" type boards have only one bank SDRAM */
229 * Check Bank 1 Memory Size
230 * use current column settings
231 * [9 column SDRAM may also be used in 8 column mode,
232 * but then only half the real size will be used.]
235 dram_size (memctl->memc_mamr, (ulong *) SDRAM_BASE3_PRELIM,
237 /* debug ("SDRAM Bank 1: %ld MB\n", size8 >> 20); */
241 #endif /* CONFIG_CAN_DRIVER */
246 * Adjust refresh rate depending on SDRAM type, both banks
247 * For types > 128 MBit leave it at the current (fast) rate
249 if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) {
250 /* reduce to 15.6 us (62.4 us / quad) */
251 memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
256 * Final mapping: map bigger bank first
258 if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */
260 memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
262 (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
266 * Position Bank 0 immediately above Bank 1
269 ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
271 ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
281 memctl->memc_br2 = 0;
283 /* adjust refresh rate depending on SDRAM type, one bank */
284 reg = memctl->memc_mptpr;
285 reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
286 memctl->memc_mptpr = reg;
289 } else { /* SDRAM Bank 0 is bigger - map first */
291 memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
293 (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
297 * Position Bank 1 immediately above Bank 0
300 ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
302 ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
307 #ifndef CONFIG_CAN_DRIVER
313 memctl->memc_br3 = 0;
314 #endif /* CONFIG_CAN_DRIVER */
316 /* adjust refresh rate depending on SDRAM type, one bank */
317 reg = memctl->memc_mptpr;
318 reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
319 memctl->memc_mptpr = reg;
325 #ifdef CONFIG_CAN_DRIVER
326 /* Initialize OR3 / BR3 */
327 memctl->memc_or3 = CFG_OR3_CAN;
328 memctl->memc_br3 = CFG_BR3_CAN;
330 /* Initialize MBMR */
331 memctl->memc_mbmr = MAMR_GPL_B4DIS; /* GPL_B4 ouput line Disable */
333 /* Initialize UPMB for CAN: single read */
334 memctl->memc_mdr = 0xFFFFC004;
335 memctl->memc_mcr = 0x0100 | UPMB;
337 memctl->memc_mdr = 0x0FFFD004;
338 memctl->memc_mcr = 0x0101 | UPMB;
340 memctl->memc_mdr = 0x0FFFC000;
341 memctl->memc_mcr = 0x0102 | UPMB;
343 memctl->memc_mdr = 0x3FFFC004;
344 memctl->memc_mcr = 0x0103 | UPMB;
346 memctl->memc_mdr = 0xFFFFDC05;
347 memctl->memc_mcr = 0x0104 | UPMB;
349 /* Initialize UPMB for CAN: single write */
350 memctl->memc_mdr = 0xFFFCC004;
351 memctl->memc_mcr = 0x0118 | UPMB;
353 memctl->memc_mdr = 0xCFFCD004;
354 memctl->memc_mcr = 0x0119 | UPMB;
356 memctl->memc_mdr = 0x0FFCC000;
357 memctl->memc_mcr = 0x011A | UPMB;
359 memctl->memc_mdr = 0x7FFCC004;
360 memctl->memc_mcr = 0x011B | UPMB;
362 memctl->memc_mdr = 0xFFFDCC05;
363 memctl->memc_mcr = 0x011C | UPMB;
364 #endif /* CONFIG_CAN_DRIVER */
367 return (size_b0 + size_b1);
370 /* ------------------------------------------------------------------------- */
373 * Check memory range for valid RAM. A simple memory test determines
374 * the actually available RAM size between addresses `base' and
375 * `base + maxsize'. Some (not all) hardware errors are detected:
376 * - short between address lines
377 * - short between data lines
380 static long int dram_size (long int mamr_value, long int *base,
383 volatile immap_t *immap = (immap_t *) CFG_IMMR;
384 volatile memctl8xx_t *memctl = &immap->im_memctl;
385 volatile long int *addr;
387 ulong save[32]; /* to make test non-destructive */
390 memctl->memc_mamr = mamr_value;
392 for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
393 addr = base + cnt; /* pointer arith! */
399 /* write 0 to base address */
404 /* check at base address */
405 if ((val = *addr) != 0) {
410 for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
411 addr = base + cnt; /* pointer arith! */
417 return (cnt * sizeof (long));
423 /* ------------------------------------------------------------------------- */