2 * (C) Copyright 2000-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 /* ------------------------------------------------------------------------- */
36 static long int dram_size (long int, long int *, long int);
38 /* ------------------------------------------------------------------------- */
40 #define _NOT_USED_ 0xFFFFFFFF
42 const uint sdram_table[] =
45 * Single Read. (Offset 0 in UPMA RAM)
47 0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00,
48 0x1FF5FC47, /* last */
50 * SDRAM Initialization (offset 5 in UPMA RAM)
52 * This is no UPM entry point. The following definition uses
53 * the remaining space to establish an initialization
54 * sequence, which is executed by a RUN command.
57 0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */
59 * Burst Read. (Offset 8 in UPMA RAM)
61 0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00,
62 0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */
63 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
64 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
66 * Single Write. (Offset 18 in UPMA RAM)
68 0x1F0DFC04, 0xEEABBC00, 0x01B27C04, 0x1FF5FC47, /* last */
69 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
71 * Burst Write. (Offset 20 in UPMA RAM)
73 0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
74 0xF0AFFC00, 0xE1BAFC04, 0x1FF5FC47, /* last */
76 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
77 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
79 * Refresh (Offset 30 in UPMA RAM)
81 0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
82 0xFFFFFC84, 0xFFFFFC07, /* last */
83 _NOT_USED_, _NOT_USED_,
84 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
86 * Exception. (Offset 3c in UPMA RAM)
88 0x7FFFFC07, /* last */
89 _NOT_USED_, _NOT_USED_, _NOT_USED_,
92 /* ------------------------------------------------------------------------- */
96 * Check Board Identity:
98 * Test TQ ID string (TQM8xx...)
99 * If present, check for "L" type (no second DRAM bank),
100 * otherwise "L" type is assumed as default.
102 * Set board_type to 'L' for "L" type, 'M' for "M" type, 0 else.
105 int checkboard (void)
107 DECLARE_GLOBAL_DATA_PTR;
109 char *s = getenv ("serial#");
113 if (!s || strncmp (s, "TQM8", 4)) {
114 puts ("### No HW ID - assuming TQM8xxL\n");
118 if ((*(s + 6) == 'L')) { /* a TQM8xxL type */
119 gd->board_type = 'L';
122 if ((*(s + 6) == 'M')) { /* a TQM8xxM type */
123 gd->board_type = 'M';
136 /* ------------------------------------------------------------------------- */
138 long int initdram (int board_type)
140 volatile immap_t *immap = (immap_t *) CFG_IMMR;
141 volatile memctl8xx_t *memctl = &immap->im_memctl;
142 long int size8, size9, size10;
143 long int size_b0 = 0;
144 long int size_b1 = 0;
146 upmconfig (UPMA, (uint *) sdram_table,
147 sizeof (sdram_table) / sizeof (uint));
150 * Preliminary prescaler for refresh (depends on number of
151 * banks): This value is selected for four cycles every 62.4 us
152 * with two SDRAM banks or four cycles every 31.2 us with one
153 * bank. It will be adjusted after memory sizing.
155 memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
158 * The following value is used as an address (i.e. opcode) for
159 * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
160 * the port size is 32bit the SDRAM does NOT "see" the lower two
161 * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
164 * | | | | +- Burst Length = 4
165 * | | | +----- Burst Type = Sequential
166 * | | +------- CAS Latency = 2
167 * | +----------- Operating Mode = Standard
168 * +-------------- Write Burst Mode = Programmed Burst Length
170 memctl->memc_mar = 0x00000088;
173 * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
174 * preliminary addresses - these have to be modified after the
175 * SDRAM size has been determined.
177 memctl->memc_or2 = CFG_OR2_PRELIM;
178 memctl->memc_br2 = CFG_BR2_PRELIM;
180 #ifndef CONFIG_CAN_DRIVER
181 if ((board_type != 'L') &&
182 (board_type != 'M') ) { /* "L" and "M" type boards have only one bank SDRAM */
183 memctl->memc_or3 = CFG_OR3_PRELIM;
184 memctl->memc_br3 = CFG_BR3_PRELIM;
186 #endif /* CONFIG_CAN_DRIVER */
188 memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
192 /* perform SDRAM initializsation sequence */
194 memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */
196 memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */
199 #ifndef CONFIG_CAN_DRIVER
200 if ((board_type != 'L') &&
201 (board_type != 'M') ) { /* "L" and "M" type boards have only one bank SDRAM */
202 memctl->memc_mcr = 0x80006105; /* SDRAM bank 1 */
204 memctl->memc_mcr = 0x80006230; /* SDRAM bank 1 - execute twice */
207 #endif /* CONFIG_CAN_DRIVER */
209 memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
214 * Check Bank 0 Memory Size for re-configuration
218 size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE2_PRELIM,
220 debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size8 >> 20);
227 size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE2_PRELIM,
229 debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size9 >> 20);
233 #if defined(CFG_MAMR_10COL)
237 size10 = dram_size (CFG_MAMR_10COL, (ulong *) SDRAM_BASE2_PRELIM,
239 debug ("SDRAM Bank 0 in 10 column mode: %ld MB\n", size10 >> 20);
242 #endif /* CFG_MAMR_10COL */
244 if ((size8 < size10) && (size9 < size10)) {
246 } else if ((size8 < size9) && (size10 < size9)) {
248 memctl->memc_mamr = CFG_MAMR_9COL;
252 memctl->memc_mamr = CFG_MAMR_8COL;
255 debug ("SDRAM Bank 0: %ld MB\n", size_b0 >> 20);
257 #ifndef CONFIG_CAN_DRIVER
258 if ((board_type != 'L') &&
259 (board_type != 'M') ) { /* "L" and "M" type boards have only one bank SDRAM */
261 * Check Bank 1 Memory Size
262 * use current column settings
263 * [9 column SDRAM may also be used in 8 column mode,
264 * but then only half the real size will be used.]
266 size_b1 = dram_size (memctl->memc_mamr, (long int *)SDRAM_BASE3_PRELIM,
268 debug ("SDRAM Bank 1: %ld MB\n", size_b1 >> 20);
272 #endif /* CONFIG_CAN_DRIVER */
277 * Adjust refresh rate depending on SDRAM type, both banks
278 * For types > 128 MBit leave it at the current (fast) rate
280 if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) {
281 /* reduce to 15.6 us (62.4 us / quad) */
282 memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
287 * Final mapping: map bigger bank first
289 if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */
291 memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
292 memctl->memc_br3 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
296 * Position Bank 0 immediately above Bank 1
298 memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
299 memctl->memc_br2 = ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
309 memctl->memc_br2 = 0;
311 /* adjust refresh rate depending on SDRAM type, one bank */
312 reg = memctl->memc_mptpr;
313 reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
314 memctl->memc_mptpr = reg;
317 } else { /* SDRAM Bank 0 is bigger - map first */
319 memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
321 (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
325 * Position Bank 1 immediately above Bank 0
328 ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
330 ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
335 #ifndef CONFIG_CAN_DRIVER
341 memctl->memc_br3 = 0;
342 #endif /* CONFIG_CAN_DRIVER */
344 /* adjust refresh rate depending on SDRAM type, one bank */
345 reg = memctl->memc_mptpr;
346 reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
347 memctl->memc_mptpr = reg;
353 #ifdef CONFIG_CAN_DRIVER
354 /* Initialize OR3 / BR3 */
355 memctl->memc_or3 = CFG_OR3_CAN;
356 memctl->memc_br3 = CFG_BR3_CAN;
358 /* Initialize MBMR */
359 memctl->memc_mbmr = MBMR_GPL_B4DIS; /* GPL_B4 ouput line Disable */
361 /* Initialize UPMB for CAN: single read */
362 memctl->memc_mdr = 0xFFFFC004;
363 memctl->memc_mcr = 0x0100 | UPMB;
365 memctl->memc_mdr = 0x0FFFD004;
366 memctl->memc_mcr = 0x0101 | UPMB;
368 memctl->memc_mdr = 0x0FFFC000;
369 memctl->memc_mcr = 0x0102 | UPMB;
371 memctl->memc_mdr = 0x3FFFC004;
372 memctl->memc_mcr = 0x0103 | UPMB;
374 memctl->memc_mdr = 0xFFFFDC05;
375 memctl->memc_mcr = 0x0104 | UPMB;
377 /* Initialize UPMB for CAN: single write */
378 memctl->memc_mdr = 0xFFFCC004;
379 memctl->memc_mcr = 0x0118 | UPMB;
381 memctl->memc_mdr = 0xCFFCD004;
382 memctl->memc_mcr = 0x0119 | UPMB;
384 memctl->memc_mdr = 0x0FFCC000;
385 memctl->memc_mcr = 0x011A | UPMB;
387 memctl->memc_mdr = 0x7FFCC004;
388 memctl->memc_mcr = 0x011B | UPMB;
390 memctl->memc_mdr = 0xFFFDCC05;
391 memctl->memc_mcr = 0x011C | UPMB;
392 #endif /* CONFIG_CAN_DRIVER */
394 #ifdef CONFIG_ISP1362_USB
395 /* Initialize OR5 / BR5 */
396 memctl->memc_or5 = CFG_OR5_ISP1362;
397 memctl->memc_br5 = CFG_BR5_ISP1362;
398 #endif /* CONFIG_ISP1362_USB */
401 return (size_b0 + size_b1);
404 /* ------------------------------------------------------------------------- */
407 * Check memory range for valid RAM. A simple memory test determines
408 * the actually available RAM size between addresses `base' and
409 * `base + maxsize'. Some (not all) hardware errors are detected:
410 * - short between address lines
411 * - short between data lines
414 static long int dram_size (long int mamr_value, long int *base, long int maxsize)
416 volatile immap_t *immap = (immap_t *) CFG_IMMR;
417 volatile memctl8xx_t *memctl = &immap->im_memctl;
419 memctl->memc_mamr = mamr_value;
421 return (get_ram_size(base, maxsize));
424 /* ------------------------------------------------------------------------- */
426 #ifdef CONFIG_PS2MULT
429 #define BASE_BAUD ( 1843200 / 16 )
430 struct serial_state rs_table[] = {
431 { BASE_BAUD, 4, (void*)0xec140000 },
432 { BASE_BAUD, 2, (void*)0xec150000 },
433 { BASE_BAUD, 6, (void*)0xec160000 },
434 { BASE_BAUD, 10, (void*)0xec170000 },
437 #ifdef CONFIG_BOARD_EARLY_INIT_R
438 int board_early_init_r (void)
440 ps2mult_early_init();
444 #endif /* CONFIG_HMI10 */
446 #endif /* CONFIG_PS2MULT */
448 /* ---------------------------------------------------------------------------- */
449 /* HMI10 specific stuff */
450 /* ---------------------------------------------------------------------------- */
453 int misc_init_r (void)
455 # ifdef CONFIG_IDE_LED
456 volatile immap_t *immap = (immap_t *) CFG_IMMR;
458 /* Configure PA15 as output port */
459 immap->im_ioport.iop_padir |= 0x0001;
460 immap->im_ioport.iop_paodr |= 0x0001;
461 immap->im_ioport.iop_papar &= ~0x0001;
462 immap->im_ioport.iop_padat &= ~0x0001; /* turn it off */
467 # ifdef CONFIG_IDE_LED
468 void ide_led (uchar led, uchar status)
470 volatile immap_t *immap = (immap_t *) CFG_IMMR;
472 /* We have one led for both pcmcia slots */
473 if (status) { /* led on */
474 immap->im_ioport.iop_padat |= 0x0001;
476 immap->im_ioport.iop_padat &= ~0x0001;
480 #endif /* CONFIG_HMI10 */
482 /* ---------------------------------------------------------------------------- */
483 /* NSCU specific stuff */
484 /* ---------------------------------------------------------------------------- */
487 int misc_init_r (void)
489 volatile immap_t *immr = (immap_t *) CFG_IMMR;
491 /* wake up ethernet module */
492 immr->im_ioport.iop_pcpar &= ~0x0004; /* GPIO pin */
493 immr->im_ioport.iop_pcdir |= 0x0004; /* output */
494 immr->im_ioport.iop_pcso &= ~0x0004; /* for clarity */
495 immr->im_ioport.iop_pcdat |= 0x0004; /* enable */
499 #endif /* CONFIG_NSCU */
501 /* ------------------------------------------------------------------------- */