3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * Copyright 2004 Freescale Semiconductor.
6 * (C) Copyright 2002,2003, Motorola Inc.
7 * Xianghua Xiao, (X.Xiao@motorola.com)
9 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #include <asm/processor.h>
34 #include <asm/immap_85xx.h>
39 extern flash_info_t flash_info[]; /* FLASH chips info */
41 void local_bus_init (void);
42 long int fixed_sdram (void);
46 * I/O Port configuration table
48 * if conf is 1, then that port pin will be configured at boot time
49 * according to the five values podr/pdir/ppar/psor/pdat for that entry
52 const iop_conf_t iop_conf_tab[4][32] = {
54 /* Port A configuration */
55 { /* conf ppar psor pdir podr pdat */
56 /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */
57 /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */
58 /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */
59 /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */
60 /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */
61 /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */
62 /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
63 /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
64 /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
65 /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
66 /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */
67 /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */
68 /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */
69 /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */
70 /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */
71 /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */
72 /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */
73 /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */
74 /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
75 /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
76 /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
77 /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
78 /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
79 /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
80 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
81 /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
82 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
83 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
84 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
85 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
86 /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* FREERUN */
87 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
90 /* Port B configuration */
91 { /* conf ppar psor pdir podr pdat */
92 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
93 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
94 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
95 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
96 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
97 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
98 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
99 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
100 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
101 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
102 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
103 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
104 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
105 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
106 /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
107 /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
108 /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
109 /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
110 /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:COL */
111 /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
112 /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
113 /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
114 /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
115 /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
116 /* PB7 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
117 /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
118 /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
119 /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
120 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
121 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
122 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
123 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
127 { /* conf ppar psor pdir podr pdat */
128 /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
129 /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
130 /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
131 /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
132 /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
133 /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
134 /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
135 /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
136 /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
137 /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
138 /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
139 /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
140 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
141 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
142 /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* PC17 */
143 /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
144 /* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */
145 /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
146 /* PC13 */ { 0, 1, 0, 0, 0, 0 }, /* PC13 */
147 /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
148 /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
149 /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FETHMDC */
150 /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FETHMDIO */
151 /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
152 /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
153 /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
154 /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
155 /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
156 /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
157 /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
158 /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
159 /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
163 { /* conf ppar psor pdir podr pdat */
164 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
165 /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
166 /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
167 /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* PD28 */
168 /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* PD27 */
169 /* PD26 */ { 1, 1, 0, 1, 0, 0 }, /* PD26 */
170 /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
171 /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
172 /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
173 /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
174 /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
175 /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
176 /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
177 /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
178 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
179 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
180 /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
181 /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
182 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
183 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
184 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
185 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
186 /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
187 /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
188 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
189 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
190 /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
191 /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
192 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
193 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
194 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
195 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
198 #endif /* CONFIG_CPM2 */
200 #define CASL_STRING1 "casl=xx"
201 #define CASL_STRING2 "casl="
203 static const int casl_table[] = { 20, 25, 30 };
204 #define N_CASL (sizeof(casl_table) / sizeof(casl_table[0]))
206 int cas_latency(void)
208 char *s = getenv("serial#");
213 casl = CONFIG_DDR_DEFAULT_CL;
216 if (strncmp(s + strlen(s) - strlen(CASL_STRING1), CASL_STRING2,
217 strlen(CASL_STRING2)) == 0) {
218 val = simple_strtoul(s + strlen(s) - 2, NULL, 10);
220 for (i=0; i<N_CASL; ++i) {
221 if (val == casl_table[i]) {
231 int checkboard (void)
233 char *s = getenv("serial#");
235 printf("Board: %s", CONFIG_BOARDNAME);
243 printf ("PCI1: 32 bit, %d MHz (compiled)\n",
244 CONFIG_SYS_CLK_FREQ / 1000000);
246 printf ("PCI1: disabled\n");
250 * Initialize local bus.
257 int misc_init_r (void)
259 DECLARE_GLOBAL_DATA_PTR;
260 volatile immap_t *immap = (immap_t *)CFG_IMMR;
261 volatile ccsr_lbc_t *memctl = &immap->im_lbc;
264 * Adjust flash start and offset to detected values
266 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
267 gd->bd->bi_flashoffset = 0;
270 * Check if boot FLASH isn't max size
272 if (gd->bd->bi_flashsize < (0 - CFG_FLASH0)) {
273 memctl->or0 = gd->bd->bi_flashstart | (CFG_OR0_PRELIM & 0x00007fff);
274 memctl->br0 = gd->bd->bi_flashstart | (CFG_BR0_PRELIM & 0x00007fff);
277 * Re-check to get correct base address
279 flash_get_size(gd->bd->bi_flashstart, CFG_MAX_FLASH_BANKS - 1);
283 * Check if only one FLASH bank is available
285 if (gd->bd->bi_flashsize != CFG_MAX_FLASH_BANKS * (0 - CFG_FLASH0)) {
290 * Re-do flash protection upon new addresses
292 flash_protect (FLAG_PROTECT_CLEAR,
293 gd->bd->bi_flashstart, 0xffffffff,
294 &flash_info[CFG_MAX_FLASH_BANKS - 1]);
296 /* Monitor protection ON by default */
297 flash_protect (FLAG_PROTECT_SET,
298 CFG_MONITOR_BASE, CFG_MONITOR_BASE + monitor_flash_len - 1,
299 &flash_info[CFG_MAX_FLASH_BANKS - 1]);
301 /* Environment protection ON by default */
302 flash_protect (FLAG_PROTECT_SET,
304 CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
305 &flash_info[CFG_MAX_FLASH_BANKS - 1]);
307 /* Redundant environment protection ON by default */
308 flash_protect (FLAG_PROTECT_SET,
310 CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
311 &flash_info[CFG_MAX_FLASH_BANKS - 1]);
318 * Initialize Local Bus
320 void local_bus_init (void)
322 volatile immap_t *immap = (immap_t *) CFG_IMMR;
323 volatile ccsr_gur_t *gur = &immap->im_gur;
324 volatile ccsr_lbc_t *lbc = &immap->im_lbc;
332 * Fix Local Bus clock glitch when DLL is enabled.
334 * If localbus freq is < 66Mhz, DLL bypass mode must be used.
335 * If localbus freq is > 133Mhz, DLL can be safely enabled.
336 * Between 66 and 133, the DLL is enabled with an override workaround.
339 get_sys_info (&sysinfo);
340 clkdiv = lbc->lcrr & 0x0f;
341 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
344 lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */
345 lbc->ltedr = 0xa4c80000; /* DK: !!! */
347 } else if (lbc_hz >= 133) {
348 lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
352 * On REV1 boards, need to change CLKDIV before enable DLL.
353 * Default CLKDIV is 8, change it to 4 temporarily.
355 uint pvr = get_pvr ();
356 uint temp_lbcdll = 0;
358 if (pvr == PVR_85xx_REV1) {
359 /* FIXME: Justify the high bit here. */
360 lbc->lcrr = 0x10000004;
363 lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
367 * Sample LBC DLL ctrl reg, upshift it to set the
370 temp_lbcdll = gur->lbcdllcr;
371 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
372 asm ("sync;isync;msync");
376 #if defined(CONFIG_PCI)
378 * Initialize PCI Devices, report devices found.
381 #ifndef CONFIG_PCI_PNP
382 static struct pci_config_table pci_mpc85xxads_config_table[] = {
383 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
384 PCI_IDSEL_NUMBER, PCI_ANY_ID,
385 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
388 PCI_COMMAND_MASTER}},
394 static struct pci_controller hose = {
395 #ifndef CONFIG_PCI_PNP
396 config_table:pci_mpc85xxads_config_table,
400 #endif /* CONFIG_PCI */
403 void pci_init_board (void)
406 extern void pci_mpc85xx_init (struct pci_controller *hose);
408 pci_mpc85xx_init (&hose);
409 #endif /* CONFIG_PCI */