2 * (C) Copyright 2003-2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
8 * (C) Copyright 2004-2006
9 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #include <asm/processor.h>
36 #ifdef CONFIG_VIDEO_SM501
40 #if defined(CONFIG_MPC5200_DDR)
41 #include "mt46v16m16-75.h"
43 #include "mt48lc16m16a2-75.h"
47 void ps2mult_early_init(void);
51 static void sdram_start (int hi_addr)
53 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
55 /* unlock mode register */
56 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
58 __asm__ volatile ("sync");
60 /* precharge all banks */
61 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
63 __asm__ volatile ("sync");
66 /* set mode register: extended mode */
67 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
68 __asm__ volatile ("sync");
70 /* set mode register: reset DLL */
71 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
72 __asm__ volatile ("sync");
75 /* precharge all banks */
76 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
78 __asm__ volatile ("sync");
81 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
83 __asm__ volatile ("sync");
85 /* set mode register */
86 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
87 __asm__ volatile ("sync");
89 /* normal operation */
90 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
91 __asm__ volatile ("sync");
96 * ATTENTION: Although partially referenced initdram does NOT make real use
97 * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
98 * is something else than 0x00000000.
101 #if defined(CONFIG_MPC5200)
102 long int initdram (int board_type)
111 /* setup SDRAM chip selects */
112 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
113 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
114 __asm__ volatile ("sync");
116 /* setup config registers */
117 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
118 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
119 __asm__ volatile ("sync");
123 *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
124 __asm__ volatile ("sync");
127 /* find RAM size using SDRAM CS0 only */
129 test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
131 test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
139 /* memory smaller than 1MB is impossible */
140 if (dramsize < (1 << 20)) {
144 /* set SDRAM CS0 size according to the amount of RAM found */
146 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
147 __builtin_ffs(dramsize >> 20) - 1;
149 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
152 /* let SDRAM CS1 start right after CS0 */
153 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */
155 /* find RAM size using SDRAM CS1 only */
157 test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
159 test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
167 /* memory smaller than 1MB is impossible */
168 if (dramsize2 < (1 << 20)) {
172 /* set SDRAM CS1 size according to the amount of RAM found */
174 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
175 | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
177 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
180 #else /* CFG_RAMBOOT */
182 /* retrieve size of memory connected to SDRAM CS0 */
183 dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
184 if (dramsize >= 0x13) {
185 dramsize = (1 << (dramsize - 0x13)) << 20;
190 /* retrieve size of memory connected to SDRAM CS1 */
191 dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
192 if (dramsize2 >= 0x13) {
193 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
197 #endif /* CFG_RAMBOOT */
200 * On MPC5200B we need to set the special configuration delay in the
201 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
202 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
204 * "The SDelay should be written to a value of 0x00000004. It is
205 * required to account for changes caused by normal wafer processing
210 if ((SVR_MJREV(svr) >= 2) &&
211 (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
213 *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
214 __asm__ volatile ("sync");
217 #if defined(CONFIG_TQM5200_B)
218 return dramsize + dramsize2;
221 #endif /* CONFIG_TQM5200_B */
224 #elif defined(CONFIG_MGT5100)
226 long int initdram (int board_type)
232 /* setup and enable SDRAM chip selects */
233 *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
234 *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
235 *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
236 __asm__ volatile ("sync");
238 /* setup config registers */
239 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
240 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
242 /* address select register */
243 *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
244 __asm__ volatile ("sync");
248 test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
250 test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
258 /* set SDRAM end address according to size */
259 *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
261 #else /* CFG_RAMBOOT */
263 /* Retrieve amount of SDRAM available */
264 dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
266 #endif /* CFG_RAMBOOT */
272 #error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
275 int checkboard (void)
277 #if defined(CONFIG_AEVFIFO)
278 puts ("Board: AEVFIFO\n");
282 #if defined(CONFIG_TQM5200S)
283 # define MODULE_NAME "TQM5200S"
285 # define MODULE_NAME "TQM5200"
288 #if defined(CONFIG_STK52XX)
289 # define CARRIER_NAME "STK52xx"
290 #elif defined(CONFIG_TB5200)
291 # define CARRIER_NAME "TB5200"
292 #elif defined(CONFIG_CAM5200)
293 # define CARRIER_NAME "CAM5200"
294 #elif defined(CONFIG_FO300)
295 # define CARRIER_NAME "FO300"
300 puts ( "Board: " MODULE_NAME " (TQ-Components GmbH)\n"
301 " on a " CARRIER_NAME " carrier board\n");
309 void flash_preinit(void)
312 * Now, when we are in RAM, enable flash write
313 * access for detection process.
314 * Note that CS_BOOT cannot be cleared when
315 * executing in flash.
317 #if defined(CONFIG_MGT5100)
318 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
319 *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
321 *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
326 static struct pci_controller hose;
328 extern void pci_mpc5xxx_init(struct pci_controller *);
330 void pci_init_board(void)
332 pci_mpc5xxx_init(&hose);
336 #if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
338 #if defined (CONFIG_MINIFAP)
339 #define SM501_POWER_MODE0_GATE 0x00000040UL
340 #define SM501_POWER_MODE1_GATE 0x00000048UL
341 #define POWER_MODE_GATE_GPIO_PWM_I2C 0x00000040UL
342 #define SM501_GPIO_DATA_DIR_HIGH 0x0001000CUL
343 #define SM501_GPIO_DATA_HIGH 0x00010004UL
344 #define SM501_GPIO_51 0x00080000UL
345 #endif /* CONFIG MINIFAP */
347 void init_ide_reset (void)
349 debug ("init_ide_reset\n");
351 #if defined (CONFIG_MINIFAP)
352 /* Configure GPIO_51 of the SM501 grafic controller as ATA reset */
354 /* enable GPIO control (in both power modes) */
355 *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE0_GATE) |=
356 POWER_MODE_GATE_GPIO_PWM_I2C;
357 *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE1_GATE) |=
358 POWER_MODE_GATE_GPIO_PWM_I2C;
359 /* configure GPIO51 as output */
360 *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_HIGH) |=
363 /* Configure PSC1_4 as GPIO output for ATA reset */
364 *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
365 *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
369 void ide_set_reset (int idereset)
371 debug ("ide_reset(%d)\n", idereset);
373 #if defined (CONFIG_MINIFAP)
375 *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
378 *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
383 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
385 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
393 * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3
394 * is left open, no keypress is detected.
396 int post_hotkeys_pressed(void)
398 #ifdef CONFIG_STK52XX
399 struct mpc5xxx_gpio *gpio;
401 gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO;
404 * Configure PSC6_1 and PSC6_3 as GPIO. PSC6 then couldn't be used in
405 * CODEC or UART mode. Consumer IrDA should still be possible.
407 gpio->port_config &= ~(0x07000000);
408 gpio->port_config |= 0x03000000;
410 /* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */
411 gpio->simple_gpioe |= 0x20000000;
413 /* Configure GPIO_IRDA_1 as input */
414 gpio->simple_ddr &= ~(0x20000000);
416 return ((gpio->simple_ival & 0x20000000) ? 0 : 1);
423 #if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
425 void post_word_store (ulong a)
427 volatile ulong *save_addr =
428 (volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE);
433 ulong post_word_load (void)
435 volatile ulong *save_addr =
436 (volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE);
440 #endif /* CONFIG_POST || CONFIG_LOGBUFFER*/
442 #ifdef CONFIG_PS2MULT
443 #ifdef CONFIG_BOARD_EARLY_INIT_R
444 int board_early_init_r (void)
446 ps2mult_early_init();
450 #endif /* CONFIG_PS2MULT */
453 int silent_boot (void)
455 vu_long timer3_status;
457 /* Configure GPT3 as GPIO input */
458 *(vu_long *)MPC5XXX_GPT3_ENABLE = 0x00000004;
460 /* Read in TIMER_3 pin status */
461 timer3_status = *(vu_long *)MPC5XXX_GPT3_STATUS;
463 #ifdef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED
464 /* Force silent console mode if S1 switch
465 * is in closed position (TIMER_3 pin status is LOW). */
466 if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 0)
469 /* Force silent console mode if S1 switch
470 * is in open position (TIMER_3 pin status is HIGH). */
471 if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 1)
478 int board_early_init_f (void)
480 DECLARE_GLOBAL_DATA_PTR;
483 gd->flags |= GD_FLG_SILENT;
487 #endif /* CONFIG_FO300 */
489 int last_stage_init (void)
492 * auto scan for really existing devices and re-set chip select
499 * Check for SRAM and SRAM size
502 /* save original SRAM content */
503 save = *(volatile u16 *)CFG_CS2_START;
506 /* write test pattern to SRAM */
507 *(volatile u16 *)CFG_CS2_START = 0xA5A5;
508 __asm__ volatile ("sync");
510 * Put a different pattern on the data lines: otherwise they may float
511 * long enough to read back what we wrote.
513 tmp = *(volatile u16 *)CFG_FLASH_BASE;
515 puts ("!! possible error in SRAM detection\n");
517 if (*(volatile u16 *)CFG_CS2_START != 0xA5A5) {
518 /* no SRAM at all, disable cs */
519 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18);
520 *(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF;
521 *(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF;
523 __asm__ volatile ("sync");
524 } else if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0xA5A5) {
525 /* make sure that we access a mirrored address */
526 *(volatile u16 *)CFG_CS2_START = 0x1111;
527 __asm__ volatile ("sync");
528 if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0x1111) {
529 /* SRAM size = 512 kByte */
530 *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CFG_CS2_START,
532 __asm__ volatile ("sync");
533 puts ("SRAM: 512 kB\n");
536 puts ("!! possible error in SRAM detection\n");
538 puts ("SRAM: 1 MB\n");
540 /* restore origianl SRAM content */
542 *(volatile u16 *)CFG_CS2_START = save;
543 __asm__ volatile ("sync");
547 * Check for Grafic Controller
550 /* save origianl FB content */
551 save = *(volatile u16 *)CFG_CS1_START;
554 /* write test pattern to FB memory */
555 *(volatile u16 *)CFG_CS1_START = 0xA5A5;
556 __asm__ volatile ("sync");
558 * Put a different pattern on the data lines: otherwise they may float
559 * long enough to read back what we wrote.
561 tmp = *(volatile u16 *)CFG_FLASH_BASE;
563 puts ("!! possible error in grafic controller detection\n");
565 if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) {
566 /* no grafic controller at all, disable cs */
567 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17);
568 *(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF;
569 *(vu_long *)MPC5XXX_CS1_STOP = 0x0000FFFF;
571 __asm__ volatile ("sync");
573 puts ("VGA: SMI501 (Voyager) with 8 MB\n");
575 /* restore origianl FB content */
577 *(volatile u16 *)CFG_CS1_START = save;
578 __asm__ volatile ("sync");
583 setenv("bootdelay", "0");
591 #ifdef CONFIG_VIDEO_SM501
594 #define DISPLAY_WIDTH 800
596 #define DISPLAY_WIDTH 640
598 #define DISPLAY_HEIGHT 480
600 #ifdef CONFIG_VIDEO_SM501_8BPP
601 #error CONFIG_VIDEO_SM501_8BPP not supported.
602 #endif /* CONFIG_VIDEO_SM501_8BPP */
604 #ifdef CONFIG_VIDEO_SM501_16BPP
605 #error CONFIG_VIDEO_SM501_16BPP not supported.
606 #endif /* CONFIG_VIDEO_SM501_16BPP */
607 #ifdef CONFIG_VIDEO_SM501_32BPP
608 static const SMI_REGS init_regs [] =
612 {0x00048, 0x00021807},
613 {0x0004C, 0x10090a01},
615 {0x00040, 0x00021807},
616 {0x00044, 0x10090a01},
618 {0x80200, 0x00010000},
620 {0x80208, 0x0A000A00},
621 {0x8020C, 0x02fa027f},
622 {0x80210, 0x004a028b},
623 {0x80214, 0x020c01df},
624 {0x80218, 0x000201e9},
625 {0x80200, 0x00013306},
626 #else /* panel + CRT */
629 {0x00048, 0x00021807},
630 {0x0004C, 0x301a0a01},
632 {0x00040, 0x00021807},
633 {0x00044, 0x091a0a01},
635 {0x80000, 0x0f013106},
636 {0x80004, 0xc428bb17},
637 {0x8000C, 0x00000000},
638 {0x80010, 0x0C800C80},
639 {0x80014, 0x03200000},
640 {0x80018, 0x01e00000},
641 {0x8001C, 0x00000000},
642 {0x80020, 0x01e00320},
643 {0x80024, 0x042a031f},
644 {0x80028, 0x0086034a},
645 {0x8002C, 0x020c01df},
646 {0x80030, 0x000201ea},
647 {0x80200, 0x00010000},
650 {0x00048, 0x00021807},
651 {0x0004C, 0x091a0a01},
653 {0x00040, 0x00021807},
654 {0x00044, 0x091a0a01},
656 {0x80000, 0x0f013106},
657 {0x80004, 0xc428bb17},
658 {0x8000C, 0x00000000},
659 {0x80010, 0x0a000a00},
660 {0x80014, 0x02800000},
661 {0x80018, 0x01e00000},
662 {0x8001C, 0x00000000},
663 {0x80020, 0x01e00280},
664 {0x80024, 0x02fa027f},
665 {0x80028, 0x004a028b},
666 {0x8002C, 0x020c01df},
667 {0x80030, 0x000201e9},
668 {0x80200, 0x00010000},
669 #endif /* #ifdef CONFIG_FO300 */
673 #endif /* CONFIG_VIDEO_SM501_32BPP */
675 #ifdef CONFIG_CONSOLE_EXTRA_INFO
677 * Return text to be printed besides the logo.
679 void video_get_info_str (int line_number, char *info)
681 if (line_number == 1) {
682 strcpy (info, " Board: TQM5200 (TQ-Components GmbH)");
683 #if defined (CONFIG_STK52XX) || defined (CONFIG_TB5200) || defined(CONFIG_FO300)
684 } else if (line_number == 2) {
685 #if defined (CONFIG_STK52XX)
686 strcpy (info, " on a STK52xx carrier board");
688 #if defined (CONFIG_TB5200)
689 strcpy (info, " on a TB5200 carrier board");
691 #if defined (CONFIG_FO300)
692 strcpy (info, " on a FO300 carrier board");
703 * Returns SM501 register base address. First thing called in the
704 * driver. Checks if SM501 is physically present.
706 unsigned int board_video_init (void)
712 * Check for Grafic Controller
715 /* save origianl FB content */
716 save = *(volatile u16 *)CFG_CS1_START;
719 /* write test pattern to FB memory */
720 *(volatile u16 *)CFG_CS1_START = 0xA5A5;
721 __asm__ volatile ("sync");
723 * Put a different pattern on the data lines: otherwise they may float
724 * long enough to read back what we wrote.
726 tmp = *(volatile u16 *)CFG_FLASH_BASE;
728 puts ("!! possible error in grafic controller detection\n");
730 if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) {
731 /* no grafic controller found */
735 ret = SM501_MMIO_BASE;
739 *(volatile u16 *)CFG_CS1_START = save;
740 __asm__ volatile ("sync");
746 * Returns SM501 framebuffer address
748 unsigned int board_video_get_fb (void)
750 return SM501_FB_BASE;
754 * Called after initializing the SM501 and before clearing the screen.
756 void board_validate_screen (unsigned int base)
761 * Return a pointer to the initialization sequence.
763 const SMI_REGS *board_get_regs (void)
768 int board_get_width (void)
770 return DISPLAY_WIDTH;
773 int board_get_height (void)
775 return DISPLAY_HEIGHT;
778 #endif /* CONFIG_VIDEO_SM501 */
780 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
781 void ft_board_setup(void *blob, bd_t *bd)
783 ft_cpu_setup(blob, bd);
785 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */