2 * (C) Copyright 2003-2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
8 * (C) Copyright 2004-2006
9 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #include <asm/processor.h>
36 #ifdef CONFIG_VIDEO_SM501
40 #if defined(CONFIG_MPC5200_DDR)
41 #include "mt46v16m16-75.h"
43 #include "mt48lc16m16a2-75.h"
46 DECLARE_GLOBAL_DATA_PTR;
49 void ps2mult_early_init(void);
53 static void sdram_start (int hi_addr)
55 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
57 /* unlock mode register */
58 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
60 __asm__ volatile ("sync");
62 /* precharge all banks */
63 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
65 __asm__ volatile ("sync");
68 /* set mode register: extended mode */
69 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
70 __asm__ volatile ("sync");
72 /* set mode register: reset DLL */
73 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
74 __asm__ volatile ("sync");
77 /* precharge all banks */
78 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
80 __asm__ volatile ("sync");
83 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
85 __asm__ volatile ("sync");
87 /* set mode register */
88 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
89 __asm__ volatile ("sync");
91 /* normal operation */
92 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
93 __asm__ volatile ("sync");
98 * ATTENTION: Although partially referenced initdram does NOT make real use
99 * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
100 * is something else than 0x00000000.
103 #if defined(CONFIG_MPC5200)
104 long int initdram (int board_type)
113 /* setup SDRAM chip selects */
114 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
115 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
116 __asm__ volatile ("sync");
118 /* setup config registers */
119 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
120 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
121 __asm__ volatile ("sync");
125 *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
126 __asm__ volatile ("sync");
129 /* find RAM size using SDRAM CS0 only */
131 test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
133 test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
141 /* memory smaller than 1MB is impossible */
142 if (dramsize < (1 << 20)) {
146 /* set SDRAM CS0 size according to the amount of RAM found */
148 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
149 __builtin_ffs(dramsize >> 20) - 1;
151 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
154 /* let SDRAM CS1 start right after CS0 */
155 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */
157 /* find RAM size using SDRAM CS1 only */
160 test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
163 test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
172 /* memory smaller than 1MB is impossible */
173 if (dramsize2 < (1 << 20)) {
177 /* set SDRAM CS1 size according to the amount of RAM found */
179 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
180 | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
182 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
185 #else /* CFG_RAMBOOT */
187 /* retrieve size of memory connected to SDRAM CS0 */
188 dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
189 if (dramsize >= 0x13) {
190 dramsize = (1 << (dramsize - 0x13)) << 20;
195 /* retrieve size of memory connected to SDRAM CS1 */
196 dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
197 if (dramsize2 >= 0x13) {
198 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
202 #endif /* CFG_RAMBOOT */
205 * On MPC5200B we need to set the special configuration delay in the
206 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
207 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
209 * "The SDelay should be written to a value of 0x00000004. It is
210 * required to account for changes caused by normal wafer processing
215 if ((SVR_MJREV(svr) >= 2) &&
216 (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
218 *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
219 __asm__ volatile ("sync");
222 #if defined(CONFIG_TQM5200_B)
223 return dramsize + dramsize2;
226 #endif /* CONFIG_TQM5200_B */
229 #elif defined(CONFIG_MGT5100)
231 long int initdram (int board_type)
237 /* setup and enable SDRAM chip selects */
238 *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
239 *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
240 *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
241 __asm__ volatile ("sync");
243 /* setup config registers */
244 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
245 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
247 /* address select register */
248 *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
249 __asm__ volatile ("sync");
253 test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
255 test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
263 /* set SDRAM end address according to size */
264 *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
266 #else /* CFG_RAMBOOT */
268 /* Retrieve amount of SDRAM available */
269 dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
271 #endif /* CFG_RAMBOOT */
277 #error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
280 int checkboard (void)
282 #if defined(CONFIG_AEVFIFO)
283 puts ("Board: AEVFIFO\n");
287 #if defined(CONFIG_TQM5200S)
288 # define MODULE_NAME "TQM5200S"
290 # define MODULE_NAME "TQM5200"
293 #if defined(CONFIG_STK52XX)
294 # define CARRIER_NAME "STK52xx"
295 #elif defined(CONFIG_TB5200)
296 # define CARRIER_NAME "TB5200"
297 #elif defined(CONFIG_CAM5200)
298 # define CARRIER_NAME "CAM5200"
299 #elif defined(CONFIG_FO300)
300 # define CARRIER_NAME "FO300"
305 puts ( "Board: " MODULE_NAME " (TQ-Components GmbH)\n"
306 " on a " CARRIER_NAME " carrier board\n");
314 void flash_preinit(void)
317 * Now, when we are in RAM, enable flash write
318 * access for detection process.
319 * Note that CS_BOOT cannot be cleared when
320 * executing in flash.
322 #if defined(CONFIG_MGT5100)
323 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
324 *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
326 *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
331 static struct pci_controller hose;
333 extern void pci_mpc5xxx_init(struct pci_controller *);
335 void pci_init_board(void)
337 pci_mpc5xxx_init(&hose);
341 #if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
343 #if defined (CONFIG_MINIFAP)
344 #define SM501_POWER_MODE0_GATE 0x00000040UL
345 #define SM501_POWER_MODE1_GATE 0x00000048UL
346 #define POWER_MODE_GATE_GPIO_PWM_I2C 0x00000040UL
347 #define SM501_GPIO_DATA_DIR_HIGH 0x0001000CUL
348 #define SM501_GPIO_DATA_HIGH 0x00010004UL
349 #define SM501_GPIO_51 0x00080000UL
350 #endif /* CONFIG MINIFAP */
352 void init_ide_reset (void)
354 debug ("init_ide_reset\n");
356 #if defined (CONFIG_MINIFAP)
357 /* Configure GPIO_51 of the SM501 grafic controller as ATA reset */
359 /* enable GPIO control (in both power modes) */
360 *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE0_GATE) |=
361 POWER_MODE_GATE_GPIO_PWM_I2C;
362 *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE1_GATE) |=
363 POWER_MODE_GATE_GPIO_PWM_I2C;
364 /* configure GPIO51 as output */
365 *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_HIGH) |=
368 /* Configure PSC1_4 as GPIO output for ATA reset */
369 *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
370 *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
374 void ide_set_reset (int idereset)
376 debug ("ide_reset(%d)\n", idereset);
378 #if defined (CONFIG_MINIFAP)
380 *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
383 *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
388 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
390 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
398 * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3
399 * is left open, no keypress is detected.
401 int post_hotkeys_pressed(void)
403 #ifdef CONFIG_STK52XX
404 struct mpc5xxx_gpio *gpio;
406 gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO;
409 * Configure PSC6_1 and PSC6_3 as GPIO. PSC6 then couldn't be used in
410 * CODEC or UART mode. Consumer IrDA should still be possible.
412 gpio->port_config &= ~(0x07000000);
413 gpio->port_config |= 0x03000000;
415 /* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */
416 gpio->simple_gpioe |= 0x20000000;
418 /* Configure GPIO_IRDA_1 as input */
419 gpio->simple_ddr &= ~(0x20000000);
421 return ((gpio->simple_ival & 0x20000000) ? 0 : 1);
428 #if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
430 void post_word_store (ulong a)
432 volatile ulong *save_addr =
433 (volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE);
438 ulong post_word_load (void)
440 volatile ulong *save_addr =
441 (volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE);
445 #endif /* CONFIG_POST || CONFIG_LOGBUFFER*/
447 #ifdef CONFIG_BOARD_EARLY_INIT_R
448 int board_early_init_r (void)
451 extern int usb_cpu_init(void);
453 #ifdef CONFIG_PS2MULT
454 ps2mult_early_init();
455 #endif /* CONFIG_PS2MULT */
457 #if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT)
458 /* Low level USB init, required for proper kernel operation */
467 int silent_boot (void)
469 vu_long timer3_status;
471 /* Configure GPT3 as GPIO input */
472 *(vu_long *)MPC5XXX_GPT3_ENABLE = 0x00000004;
474 /* Read in TIMER_3 pin status */
475 timer3_status = *(vu_long *)MPC5XXX_GPT3_STATUS;
477 #ifdef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED
478 /* Force silent console mode if S1 switch
479 * is in closed position (TIMER_3 pin status is LOW). */
480 if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 0)
483 /* Force silent console mode if S1 switch
484 * is in open position (TIMER_3 pin status is HIGH). */
485 if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 1)
492 int board_early_init_f (void)
495 gd->flags |= GD_FLG_SILENT;
499 #endif /* CONFIG_FO300 */
501 int last_stage_init (void)
504 * auto scan for really existing devices and re-set chip select
511 * Check for SRAM and SRAM size
514 /* save original SRAM content */
515 save = *(volatile u16 *)CFG_CS2_START;
518 /* write test pattern to SRAM */
519 *(volatile u16 *)CFG_CS2_START = 0xA5A5;
520 __asm__ volatile ("sync");
522 * Put a different pattern on the data lines: otherwise they may float
523 * long enough to read back what we wrote.
525 tmp = *(volatile u16 *)CFG_FLASH_BASE;
527 puts ("!! possible error in SRAM detection\n");
529 if (*(volatile u16 *)CFG_CS2_START != 0xA5A5) {
530 /* no SRAM at all, disable cs */
531 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18);
532 *(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF;
533 *(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF;
535 __asm__ volatile ("sync");
536 } else if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0xA5A5) {
537 /* make sure that we access a mirrored address */
538 *(volatile u16 *)CFG_CS2_START = 0x1111;
539 __asm__ volatile ("sync");
540 if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0x1111) {
541 /* SRAM size = 512 kByte */
542 *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CFG_CS2_START,
544 __asm__ volatile ("sync");
545 puts ("SRAM: 512 kB\n");
548 puts ("!! possible error in SRAM detection\n");
550 puts ("SRAM: 1 MB\n");
552 /* restore origianl SRAM content */
554 *(volatile u16 *)CFG_CS2_START = save;
555 __asm__ volatile ("sync");
558 #ifndef CONFIG_TQM5200S /* The TQM5200S has no SM501 grafic controller */
560 * Check for Grafic Controller
563 /* save origianl FB content */
564 save = *(volatile u16 *)CFG_CS1_START;
567 /* write test pattern to FB memory */
568 *(volatile u16 *)CFG_CS1_START = 0xA5A5;
569 __asm__ volatile ("sync");
571 * Put a different pattern on the data lines: otherwise they may float
572 * long enough to read back what we wrote.
574 tmp = *(volatile u16 *)CFG_FLASH_BASE;
576 puts ("!! possible error in grafic controller detection\n");
578 if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) {
579 /* no grafic controller at all, disable cs */
580 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17);
581 *(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF;
582 *(vu_long *)MPC5XXX_CS1_STOP = 0x0000FFFF;
584 __asm__ volatile ("sync");
586 puts ("VGA: SMI501 (Voyager) with 8 MB\n");
588 /* restore origianl FB content */
590 *(volatile u16 *)CFG_CS1_START = save;
591 __asm__ volatile ("sync");
596 setenv("bootdelay", "0");
600 #endif /* !CONFIG_TQM5200S */
605 #ifdef CONFIG_VIDEO_SM501
608 #define DISPLAY_WIDTH 800
610 #define DISPLAY_WIDTH 640
612 #define DISPLAY_HEIGHT 480
614 #ifdef CONFIG_VIDEO_SM501_8BPP
615 #error CONFIG_VIDEO_SM501_8BPP not supported.
616 #endif /* CONFIG_VIDEO_SM501_8BPP */
618 #ifdef CONFIG_VIDEO_SM501_16BPP
619 #error CONFIG_VIDEO_SM501_16BPP not supported.
620 #endif /* CONFIG_VIDEO_SM501_16BPP */
621 #ifdef CONFIG_VIDEO_SM501_32BPP
622 static const SMI_REGS init_regs [] =
626 {0x00048, 0x00021807},
627 {0x0004C, 0x10090a01},
629 {0x00040, 0x00021807},
630 {0x00044, 0x10090a01},
632 {0x80200, 0x00010000},
634 {0x80208, 0x0A000A00},
635 {0x8020C, 0x02fa027f},
636 {0x80210, 0x004a028b},
637 {0x80214, 0x020c01df},
638 {0x80218, 0x000201e9},
639 {0x80200, 0x00013306},
640 #else /* panel + CRT */
643 {0x00048, 0x00021807},
644 {0x0004C, 0x301a0a01},
646 {0x00040, 0x00021807},
647 {0x00044, 0x091a0a01},
649 {0x80000, 0x0f013106},
650 {0x80004, 0xc428bb17},
651 {0x8000C, 0x00000000},
652 {0x80010, 0x0C800C80},
653 {0x80014, 0x03200000},
654 {0x80018, 0x01e00000},
655 {0x8001C, 0x00000000},
656 {0x80020, 0x01e00320},
657 {0x80024, 0x042a031f},
658 {0x80028, 0x0086034a},
659 {0x8002C, 0x020c01df},
660 {0x80030, 0x000201ea},
661 {0x80200, 0x00010000},
664 {0x00048, 0x00021807},
665 {0x0004C, 0x091a0a01},
667 {0x00040, 0x00021807},
668 {0x00044, 0x091a0a01},
670 {0x80000, 0x0f013106},
671 {0x80004, 0xc428bb17},
672 {0x8000C, 0x00000000},
673 {0x80010, 0x0a000a00},
674 {0x80014, 0x02800000},
675 {0x80018, 0x01e00000},
676 {0x8001C, 0x00000000},
677 {0x80020, 0x01e00280},
678 {0x80024, 0x02fa027f},
679 {0x80028, 0x004a028b},
680 {0x8002C, 0x020c01df},
681 {0x80030, 0x000201e9},
682 {0x80200, 0x00010000},
683 #endif /* #ifdef CONFIG_FO300 */
687 #endif /* CONFIG_VIDEO_SM501_32BPP */
689 #ifdef CONFIG_CONSOLE_EXTRA_INFO
691 * Return text to be printed besides the logo.
693 void video_get_info_str (int line_number, char *info)
695 if (line_number == 1) {
696 strcpy (info, " Board: TQM5200 (TQ-Components GmbH)");
697 #if defined (CONFIG_STK52XX) || defined (CONFIG_TB5200) || defined(CONFIG_FO300)
698 } else if (line_number == 2) {
699 #if defined (CONFIG_STK52XX)
700 strcpy (info, " on a STK52xx carrier board");
702 #if defined (CONFIG_TB5200)
703 strcpy (info, " on a TB5200 carrier board");
705 #if defined (CONFIG_FO300)
706 strcpy (info, " on a FO300 carrier board");
717 * Returns SM501 register base address. First thing called in the
718 * driver. Checks if SM501 is physically present.
720 unsigned int board_video_init (void)
726 * Check for Grafic Controller
729 /* save origianl FB content */
730 save = *(volatile u16 *)CFG_CS1_START;
733 /* write test pattern to FB memory */
734 *(volatile u16 *)CFG_CS1_START = 0xA5A5;
735 __asm__ volatile ("sync");
737 * Put a different pattern on the data lines: otherwise they may float
738 * long enough to read back what we wrote.
740 tmp = *(volatile u16 *)CFG_FLASH_BASE;
742 puts ("!! possible error in grafic controller detection\n");
744 if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) {
745 /* no grafic controller found */
749 ret = SM501_MMIO_BASE;
753 *(volatile u16 *)CFG_CS1_START = save;
754 __asm__ volatile ("sync");
760 * Returns SM501 framebuffer address
762 unsigned int board_video_get_fb (void)
764 return SM501_FB_BASE;
768 * Called after initializing the SM501 and before clearing the screen.
770 void board_validate_screen (unsigned int base)
775 * Return a pointer to the initialization sequence.
777 const SMI_REGS *board_get_regs (void)
782 int board_get_width (void)
784 return DISPLAY_WIDTH;
787 int board_get_height (void)
789 return DISPLAY_HEIGHT;
792 #endif /* CONFIG_VIDEO_SM501 */
794 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
795 void ft_board_setup(void *blob, bd_t *bd)
797 ft_cpu_setup(blob, bd);
799 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */