2 * (C) Copyright 2003-2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
8 * (C) Copyright 2004-2006
9 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #include <asm/processor.h>
36 #ifdef CONFIG_VIDEO_SM501
40 #if defined(CONFIG_MPC5200_DDR)
41 #include "mt46v16m16-75.h"
43 #include "mt48lc16m16a2-75.h"
46 #ifdef CONFIG_OF_LIBFDT
47 #include <fdt_support.h>
48 #endif /* CONFIG_OF_LIBFDT */
50 DECLARE_GLOBAL_DATA_PTR;
53 void ps2mult_early_init(void);
57 static void sdram_start (int hi_addr)
59 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
61 /* unlock mode register */
62 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
64 __asm__ volatile ("sync");
66 /* precharge all banks */
67 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
69 __asm__ volatile ("sync");
72 /* set mode register: extended mode */
73 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
74 __asm__ volatile ("sync");
76 /* set mode register: reset DLL */
77 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
78 __asm__ volatile ("sync");
81 /* precharge all banks */
82 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
84 __asm__ volatile ("sync");
87 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
89 __asm__ volatile ("sync");
91 /* set mode register */
92 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
93 __asm__ volatile ("sync");
95 /* normal operation */
96 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
97 __asm__ volatile ("sync");
102 * ATTENTION: Although partially referenced initdram does NOT make real use
103 * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
104 * is something else than 0x00000000.
107 #if defined(CONFIG_MPC5200)
108 long int initdram (int board_type)
117 /* setup SDRAM chip selects */
118 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
119 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
120 __asm__ volatile ("sync");
122 /* setup config registers */
123 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
124 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
125 __asm__ volatile ("sync");
129 *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
130 __asm__ volatile ("sync");
133 /* find RAM size using SDRAM CS0 only */
135 test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
137 test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
145 /* memory smaller than 1MB is impossible */
146 if (dramsize < (1 << 20)) {
150 /* set SDRAM CS0 size according to the amount of RAM found */
152 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
153 __builtin_ffs(dramsize >> 20) - 1;
155 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
158 /* let SDRAM CS1 start right after CS0 */
159 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */
161 /* find RAM size using SDRAM CS1 only */
164 test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
167 test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
176 /* memory smaller than 1MB is impossible */
177 if (dramsize2 < (1 << 20)) {
181 /* set SDRAM CS1 size according to the amount of RAM found */
183 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
184 | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
186 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
189 #else /* CFG_RAMBOOT */
191 /* retrieve size of memory connected to SDRAM CS0 */
192 dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
193 if (dramsize >= 0x13) {
194 dramsize = (1 << (dramsize - 0x13)) << 20;
199 /* retrieve size of memory connected to SDRAM CS1 */
200 dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
201 if (dramsize2 >= 0x13) {
202 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
206 #endif /* CFG_RAMBOOT */
209 * On MPC5200B we need to set the special configuration delay in the
210 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
211 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
213 * "The SDelay should be written to a value of 0x00000004. It is
214 * required to account for changes caused by normal wafer processing
219 if ((SVR_MJREV(svr) >= 2) &&
220 (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
222 *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
223 __asm__ volatile ("sync");
226 #if defined(CONFIG_TQM5200_B)
227 return dramsize + dramsize2;
230 #endif /* CONFIG_TQM5200_B */
233 #elif defined(CONFIG_MGT5100)
235 long int initdram (int board_type)
241 /* setup and enable SDRAM chip selects */
242 *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
243 *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
244 *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
245 __asm__ volatile ("sync");
247 /* setup config registers */
248 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
249 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
251 /* address select register */
252 *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
253 __asm__ volatile ("sync");
257 test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
259 test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
267 /* set SDRAM end address according to size */
268 *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
270 #else /* CFG_RAMBOOT */
272 /* Retrieve amount of SDRAM available */
273 dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
275 #endif /* CFG_RAMBOOT */
281 #error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
284 int checkboard (void)
286 #if defined(CONFIG_AEVFIFO)
287 puts ("Board: AEVFIFO\n");
291 #if defined(CONFIG_TQM5200S)
292 # define MODULE_NAME "TQM5200S"
294 # define MODULE_NAME "TQM5200"
297 #if defined(CONFIG_STK52XX)
298 # define CARRIER_NAME "STK52xx"
299 #elif defined(CONFIG_TB5200)
300 # define CARRIER_NAME "TB5200"
301 #elif defined(CONFIG_CAM5200)
302 # define CARRIER_NAME "CAM5200"
303 #elif defined(CONFIG_FO300)
304 # define CARRIER_NAME "FO300"
309 puts ( "Board: " MODULE_NAME " (TQ-Components GmbH)\n"
310 " on a " CARRIER_NAME " carrier board\n");
318 void flash_preinit(void)
321 * Now, when we are in RAM, enable flash write
322 * access for detection process.
323 * Note that CS_BOOT cannot be cleared when
324 * executing in flash.
326 #if defined(CONFIG_MGT5100)
327 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
328 *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
330 *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
335 static struct pci_controller hose;
337 extern void pci_mpc5xxx_init(struct pci_controller *);
339 void pci_init_board(void)
341 pci_mpc5xxx_init(&hose);
345 #if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
347 #if defined (CONFIG_MINIFAP)
348 #define SM501_POWER_MODE0_GATE 0x00000040UL
349 #define SM501_POWER_MODE1_GATE 0x00000048UL
350 #define POWER_MODE_GATE_GPIO_PWM_I2C 0x00000040UL
351 #define SM501_GPIO_DATA_DIR_HIGH 0x0001000CUL
352 #define SM501_GPIO_DATA_HIGH 0x00010004UL
353 #define SM501_GPIO_51 0x00080000UL
354 #endif /* CONFIG MINIFAP */
356 void init_ide_reset (void)
358 debug ("init_ide_reset\n");
360 #if defined (CONFIG_MINIFAP)
361 /* Configure GPIO_51 of the SM501 grafic controller as ATA reset */
363 /* enable GPIO control (in both power modes) */
364 *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE0_GATE) |=
365 POWER_MODE_GATE_GPIO_PWM_I2C;
366 *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE1_GATE) |=
367 POWER_MODE_GATE_GPIO_PWM_I2C;
368 /* configure GPIO51 as output */
369 *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_HIGH) |=
372 /* Configure PSC1_4 as GPIO output for ATA reset */
373 *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
374 *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
378 void ide_set_reset (int idereset)
380 debug ("ide_reset(%d)\n", idereset);
382 #if defined (CONFIG_MINIFAP)
384 *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
387 *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
392 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
394 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
402 * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3
403 * is left open, no keypress is detected.
405 int post_hotkeys_pressed(void)
407 #ifdef CONFIG_STK52XX
408 struct mpc5xxx_gpio *gpio;
410 gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO;
413 * Configure PSC6_1 and PSC6_3 as GPIO. PSC6 then couldn't be used in
414 * CODEC or UART mode. Consumer IrDA should still be possible.
416 gpio->port_config &= ~(0x07000000);
417 gpio->port_config |= 0x03000000;
419 /* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */
420 gpio->simple_gpioe |= 0x20000000;
422 /* Configure GPIO_IRDA_1 as input */
423 gpio->simple_ddr &= ~(0x20000000);
425 return ((gpio->simple_ival & 0x20000000) ? 0 : 1);
432 #if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
434 void post_word_store (ulong a)
436 volatile ulong *save_addr =
437 (volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE);
442 ulong post_word_load (void)
444 volatile ulong *save_addr =
445 (volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE);
449 #endif /* CONFIG_POST || CONFIG_LOGBUFFER*/
451 #ifdef CONFIG_BOARD_EARLY_INIT_R
452 int board_early_init_r (void)
455 extern int usb_cpu_init(void);
457 #ifdef CONFIG_PS2MULT
458 ps2mult_early_init();
459 #endif /* CONFIG_PS2MULT */
461 #if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT)
462 /* Low level USB init, required for proper kernel operation */
471 int silent_boot (void)
473 vu_long timer3_status;
475 /* Configure GPT3 as GPIO input */
476 *(vu_long *)MPC5XXX_GPT3_ENABLE = 0x00000004;
478 /* Read in TIMER_3 pin status */
479 timer3_status = *(vu_long *)MPC5XXX_GPT3_STATUS;
481 #ifdef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED
482 /* Force silent console mode if S1 switch
483 * is in closed position (TIMER_3 pin status is LOW). */
484 if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 0)
487 /* Force silent console mode if S1 switch
488 * is in open position (TIMER_3 pin status is HIGH). */
489 if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 1)
496 int board_early_init_f (void)
499 gd->flags |= GD_FLG_SILENT;
503 #endif /* CONFIG_FO300 */
505 int last_stage_init (void)
508 * auto scan for really existing devices and re-set chip select
515 * Check for SRAM and SRAM size
518 /* save original SRAM content */
519 save = *(volatile u16 *)CFG_CS2_START;
522 /* write test pattern to SRAM */
523 *(volatile u16 *)CFG_CS2_START = 0xA5A5;
524 __asm__ volatile ("sync");
526 * Put a different pattern on the data lines: otherwise they may float
527 * long enough to read back what we wrote.
529 tmp = *(volatile u16 *)CFG_FLASH_BASE;
531 puts ("!! possible error in SRAM detection\n");
533 if (*(volatile u16 *)CFG_CS2_START != 0xA5A5) {
534 /* no SRAM at all, disable cs */
535 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18);
536 *(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF;
537 *(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF;
539 __asm__ volatile ("sync");
540 } else if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0xA5A5) {
541 /* make sure that we access a mirrored address */
542 *(volatile u16 *)CFG_CS2_START = 0x1111;
543 __asm__ volatile ("sync");
544 if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0x1111) {
545 /* SRAM size = 512 kByte */
546 *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CFG_CS2_START,
548 __asm__ volatile ("sync");
549 puts ("SRAM: 512 kB\n");
552 puts ("!! possible error in SRAM detection\n");
554 puts ("SRAM: 1 MB\n");
556 /* restore origianl SRAM content */
558 *(volatile u16 *)CFG_CS2_START = save;
559 __asm__ volatile ("sync");
562 #ifndef CONFIG_TQM5200S /* The TQM5200S has no SM501 grafic controller */
564 * Check for Grafic Controller
567 /* save origianl FB content */
568 save = *(volatile u16 *)CFG_CS1_START;
571 /* write test pattern to FB memory */
572 *(volatile u16 *)CFG_CS1_START = 0xA5A5;
573 __asm__ volatile ("sync");
575 * Put a different pattern on the data lines: otherwise they may float
576 * long enough to read back what we wrote.
578 tmp = *(volatile u16 *)CFG_FLASH_BASE;
580 puts ("!! possible error in grafic controller detection\n");
582 if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) {
583 /* no grafic controller at all, disable cs */
584 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17);
585 *(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF;
586 *(vu_long *)MPC5XXX_CS1_STOP = 0x0000FFFF;
588 __asm__ volatile ("sync");
590 puts ("VGA: SMI501 (Voyager) with 8 MB\n");
592 /* restore origianl FB content */
594 *(volatile u16 *)CFG_CS1_START = save;
595 __asm__ volatile ("sync");
600 setenv("bootdelay", "0");
604 #endif /* !CONFIG_TQM5200S */
609 #ifdef CONFIG_VIDEO_SM501
612 #define DISPLAY_WIDTH 800
614 #define DISPLAY_WIDTH 640
616 #define DISPLAY_HEIGHT 480
618 #ifdef CONFIG_VIDEO_SM501_8BPP
619 #error CONFIG_VIDEO_SM501_8BPP not supported.
620 #endif /* CONFIG_VIDEO_SM501_8BPP */
622 #ifdef CONFIG_VIDEO_SM501_16BPP
623 #error CONFIG_VIDEO_SM501_16BPP not supported.
624 #endif /* CONFIG_VIDEO_SM501_16BPP */
625 #ifdef CONFIG_VIDEO_SM501_32BPP
626 static const SMI_REGS init_regs [] =
630 {0x00048, 0x00021807},
631 {0x0004C, 0x10090a01},
633 {0x00040, 0x00021807},
634 {0x00044, 0x10090a01},
636 {0x80200, 0x00010000},
638 {0x80208, 0x0A000A00},
639 {0x8020C, 0x02fa027f},
640 {0x80210, 0x004a028b},
641 {0x80214, 0x020c01df},
642 {0x80218, 0x000201e9},
643 {0x80200, 0x00013306},
644 #else /* panel + CRT */
647 {0x00048, 0x00021807},
648 {0x0004C, 0x301a0a01},
650 {0x00040, 0x00021807},
651 {0x00044, 0x091a0a01},
653 {0x80000, 0x0f013106},
654 {0x80004, 0xc428bb17},
655 {0x8000C, 0x00000000},
656 {0x80010, 0x0C800C80},
657 {0x80014, 0x03200000},
658 {0x80018, 0x01e00000},
659 {0x8001C, 0x00000000},
660 {0x80020, 0x01e00320},
661 {0x80024, 0x042a031f},
662 {0x80028, 0x0086034a},
663 {0x8002C, 0x020c01df},
664 {0x80030, 0x000201ea},
665 {0x80200, 0x00010000},
668 {0x00048, 0x00021807},
669 {0x0004C, 0x091a0a01},
671 {0x00040, 0x00021807},
672 {0x00044, 0x091a0a01},
674 {0x80000, 0x0f013106},
675 {0x80004, 0xc428bb17},
676 {0x8000C, 0x00000000},
677 {0x80010, 0x0a000a00},
678 {0x80014, 0x02800000},
679 {0x80018, 0x01e00000},
680 {0x8001C, 0x00000000},
681 {0x80020, 0x01e00280},
682 {0x80024, 0x02fa027f},
683 {0x80028, 0x004a028b},
684 {0x8002C, 0x020c01df},
685 {0x80030, 0x000201e9},
686 {0x80200, 0x00010000},
687 #endif /* #ifdef CONFIG_FO300 */
691 #endif /* CONFIG_VIDEO_SM501_32BPP */
693 #ifdef CONFIG_CONSOLE_EXTRA_INFO
695 * Return text to be printed besides the logo.
697 void video_get_info_str (int line_number, char *info)
699 if (line_number == 1) {
700 strcpy (info, " Board: TQM5200 (TQ-Components GmbH)");
701 #if defined (CONFIG_STK52XX) || defined (CONFIG_TB5200) || defined(CONFIG_FO300)
702 } else if (line_number == 2) {
703 #if defined (CONFIG_STK52XX)
704 strcpy (info, " on a STK52xx carrier board");
706 #if defined (CONFIG_TB5200)
707 strcpy (info, " on a TB5200 carrier board");
709 #if defined (CONFIG_FO300)
710 strcpy (info, " on a FO300 carrier board");
721 * Returns SM501 register base address. First thing called in the
722 * driver. Checks if SM501 is physically present.
724 unsigned int board_video_init (void)
730 * Check for Grafic Controller
733 /* save origianl FB content */
734 save = *(volatile u16 *)CFG_CS1_START;
737 /* write test pattern to FB memory */
738 *(volatile u16 *)CFG_CS1_START = 0xA5A5;
739 __asm__ volatile ("sync");
741 * Put a different pattern on the data lines: otherwise they may float
742 * long enough to read back what we wrote.
744 tmp = *(volatile u16 *)CFG_FLASH_BASE;
746 puts ("!! possible error in grafic controller detection\n");
748 if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) {
749 /* no grafic controller found */
753 ret = SM501_MMIO_BASE;
757 *(volatile u16 *)CFG_CS1_START = save;
758 __asm__ volatile ("sync");
764 * Returns SM501 framebuffer address
766 unsigned int board_video_get_fb (void)
768 return SM501_FB_BASE;
772 * Called after initializing the SM501 and before clearing the screen.
774 void board_validate_screen (unsigned int base)
779 * Return a pointer to the initialization sequence.
781 const SMI_REGS *board_get_regs (void)
786 int board_get_width (void)
788 return DISPLAY_WIDTH;
791 int board_get_height (void)
793 return DISPLAY_HEIGHT;
796 #endif /* CONFIG_VIDEO_SM501 */
798 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
799 void ft_board_setup(void *blob, bd_t *bd)
801 ft_cpu_setup(blob, bd);
802 fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
804 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */