1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2012 Freescale Semiconductor, Inc.
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
6 * Copyright (C) 2013, 2014 TQ Systems (ported SabreSD to TQMa6x)
7 * Author: Markus Niebel <markus.niebel@tq-group.com>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/mx6-pins.h>
15 #include <asm/arch/imx-regs.h>
16 #include <asm/arch/iomux.h>
17 #include <asm/arch/sys_proto.h>
18 #include <linux/errno.h>
20 #include <asm/mach-imx/mxc_i2c.h>
23 #include <fsl_esdhc_imx.h>
24 #include <linux/libfdt.h>
34 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
35 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
37 #define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
38 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
40 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
41 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
43 #define GPIO_OUT_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
44 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
46 #define GPIO_IN_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
47 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
49 #define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
50 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
52 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
53 PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \
54 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
56 #if defined(CONFIG_TQMA6Q)
58 #define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII 0x02e0790
59 #define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM 0x02e07ac
61 #elif defined(CONFIG_TQMA6S) || defined(CONFIG_TQMA6DL)
63 #define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII 0x02e0768
64 #define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM 0x02e0788
68 #error "need to select module"
72 /* disable on die termination for RGMII */
73 #define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM_DISABLE 0x00000000
74 /* optimised drive strength for 1.0 .. 1.3 V signal on RGMII */
75 #define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P2V 0x00080000
76 /* optimised drive strength for 1.3 .. 2.5 V signal on RGMII */
77 #define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P5V 0x000C0000
79 static void mba6_setup_iomuxc_enet(void)
81 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
83 /* clear gpr1[ENET_CLK_SEL] for externel clock */
84 clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
86 __raw_writel(IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM_DISABLE,
87 (void *)IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM);
88 __raw_writel(IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P5V,
89 (void *)IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII);
92 static iomux_v3_cfg_t const mba6_uart2_pads[] = {
93 NEW_PAD_CTRL(MX6_PAD_SD4_DAT4__UART2_RX_DATA, UART_PAD_CTRL),
94 NEW_PAD_CTRL(MX6_PAD_SD4_DAT7__UART2_TX_DATA, UART_PAD_CTRL),
97 static void mba6_setup_iomuxc_uart(void)
99 imx_iomux_v3_setup_multiple_pads(mba6_uart2_pads,
100 ARRAY_SIZE(mba6_uart2_pads));
103 int board_mmc_get_env_dev(int devno)
106 * This assumes that the baseboard registered
107 * the boot device first ...
108 * Note: SDHC3 == idx2
110 return (2 == devno) ? 0 : 1;
113 int board_phy_config(struct phy_device *phydev)
116 * optimized pad skew values depends on CPU variant on the TQMa6x module:
117 * CONFIG_TQMA6Q: i.MX6Q/D
118 * CONFIG_TQMA6S: i.MX6S
119 * CONFIG_TQMA6DL: i.MX6DL
121 #if defined(CONFIG_TQMA6Q)
122 #define MBA6X_KSZ9031_CTRL_SKEW 0x0032
123 #define MBA6X_KSZ9031_CLK_SKEW 0x03ff
124 #define MBA6X_KSZ9031_RX_SKEW 0x3333
125 #define MBA6X_KSZ9031_TX_SKEW 0x2036
126 #elif defined(CONFIG_TQMA6S) || defined(CONFIG_TQMA6DL)
127 #define MBA6X_KSZ9031_CTRL_SKEW 0x0030
128 #define MBA6X_KSZ9031_CLK_SKEW 0x03ff
129 #define MBA6X_KSZ9031_RX_SKEW 0x3333
130 #define MBA6X_KSZ9031_TX_SKEW 0x2052
134 /* min rx/tx ctrl delay */
135 ksz9031_phy_extended_write(phydev, 2,
136 MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
137 MII_KSZ9031_MOD_DATA_NO_POST_INC,
138 MBA6X_KSZ9031_CTRL_SKEW);
140 ksz9031_phy_extended_write(phydev, 2,
141 MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
142 MII_KSZ9031_MOD_DATA_NO_POST_INC,
143 MBA6X_KSZ9031_RX_SKEW);
145 ksz9031_phy_extended_write(phydev, 2,
146 MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
147 MII_KSZ9031_MOD_DATA_NO_POST_INC,
148 MBA6X_KSZ9031_TX_SKEW);
150 ksz9031_phy_extended_write(phydev, 2,
151 MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
152 MII_KSZ9031_MOD_DATA_NO_POST_INC,
153 MBA6X_KSZ9031_CLK_SKEW);
155 phydev->drv->config(phydev);
160 int tqma6_bb_board_early_init_f(void)
162 mba6_setup_iomuxc_uart();
167 int tqma6_bb_board_init(void)
169 mba6_setup_iomuxc_enet();
174 int tqma6_bb_board_late_init(void)
179 const char *tqma6_bb_get_boardname(void)
185 * Device Tree Support
187 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
188 void tqma6_bb_ft_board_setup(void *blob, bd_t *bd)
192 #endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */