board/tqc/tqma6/tqma6_mba6.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2012 Freescale Semiconductor, Inc.
   4  * Author: Fabio Estevam <fabio.estevam@freescale.com>
   5  *
   6  * Copyright (C) 2013, 2014 TQ Systems (ported SabreSD to TQMa6x)
   7  * Author: Markus Niebel <markus.niebel@tq-group.com>
   8  */
   9
  10 #include <init.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/mx6-pins.h>
  14 #include <asm/arch/imx-regs.h>
  15 #include <asm/arch/iomux.h>
  16 #include <asm/arch/sys_proto.h>
  17 #include <linux/errno.h>
  18 #include <asm/gpio.h>
  19 #include <asm/mach-imx/mxc_i2c.h>
  20
  21 #include <common.h>
  22 #include <fsl_esdhc_imx.h>
  23 #include <linux/libfdt.h>
  24 #include <malloc.h>
  25 #include <i2c.h>
  26 #include <micrel.h>
  27 #include <miiphy.h>
  28 #include <mmc.h>
  29 #include <netdev.h>
  30
  31 #include "tqma6_bb.h"
  32
  33 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  34         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  35
  36 #define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW | \
  37         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  38
  39 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW | \
  40         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  41
  42 #define GPIO_OUT_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
  43         PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
  44
  45 #define GPIO_IN_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
  46         PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
  47
  48 #define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  49         PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  50
  51 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  52         PAD_CTL_DSE_80ohm | PAD_CTL_HYS |                       \
  53         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  54
  55 #if defined(CONFIG_TQMA6Q)
  56
  57 #define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII    0x02e0790
  58 #define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM        0x02e07ac
  59
  60 #elif defined(CONFIG_TQMA6S) || defined(CONFIG_TQMA6DL)
  61
  62 #define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII    0x02e0768
  63 #define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM        0x02e0788
  64
  65 #else
  66
  67 #error "need to select module"
  68
  69 #endif
  70
  71 /* disable on die termination for RGMII */
  72 #define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM_DISABLE        0x00000000
  73 /* optimised drive strength for 1.0 .. 1.3 V signal on RGMII */
  74 #define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P2V       0x00080000
  75 /* optimised drive strength for 1.3 .. 2.5 V signal on RGMII */
  76 #define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P5V       0x000C0000
  77
  78 static void mba6_setup_iomuxc_enet(void)
  79 {
  80         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  81
  82         /* clear gpr1[ENET_CLK_SEL] for externel clock */
  83         clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
  84
  85         __raw_writel(IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM_DISABLE,
  86                      (void *)IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM);
  87         __raw_writel(IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P5V,
  88                      (void *)IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII);
  89 }
  90
  91 static iomux_v3_cfg_t const mba6_uart2_pads[] = {
  92         NEW_PAD_CTRL(MX6_PAD_SD4_DAT4__UART2_RX_DATA, UART_PAD_CTRL),
  93         NEW_PAD_CTRL(MX6_PAD_SD4_DAT7__UART2_TX_DATA, UART_PAD_CTRL),
  94 };
  95
  96 static void mba6_setup_iomuxc_uart(void)
  97 {
  98         imx_iomux_v3_setup_multiple_pads(mba6_uart2_pads,
  99                                          ARRAY_SIZE(mba6_uart2_pads));
 100 }
 101
 102 int board_mmc_get_env_dev(int devno)
 103 {
 104         /*
 105          * This assumes that the baseboard registered
 106          * the boot device first ...
 107          * Note: SDHC3 == idx2
 108          */
 109         return (2 == devno) ? 0 : 1;
 110 }
 111
 112 int board_phy_config(struct phy_device *phydev)
 113 {
 114 /*
 115  * optimized pad skew values depends on CPU variant on the TQMa6x module:
 116  * CONFIG_TQMA6Q: i.MX6Q/D
 117  * CONFIG_TQMA6S: i.MX6S
 118  * CONFIG_TQMA6DL: i.MX6DL
 119  */
 120 #if defined(CONFIG_TQMA6Q)
 121 #define MBA6X_KSZ9031_CTRL_SKEW 0x0032
 122 #define MBA6X_KSZ9031_CLK_SKEW  0x03ff
 123 #define MBA6X_KSZ9031_RX_SKEW   0x3333
 124 #define MBA6X_KSZ9031_TX_SKEW   0x2036
 125 #elif defined(CONFIG_TQMA6S) || defined(CONFIG_TQMA6DL)
 126 #define MBA6X_KSZ9031_CTRL_SKEW 0x0030
 127 #define MBA6X_KSZ9031_CLK_SKEW  0x03ff
 128 #define MBA6X_KSZ9031_RX_SKEW   0x3333
 129 #define MBA6X_KSZ9031_TX_SKEW   0x2052
 130 #else
 131 #error
 132 #endif
 133         /* min rx/tx ctrl delay */
 134         ksz9031_phy_extended_write(phydev, 2,
 135                                    MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
 136                                    MII_KSZ9031_MOD_DATA_NO_POST_INC,
 137                                    MBA6X_KSZ9031_CTRL_SKEW);
 138         /* min rx delay */
 139         ksz9031_phy_extended_write(phydev, 2,
 140                                    MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
 141                                    MII_KSZ9031_MOD_DATA_NO_POST_INC,
 142                                    MBA6X_KSZ9031_RX_SKEW);
 143         /* max tx delay */
 144         ksz9031_phy_extended_write(phydev, 2,
 145                                    MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
 146                                    MII_KSZ9031_MOD_DATA_NO_POST_INC,
 147                                    MBA6X_KSZ9031_TX_SKEW);
 148         /* rx/tx clk skew */
 149         ksz9031_phy_extended_write(phydev, 2,
 150                                    MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
 151                                    MII_KSZ9031_MOD_DATA_NO_POST_INC,
 152                                    MBA6X_KSZ9031_CLK_SKEW);
 153
 154         phydev->drv->config(phydev);
 155
 156         return 0;
 157 }
 158
 159 int tqma6_bb_board_early_init_f(void)
 160 {
 161         mba6_setup_iomuxc_uart();
 162
 163         return 0;
 164 }
 165
 166 int tqma6_bb_board_init(void)
 167 {
 168         mba6_setup_iomuxc_enet();
 169
 170         return 0;
 171 }
 172
 173 int tqma6_bb_board_late_init(void)
 174 {
 175         return 0;
 176 }
 177
 178 const char *tqma6_bb_get_boardname(void)
 179 {
 180         return "MBa6x";
 181 }
 182
 183 /*
 184  * Device Tree Support
 185  */
 186 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
 187 void tqma6_bb_ft_board_setup(void *blob, bd_t *bd)
 188 {
 189  /* TBD */
 190 }
 191 #endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */