1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2012 Freescale Semiconductor, Inc.
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
6 * Copyright (C) 2013, 2014 TQ Systems (ported SabreSD to TQMa6x)
7 * Author: Markus Niebel <markus.niebel@tq-group.com>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/mx6-pins.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/iomux.h>
15 #include <asm/arch/sys_proto.h>
17 #include <linux/errno.h>
20 #include <asm/mach-imx/mxc_i2c.h>
21 #include <asm/mach-imx/spi.h>
23 #include <fsl_esdhc_imx.h>
24 #include <linux/libfdt.h>
27 #include <power/pfuze100_pmic.h>
28 #include <power/pmic.h>
29 #include <spi_flash.h>
33 DECLARE_GLOBAL_DATA_PTR;
35 #define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
36 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
38 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
39 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
41 #define GPIO_OUT_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
42 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
44 #define GPIO_IN_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
45 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
47 #define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
48 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
50 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
51 PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \
52 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
56 gd->ram_size = imx_ddr_size();
61 static const uint16_t tqma6_emmc_dsr = 0x0100;
63 /* eMMC on USDHCI3 always present */
64 static iomux_v3_cfg_t const tqma6_usdhc3_pads[] = {
65 NEW_PAD_CTRL(MX6_PAD_SD3_CLK__SD3_CLK, USDHC_PAD_CTRL),
66 NEW_PAD_CTRL(MX6_PAD_SD3_CMD__SD3_CMD, USDHC_PAD_CTRL),
67 NEW_PAD_CTRL(MX6_PAD_SD3_DAT0__SD3_DATA0, USDHC_PAD_CTRL),
68 NEW_PAD_CTRL(MX6_PAD_SD3_DAT1__SD3_DATA1, USDHC_PAD_CTRL),
69 NEW_PAD_CTRL(MX6_PAD_SD3_DAT2__SD3_DATA2, USDHC_PAD_CTRL),
70 NEW_PAD_CTRL(MX6_PAD_SD3_DAT3__SD3_DATA3, USDHC_PAD_CTRL),
71 NEW_PAD_CTRL(MX6_PAD_SD3_DAT4__SD3_DATA4, USDHC_PAD_CTRL),
72 NEW_PAD_CTRL(MX6_PAD_SD3_DAT5__SD3_DATA5, USDHC_PAD_CTRL),
73 NEW_PAD_CTRL(MX6_PAD_SD3_DAT6__SD3_DATA6, USDHC_PAD_CTRL),
74 NEW_PAD_CTRL(MX6_PAD_SD3_DAT7__SD3_DATA7, USDHC_PAD_CTRL),
76 NEW_PAD_CTRL(MX6_PAD_SD3_RST__SD3_RESET, GPIO_OUT_PAD_CTRL),
80 * According to board_mmc_init() the following map is done:
81 * (U-Boot device node) (Physical Port)
82 * mmc0 eMMC (SD3) on TQMa6
83 * mmc1 .. n optional slots used on baseboard
85 struct fsl_esdhc_cfg tqma6_usdhc_cfg = {
86 .esdhc_base = USDHC3_BASE_ADDR,
90 int board_mmc_getcd(struct mmc *mmc)
92 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
95 if (cfg->esdhc_base == USDHC3_BASE_ADDR)
96 /* eMMC/uSDHC3 is always present */
99 ret = tqma6_bb_board_mmc_getcd(mmc);
104 int board_mmc_getwp(struct mmc *mmc)
106 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
109 if (cfg->esdhc_base == USDHC3_BASE_ADDR)
110 /* eMMC/uSDHC3 is always present */
113 ret = tqma6_bb_board_mmc_getwp(mmc);
118 int board_mmc_init(bd_t *bis)
120 imx_iomux_v3_setup_multiple_pads(tqma6_usdhc3_pads,
121 ARRAY_SIZE(tqma6_usdhc3_pads));
122 tqma6_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
123 if (fsl_esdhc_initialize(bis, &tqma6_usdhc_cfg)) {
124 puts("Warning: failed to initialize eMMC dev\n");
126 struct mmc *mmc = find_mmc_device(0);
128 mmc_set_dsr(mmc, tqma6_emmc_dsr);
131 tqma6_bb_board_mmc_init(bis);
136 static iomux_v3_cfg_t const tqma6_ecspi1_pads[] = {
138 NEW_PAD_CTRL(MX6_PAD_EIM_D19__GPIO3_IO19, SPI_PAD_CTRL),
139 NEW_PAD_CTRL(MX6_PAD_EIM_D16__ECSPI1_SCLK, SPI_PAD_CTRL),
140 NEW_PAD_CTRL(MX6_PAD_EIM_D17__ECSPI1_MISO, SPI_PAD_CTRL),
141 NEW_PAD_CTRL(MX6_PAD_EIM_D18__ECSPI1_MOSI, SPI_PAD_CTRL),
144 #define TQMA6_SF_CS_GPIO IMX_GPIO_NR(3, 19)
146 static unsigned const tqma6_ecspi1_cs[] = {
150 __weak void tqma6_iomuxc_spi(void)
154 for (i = 0; i < ARRAY_SIZE(tqma6_ecspi1_cs); ++i)
155 gpio_direction_output(tqma6_ecspi1_cs[i], 1);
156 imx_iomux_v3_setup_multiple_pads(tqma6_ecspi1_pads,
157 ARRAY_SIZE(tqma6_ecspi1_pads));
160 #if defined(CONFIG_SF_DEFAULT_BUS) && defined(CONFIG_SF_DEFAULT_CS)
161 int board_spi_cs_gpio(unsigned bus, unsigned cs)
163 return ((bus == CONFIG_SF_DEFAULT_BUS) &&
164 (cs == CONFIG_SF_DEFAULT_CS)) ? TQMA6_SF_CS_GPIO : -1;
168 static struct i2c_pads_info tqma6_i2c3_pads = {
169 /* I2C3: on board LM75, M24C64, */
171 .i2c_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_5__I2C3_SCL,
173 .gpio_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_5__GPIO1_IO05,
175 .gp = IMX_GPIO_NR(1, 5)
178 .i2c_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_6__I2C3_SDA,
180 .gpio_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_6__GPIO1_IO06,
182 .gp = IMX_GPIO_NR(1, 6)
186 static void tqma6_setup_i2c(void)
190 * use logical index for bus, e.g. I2C1 -> 0
193 ret = setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &tqma6_i2c3_pads);
195 printf("setup I2C3 failed: %d\n", ret);
198 int board_early_init_f(void)
200 return tqma6_bb_board_early_init_f();
205 /* address of boot parameters */
206 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
211 tqma6_bb_board_init();
216 static const char *tqma6_get_boardname(void)
218 u32 cpurev = get_cpu_rev();
220 switch ((cpurev & 0xFF000) >> 12) {
221 case MXC_CPU_MX6SOLO:
238 /* setup board specific PMIC */
239 int power_init_board(void)
244 power_pfuze100_init(TQMA6_PFUZE100_I2C_BUS);
245 p = pmic_get("PFUZE100");
246 if (p && !pmic_probe(p)) {
247 pmic_reg_read(p, PFUZE100_DEVICEID, ®);
248 pmic_reg_read(p, PFUZE100_REVID, &rev);
249 printf("PMIC: PFUZE100 ID=0x%02x REV=0x%02x\n", reg, rev);
255 int board_late_init(void)
257 env_set("board_name", tqma6_get_boardname());
259 tqma6_bb_board_late_init();
266 printf("Board: %s on a %s\n", tqma6_get_boardname(),
267 tqma6_bb_get_boardname());
272 * Device Tree Support
274 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
275 #define MODELSTRLEN 32u
276 int ft_board_setup(void *blob, bd_t *bd)
278 char modelstr[MODELSTRLEN];
280 snprintf(modelstr, MODELSTRLEN, "TQ %s on %s", tqma6_get_boardname(),
281 tqma6_bb_get_boardname());
282 do_fixup_by_path_string(blob, "/", "model", modelstr);
283 fdt_fixup_memory(blob, (u64)PHYS_SDRAM, (u64)gd->ram_size);
284 /* bring in eMMC dsr settings */
285 do_fixup_by_path_u32(blob,
286 "/soc/aips-bus@02100000/usdhc@02198000",
287 "dsr", tqma6_emmc_dsr, 2);
288 tqma6_bb_ft_board_setup(blob, bd);
292 #endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */