3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
26 #include <asm/immap_85xx.h>
27 #include <asm/processor.h>
35 typedef struct sdram_conf_s sdram_conf_t;
37 sdram_conf_t ddr_cs_conf[] = {
38 {(512 << 20), 0x80000202}, /* 512MB, 14x10(4) */
39 {(256 << 20), 0x80000102}, /* 256MB, 13x10(4) */
40 {(128 << 20), 0x80000101}, /* 128MB, 13x9(4) */
41 {( 64 << 20), 0x80000001}, /* 64MB, 12x9(4) */
44 #define N_DDR_CS_CONF (sizeof(ddr_cs_conf) / sizeof(ddr_cs_conf[0]))
46 int cas_latency (void);
49 * Autodetect onboard DDR SDRAM on 85xx platforms
51 * NOTE: Some of the hardcoded values are hardware dependant,
52 * so this should be extended for other future boards
55 long int sdram_setup (int casl)
58 volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR);
59 unsigned long cfg_ddr_timing1;
60 unsigned long cfg_ddr_mode;
63 * Disable memory controller.
70 cfg_ddr_timing1 = 0x47405331 | (3 << 16);
71 cfg_ddr_mode = 0x40020002 | (2 << 4);
75 cfg_ddr_timing1 = 0x47405331 | (4 << 16);
76 cfg_ddr_mode = 0x40020002 | (6 << 4);
81 cfg_ddr_timing1 = 0x47405331 | (5 << 16);
82 cfg_ddr_mode = 0x40020002 | (3 << 4);
86 ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24;
87 ddr->cs0_config = ddr_cs_conf[0].reg;
88 ddr->timing_cfg_1 = cfg_ddr_timing1;
89 ddr->timing_cfg_2 = 0x00000800; /* P9-45,may need tuning */
90 ddr->sdram_mode = cfg_ddr_mode;
91 ddr->sdram_interval = 0x05160100; /* autocharge,no open page */
92 ddr->err_disable = 0x0000000D;
94 asm ("sync; isync; msync");
97 ddr->sdram_cfg = 0xc2000000; /* unbuffered,no DYN_PWR */
98 asm ("sync; isync; msync");
101 for (i = 0; i < N_DDR_CS_CONF; i++) {
102 ddr->cs0_config = ddr_cs_conf[i].reg;
104 if (get_ram_size (0, ddr_cs_conf[i].size) ==
105 ddr_cs_conf[i].size) {
107 * size detected -> set Chip Select Bounds Register
109 ddr->cs0_bnds = (ddr_cs_conf[i].size - 1) >> 24;
111 return ddr_cs_conf[i].size;
115 return 0; /* nothing found ! */
118 void board_add_ram_info (int use_default)
123 casl = CONFIG_DDR_DEFAULT_CL;
125 casl = cas_latency ();
143 long int initdram (int board_type)
148 #if defined(CONFIG_DDR_DLL)
150 * This DLL-Override only used on TQM8540 and TQM8560
153 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
159 * Work around to stabilize DDR DLL
161 gur->ddrdllcr = 0x81000000;
162 asm ("sync; isync; msync");
164 while (gur->ddrdllcr != 0x81000100) {
165 gur->devdisr = gur->devdisr | 0x00010000;
166 asm ("sync; isync; msync");
167 for (i = 0; i < x; i++)
169 gur->devdisr = gur->devdisr & 0xfff7ffff;
170 asm ("sync; isync; msync");
176 casl = cas_latency ();
177 dram_size = sdram_setup (casl);
178 if ((dram_size == 0) && (casl != CONFIG_DDR_DEFAULT_CL)) {
180 * Try again with default CAS latency
182 puts ("Problem with CAS lantency");
183 board_add_ram_info (1);
184 puts (", using default CL!\n");
185 casl = CONFIG_DDR_DEFAULT_CL;
186 dram_size = sdram_setup (casl);
193 #if defined(CFG_DRAM_TEST)
196 uint *pstart = (uint *) CFG_MEMTEST_START;
197 uint *pend = (uint *) CFG_MEMTEST_END;
200 printf ("SDRAM test phase 1:\n");
201 for (p = pstart; p < pend; p++)
204 for (p = pstart; p < pend; p++) {
205 if (*p != 0xaaaaaaaa) {
206 printf ("SDRAM test fails at: %08x\n", (uint) p);
211 printf ("SDRAM test phase 2:\n");
212 for (p = pstart; p < pend; p++)
215 for (p = pstart; p < pend; p++) {
216 if (*p != 0x55555555) {
217 printf ("SDRAM test fails at: %08x\n", (uint) p);
222 printf ("SDRAM test passed.\n");