2 * (C) Copyright 2003-2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
8 * (C) Copyright 2004-2006
9 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
11 * SPDX-License-Identifier: GPL-2.0+
18 #include <asm/processor.h>
22 #ifdef CONFIG_VIDEO_SM501
26 #if defined(CONFIG_MPC5200_DDR)
27 #include "mt46v16m16-75.h"
29 #include "mt48lc16m16a2-75.h"
32 #ifdef CONFIG_OF_LIBFDT
33 #include <fdt_support.h>
34 #endif /* CONFIG_OF_LIBFDT */
36 DECLARE_GLOBAL_DATA_PTR;
39 void ps2mult_early_init(void);
42 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) && \
45 * EDID block has been generated using Phoenix EDID Designer 1.3.
46 * This tool creates a text file containing:
50 * 0x 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
51 * ------------------------------------------------
52 * 00 | 00 FF FF FF FF FF FF 00 04 21 00 00 00 00 00 00
53 * 10 | 01 00 01 03 00 00 00 00 00 00 00 00 00 00 00 00
54 * 20 | 00 00 00 21 00 00 01 01 01 01 01 01 01 01 01 01
55 * 30 | 01 01 01 01 01 01 64 00 00 00 00 00 00 00 00 00
56 * 40 | 00 00 00 00 00 00 00 00 00 00 00 10 00 00 00 00
57 * 50 | 00 00 00 00 00 00 00 00 00 00 00 00 00 10 00 00
58 * 60 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10
59 * 70 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 17
61 * Then this data has been manually converted to the char
64 static unsigned char edid_buf[128] = {
65 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
66 0x04, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
67 0x01, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00,
68 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
69 0x00, 0x00, 0x00, 0x21, 0x00, 0x00, 0x01, 0x01,
70 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
71 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x64, 0x00,
72 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
73 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
74 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00,
75 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
76 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00,
77 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
78 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
79 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
80 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x17,
84 #ifndef CONFIG_SYS_RAMBOOT
85 static void sdram_start (int hi_addr)
87 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
89 /* unlock mode register */
90 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
92 __asm__ volatile ("sync");
94 /* precharge all banks */
95 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
97 __asm__ volatile ("sync");
100 /* set mode register: extended mode */
101 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
102 __asm__ volatile ("sync");
104 /* set mode register: reset DLL */
105 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
106 __asm__ volatile ("sync");
109 /* precharge all banks */
110 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
112 __asm__ volatile ("sync");
115 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
117 __asm__ volatile ("sync");
119 /* set mode register */
120 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
121 __asm__ volatile ("sync");
123 /* normal operation */
124 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
125 __asm__ volatile ("sync");
130 * ATTENTION: Although partially referenced initdram does NOT make real use
131 * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
132 * is something else than 0x00000000.
135 phys_size_t initdram (int board_type)
141 #ifndef CONFIG_SYS_RAMBOOT
144 /* setup SDRAM chip selects */
145 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
146 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
147 __asm__ volatile ("sync");
149 /* setup config registers */
150 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
151 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
152 __asm__ volatile ("sync");
156 *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
157 __asm__ volatile ("sync");
160 /* find RAM size using SDRAM CS0 only */
162 test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
164 test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
172 /* memory smaller than 1MB is impossible */
173 if (dramsize < (1 << 20)) {
177 /* set SDRAM CS0 size according to the amount of RAM found */
179 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
180 __builtin_ffs(dramsize >> 20) - 1;
182 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
185 /* let SDRAM CS1 start right after CS0 */
186 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */
188 /* find RAM size using SDRAM CS1 only */
191 test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
194 test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
203 /* memory smaller than 1MB is impossible */
204 if (dramsize2 < (1 << 20)) {
208 /* set SDRAM CS1 size according to the amount of RAM found */
210 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
211 | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
213 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
216 #else /* CONFIG_SYS_RAMBOOT */
218 /* retrieve size of memory connected to SDRAM CS0 */
219 dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
220 if (dramsize >= 0x13) {
221 dramsize = (1 << (dramsize - 0x13)) << 20;
226 /* retrieve size of memory connected to SDRAM CS1 */
227 dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
228 if (dramsize2 >= 0x13) {
229 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
233 #endif /* CONFIG_SYS_RAMBOOT */
236 * On MPC5200B we need to set the special configuration delay in the
237 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
238 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
240 * "The SDelay should be written to a value of 0x00000004. It is
241 * required to account for changes caused by normal wafer processing
246 if ((SVR_MJREV(svr) >= 2) &&
247 (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
249 *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
250 __asm__ volatile ("sync");
253 #if defined(CONFIG_TQM5200_B)
254 return dramsize + dramsize2;
257 #endif /* CONFIG_TQM5200_B */
260 int checkboard (void)
262 #if defined(CONFIG_TQM5200S)
263 # define MODULE_NAME "TQM5200S"
265 # define MODULE_NAME "TQM5200"
268 #if defined(CONFIG_STK52XX)
269 # define CARRIER_NAME "STK52xx"
270 #elif defined(CONFIG_CAM5200)
271 # define CARRIER_NAME "CAM5200"
272 #elif defined(CONFIG_FO300)
273 # define CARRIER_NAME "FO300"
274 #elif defined(CONFIG_CHARON)
275 # define CARRIER_NAME "CHARON"
280 puts ( "Board: " MODULE_NAME " (TQ-Components GmbH)\n"
281 " on a " CARRIER_NAME " carrier board\n");
289 void flash_preinit(void)
292 * Now, when we are in RAM, enable flash write
293 * access for detection process.
294 * Note that CS_BOOT cannot be cleared when
295 * executing in flash.
297 *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
302 static struct pci_controller hose;
304 extern void pci_mpc5xxx_init(struct pci_controller *);
306 void pci_init_board(void)
308 pci_mpc5xxx_init(&hose);
312 #if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
314 #if defined (CONFIG_MINIFAP)
315 #define SM501_POWER_MODE0_GATE 0x00000040UL
316 #define SM501_POWER_MODE1_GATE 0x00000048UL
317 #define POWER_MODE_GATE_GPIO_PWM_I2C 0x00000040UL
318 #define SM501_GPIO_DATA_DIR_HIGH 0x0001000CUL
319 #define SM501_GPIO_DATA_HIGH 0x00010004UL
320 #define SM501_GPIO_51 0x00080000UL
321 #endif /* CONFIG MINIFAP */
323 void init_ide_reset (void)
325 debug ("init_ide_reset\n");
327 #if defined (CONFIG_MINIFAP)
328 /* Configure GPIO_51 of the SM501 grafic controller as ATA reset */
330 /* enable GPIO control (in both power modes) */
331 *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE0_GATE) |=
332 POWER_MODE_GATE_GPIO_PWM_I2C;
333 *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE1_GATE) |=
334 POWER_MODE_GATE_GPIO_PWM_I2C;
335 /* configure GPIO51 as output */
336 *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_HIGH) |=
339 /* Configure PSC1_4 as GPIO output for ATA reset */
340 *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
341 *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
343 /* by default the ATA reset is de-asserted */
344 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
348 void ide_set_reset (int idereset)
350 debug ("ide_reset(%d)\n", idereset);
352 #if defined (CONFIG_MINIFAP)
354 *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
357 *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
362 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
364 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
372 * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3
373 * is left open, no keypress is detected.
375 int post_hotkeys_pressed(void)
377 #ifdef CONFIG_STK52XX
378 struct mpc5xxx_gpio *gpio;
380 gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO;
383 * Configure PSC6_0 through PSC6_3 as GPIO.
385 gpio->port_config &= ~(0x00700000);
387 /* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */
388 gpio->simple_gpioe |= 0x20000000;
390 /* Configure GPIO_IRDA_1 as input */
391 gpio->simple_ddr &= ~(0x20000000);
393 return ((gpio->simple_ival & 0x20000000) ? 0 : 1);
400 #ifdef CONFIG_BOARD_EARLY_INIT_R
401 int board_early_init_r (void)
404 extern int usb_cpu_init(void);
406 #ifdef CONFIG_PS2MULT
407 ps2mult_early_init();
408 #endif /* CONFIG_PS2MULT */
410 #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
411 /* Low level USB init, required for proper kernel operation */
420 int silent_boot (void)
422 vu_long timer3_status;
424 /* Configure GPT3 as GPIO input */
425 *(vu_long *)MPC5XXX_GPT3_ENABLE = 0x00000004;
427 /* Read in TIMER_3 pin status */
428 timer3_status = *(vu_long *)MPC5XXX_GPT3_STATUS;
430 #ifdef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED
431 /* Force silent console mode if S1 switch
432 * is in closed position (TIMER_3 pin status is LOW). */
433 if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 0)
436 /* Force silent console mode if S1 switch
437 * is in open position (TIMER_3 pin status is HIGH). */
438 if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 1)
445 int board_early_init_f (void)
448 gd->flags |= GD_FLG_SILENT;
452 #endif /* CONFIG_FO300 */
454 #if defined(CONFIG_CHARON)
458 /* The TFP410 registers */
459 #define TFP410_REG_VEN_ID_L 0x00
460 #define TFP410_REG_VEN_ID_H 0x01
461 #define TFP410_REG_DEV_ID_L 0x02
462 #define TFP410_REG_DEV_ID_H 0x03
463 #define TFP410_REG_REV_ID 0x04
465 #define TFP410_REG_CTL_1_MODE 0x08
466 #define TFP410_REG_CTL_2_MODE 0x09
467 #define TFP410_REG_CTL_3_MODE 0x0A
469 #define TFP410_REG_CFG 0x0B
471 #define TFP410_REG_DE_DLY 0x32
472 #define TFP410_REG_DE_CTL 0x33
473 #define TFP410_REG_DE_TOP 0x34
474 #define TFP410_REG_DE_CNT_L 0x36
475 #define TFP410_REG_DE_CNT_H 0x37
476 #define TFP410_REG_DE_LIN_L 0x38
477 #define TFP410_REG_DE_LIN_H 0x39
479 #define TFP410_REG_H_RES_L 0x3A
480 #define TFP410_REG_H_RES_H 0x3B
481 #define TFP410_REG_V_RES_L 0x3C
482 #define TFP410_REG_V_RES_H 0x3D
484 static int tfp410_read_reg(int reg, uchar *buf)
486 if (i2c_read(CONFIG_SYS_TFP410_ADDR, reg, 1, buf, 1) != 0) {
487 puts ("Error reading the chip.\n");
493 static int tfp410_write_reg(int reg, uchar buf)
495 if (i2c_write(CONFIG_SYS_TFP410_ADDR, reg, 1, &buf, 1) != 0) {
496 puts ("Error writing the chip.\n");
502 typedef struct _tfp410_config {
507 static TFP410_CONFIG tfp410_configtbl[] = {
508 {TFP410_REG_CTL_1_MODE, 0x37},
509 {TFP410_REG_CTL_2_MODE, 0x20},
510 {TFP410_REG_CTL_3_MODE, 0x80},
511 {TFP410_REG_DE_DLY, 0x90},
512 {TFP410_REG_DE_CTL, 0x00},
513 {TFP410_REG_DE_TOP, 0x23},
514 {TFP410_REG_DE_CNT_H, 0x02},
515 {TFP410_REG_DE_CNT_L, 0x80},
516 {TFP410_REG_DE_LIN_H, 0x01},
517 {TFP410_REG_DE_LIN_L, 0xe0},
521 static int charon_last_stage_init(void)
523 volatile struct mpc5xxx_lpb *lpb =
524 (struct mpc5xxx_lpb *) MPC5XXX_LPB;
525 int oldbus = i2c_get_bus_num();
529 i2c_set_bus_num(CONFIG_SYS_TFP410_BUS);
532 if (tfp410_read_reg(TFP410_REG_DEV_ID_H, &buf) != 0)
536 if (tfp410_read_reg(TFP410_REG_DEV_ID_L, &buf) != 0)
540 /* OK, now init the chip */
541 while (tfp410_configtbl[i].reg != -1) {
544 ret = tfp410_write_reg(tfp410_configtbl[i].reg,
545 tfp410_configtbl[i].val);
550 printf("TFP410 initialized.\n");
551 i2c_set_bus_num(oldbus);
553 /* set deadcycle for cs3 to 0 */
554 setbits_be32(&lpb->cs_deadcycle, 0xffffcfff);
559 int last_stage_init (void)
562 * auto scan for really existing devices and re-set chip select
569 * Check for SRAM and SRAM size
572 /* save original SRAM content */
573 save = *(volatile u16 *)CONFIG_SYS_CS2_START;
576 /* write test pattern to SRAM */
577 *(volatile u16 *)CONFIG_SYS_CS2_START = 0xA5A5;
578 __asm__ volatile ("sync");
580 * Put a different pattern on the data lines: otherwise they may float
581 * long enough to read back what we wrote.
583 tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
585 puts ("!! possible error in SRAM detection\n");
587 if (*(volatile u16 *)CONFIG_SYS_CS2_START != 0xA5A5) {
588 /* no SRAM at all, disable cs */
589 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18);
590 *(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF;
591 *(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF;
593 __asm__ volatile ("sync");
594 } else if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0xA5A5) {
595 /* make sure that we access a mirrored address */
596 *(volatile u16 *)CONFIG_SYS_CS2_START = 0x1111;
597 __asm__ volatile ("sync");
598 if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0x1111) {
599 /* SRAM size = 512 kByte */
600 *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CONFIG_SYS_CS2_START,
602 __asm__ volatile ("sync");
603 puts ("SRAM: 512 kB\n");
606 puts ("!! possible error in SRAM detection\n");
608 puts ("SRAM: 1 MB\n");
610 /* restore origianl SRAM content */
612 *(volatile u16 *)CONFIG_SYS_CS2_START = save;
613 __asm__ volatile ("sync");
616 #ifndef CONFIG_TQM5200S /* The TQM5200S has no SM501 grafic controller */
618 * Check for Grafic Controller
621 /* save origianl FB content */
622 save = *(volatile u16 *)CONFIG_SYS_CS1_START;
625 /* write test pattern to FB memory */
626 *(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5;
627 __asm__ volatile ("sync");
629 * Put a different pattern on the data lines: otherwise they may float
630 * long enough to read back what we wrote.
632 tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
634 puts ("!! possible error in grafic controller detection\n");
636 if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) {
637 /* no grafic controller at all, disable cs */
638 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17);
639 *(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF;
640 *(vu_long *)MPC5XXX_CS1_STOP = 0x0000FFFF;
642 __asm__ volatile ("sync");
644 puts ("VGA: SMI501 (Voyager) with 8 MB\n");
646 /* restore origianl FB content */
648 *(volatile u16 *)CONFIG_SYS_CS1_START = save;
649 __asm__ volatile ("sync");
654 setenv("bootdelay", "0");
658 #endif /* !CONFIG_TQM5200S */
660 #if defined(CONFIG_CHARON)
661 charon_last_stage_init();
666 #ifdef CONFIG_VIDEO_SM501
669 #define DISPLAY_WIDTH 800
671 #define DISPLAY_WIDTH 640
673 #define DISPLAY_HEIGHT 480
675 #ifdef CONFIG_VIDEO_SM501_8BPP
676 #error CONFIG_VIDEO_SM501_8BPP not supported.
677 #endif /* CONFIG_VIDEO_SM501_8BPP */
679 #ifdef CONFIG_VIDEO_SM501_16BPP
680 #error CONFIG_VIDEO_SM501_16BPP not supported.
681 #endif /* CONFIG_VIDEO_SM501_16BPP */
682 #ifdef CONFIG_VIDEO_SM501_32BPP
683 static const SMI_REGS init_regs [] =
687 {0x00048, 0x00021807},
688 {0x0004C, 0x10090a01},
690 {0x00040, 0x00021807},
691 {0x00044, 0x10090a01},
693 {0x80200, 0x00010000},
695 {0x80208, 0x0A000A00},
696 {0x8020C, 0x02fa027f},
697 {0x80210, 0x004a028b},
698 {0x80214, 0x020c01df},
699 {0x80218, 0x000201e9},
700 {0x80200, 0x00013306},
701 #else /* panel + CRT */
704 {0x00048, 0x00021807},
705 {0x0004C, 0x301a0a01},
707 {0x00040, 0x00021807},
708 {0x00044, 0x091a0a01},
710 {0x80000, 0x0f013106},
711 {0x80004, 0xc428bb17},
712 {0x8000C, 0x00000000},
713 {0x80010, 0x0C800C80},
714 {0x80014, 0x03200000},
715 {0x80018, 0x01e00000},
716 {0x8001C, 0x00000000},
717 {0x80020, 0x01e00320},
718 {0x80024, 0x042a031f},
719 {0x80028, 0x0086034a},
720 {0x8002C, 0x020c01df},
721 {0x80030, 0x000201ea},
722 {0x80200, 0x00010000},
725 {0x00048, 0x00021807},
726 {0x0004C, 0x091a0a01},
728 {0x00040, 0x00021807},
729 {0x00044, 0x091a0a01},
731 {0x80000, 0x0f013106},
732 {0x80004, 0xc428bb17},
733 {0x8000C, 0x00000000},
734 {0x80010, 0x0a000a00},
735 {0x80014, 0x02800000},
736 {0x80018, 0x01e00000},
737 {0x8001C, 0x00000000},
738 {0x80020, 0x01e00280},
739 {0x80024, 0x02fa027f},
740 {0x80028, 0x004a028b},
741 {0x8002C, 0x020c01df},
742 {0x80030, 0x000201e9},
743 {0x80200, 0x00010000},
744 #endif /* #ifdef CONFIG_FO300 */
748 #endif /* CONFIG_VIDEO_SM501_32BPP */
750 #ifdef CONFIG_CONSOLE_EXTRA_INFO
752 * Return text to be printed besides the logo.
754 void video_get_info_str (int line_number, char *info)
756 if (line_number == 1) {
757 strcpy (info, " Board: TQM5200 (TQ-Components GmbH)");
758 #if defined (CONFIG_CHARON) || defined (CONFIG_FO300) || \
759 defined(CONFIG_STK52XX)
760 } else if (line_number == 2) {
761 #if defined (CONFIG_CHARON)
762 strcpy (info, " on a CHARON carrier board");
764 #if defined (CONFIG_STK52XX)
765 strcpy (info, " on a STK52xx carrier board");
767 #if defined (CONFIG_FO300)
768 strcpy (info, " on a FO300 carrier board");
779 * Returns SM501 register base address. First thing called in the
780 * driver. Checks if SM501 is physically present.
782 unsigned int board_video_init (void)
788 * Check for Grafic Controller
791 /* save origianl FB content */
792 save = *(volatile u16 *)CONFIG_SYS_CS1_START;
795 /* write test pattern to FB memory */
796 *(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5;
797 __asm__ volatile ("sync");
799 * Put a different pattern on the data lines: otherwise they may float
800 * long enough to read back what we wrote.
802 tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
804 puts ("!! possible error in grafic controller detection\n");
806 if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) {
807 /* no grafic controller found */
811 ret = SM501_MMIO_BASE;
815 *(volatile u16 *)CONFIG_SYS_CS1_START = save;
816 __asm__ volatile ("sync");
822 * Returns SM501 framebuffer address
824 unsigned int board_video_get_fb (void)
826 return SM501_FB_BASE;
830 * Called after initializing the SM501 and before clearing the screen.
832 void board_validate_screen (unsigned int base)
837 * Return a pointer to the initialization sequence.
839 const SMI_REGS *board_get_regs (void)
844 int board_get_width (void)
846 return DISPLAY_WIDTH;
849 int board_get_height (void)
851 return DISPLAY_HEIGHT;
854 #endif /* CONFIG_VIDEO_SM501 */
856 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
857 int ft_board_setup(void *blob, bd_t *bd)
859 ft_cpu_setup(blob, bd);
860 #if defined(CONFIG_VIDEO)
861 fdt_add_edid(blob, "smi,sm501", edid_buf);
866 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
868 #if defined(CONFIG_RESET_PHY_R)
873 /* init Micrel KSZ8993 PHY */
874 miiphy_write("FEC", CONFIG_PHY_ADDR, 0x01, 0x09);
878 int board_eth_init(bd_t *bis)
880 cpu_eth_init(bis); /* Built in FEC comes first */
881 return pci_eth_init(bis);