2 * (C) Copyright 2003-2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
8 * (C) Copyright 2004-2006
9 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #include <asm/processor.h>
37 #ifdef CONFIG_VIDEO_SM501
41 #if defined(CONFIG_MPC5200_DDR)
42 #include "mt46v16m16-75.h"
44 #include "mt48lc16m16a2-75.h"
47 #ifdef CONFIG_OF_LIBFDT
48 #include <fdt_support.h>
49 #endif /* CONFIG_OF_LIBFDT */
51 DECLARE_GLOBAL_DATA_PTR;
54 void ps2mult_early_init(void);
57 #if defined(CONFIG_VIDEO)
59 * EDID block has been generated using Phoenix EDID Designer 1.3.
60 * This tool creates a text file containing:
64 * 0x 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
65 * ------------------------------------------------
66 * 00 | 00 FF FF FF FF FF FF 00 04 21 00 00 00 00 00 00
67 * 10 | 01 00 01 03 00 00 00 00 00 00 00 00 00 00 00 00
68 * 20 | 00 00 00 21 00 00 01 01 01 01 01 01 01 01 01 01
69 * 30 | 01 01 01 01 01 01 64 00 00 00 00 00 00 00 00 00
70 * 40 | 00 00 00 00 00 00 00 00 00 00 00 10 00 00 00 00
71 * 50 | 00 00 00 00 00 00 00 00 00 00 00 00 00 10 00 00
72 * 60 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10
73 * 70 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 17
75 * Then this data has been manually converted to the char
78 static unsigned char edid_buf[128] = {
79 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
80 0x04, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
81 0x01, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00,
82 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
83 0x00, 0x00, 0x00, 0x21, 0x00, 0x00, 0x01, 0x01,
84 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
85 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x64, 0x00,
86 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
87 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
88 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00,
89 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
90 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00,
91 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
92 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
93 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
94 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x17,
98 #ifndef CONFIG_SYS_RAMBOOT
99 static void sdram_start (int hi_addr)
101 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
103 /* unlock mode register */
104 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
106 __asm__ volatile ("sync");
108 /* precharge all banks */
109 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
111 __asm__ volatile ("sync");
114 /* set mode register: extended mode */
115 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
116 __asm__ volatile ("sync");
118 /* set mode register: reset DLL */
119 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
120 __asm__ volatile ("sync");
123 /* precharge all banks */
124 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
126 __asm__ volatile ("sync");
129 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
131 __asm__ volatile ("sync");
133 /* set mode register */
134 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
135 __asm__ volatile ("sync");
137 /* normal operation */
138 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
139 __asm__ volatile ("sync");
144 * ATTENTION: Although partially referenced initdram does NOT make real use
145 * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
146 * is something else than 0x00000000.
149 phys_size_t initdram (int board_type)
155 #ifndef CONFIG_SYS_RAMBOOT
158 /* setup SDRAM chip selects */
159 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
160 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
161 __asm__ volatile ("sync");
163 /* setup config registers */
164 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
165 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
166 __asm__ volatile ("sync");
170 *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
171 __asm__ volatile ("sync");
174 /* find RAM size using SDRAM CS0 only */
176 test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
178 test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
186 /* memory smaller than 1MB is impossible */
187 if (dramsize < (1 << 20)) {
191 /* set SDRAM CS0 size according to the amount of RAM found */
193 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
194 __builtin_ffs(dramsize >> 20) - 1;
196 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
199 /* let SDRAM CS1 start right after CS0 */
200 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */
202 /* find RAM size using SDRAM CS1 only */
205 test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
208 test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
217 /* memory smaller than 1MB is impossible */
218 if (dramsize2 < (1 << 20)) {
222 /* set SDRAM CS1 size according to the amount of RAM found */
224 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
225 | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
227 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
230 #else /* CONFIG_SYS_RAMBOOT */
232 /* retrieve size of memory connected to SDRAM CS0 */
233 dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
234 if (dramsize >= 0x13) {
235 dramsize = (1 << (dramsize - 0x13)) << 20;
240 /* retrieve size of memory connected to SDRAM CS1 */
241 dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
242 if (dramsize2 >= 0x13) {
243 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
247 #endif /* CONFIG_SYS_RAMBOOT */
250 * On MPC5200B we need to set the special configuration delay in the
251 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
252 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
254 * "The SDelay should be written to a value of 0x00000004. It is
255 * required to account for changes caused by normal wafer processing
260 if ((SVR_MJREV(svr) >= 2) &&
261 (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
263 *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
264 __asm__ volatile ("sync");
267 #if defined(CONFIG_TQM5200_B)
268 return dramsize + dramsize2;
271 #endif /* CONFIG_TQM5200_B */
274 int checkboard (void)
276 #if defined(CONFIG_AEVFIFO)
277 puts ("Board: AEVFIFO\n");
281 #if defined(CONFIG_TQM5200S)
282 # define MODULE_NAME "TQM5200S"
284 # define MODULE_NAME "TQM5200"
287 #if defined(CONFIG_STK52XX)
288 # define CARRIER_NAME "STK52xx"
289 #elif defined(CONFIG_TB5200)
290 # define CARRIER_NAME "TB5200"
291 #elif defined(CONFIG_CAM5200)
292 # define CARRIER_NAME "CAM5200"
293 #elif defined(CONFIG_FO300)
294 # define CARRIER_NAME "FO300"
295 #elif defined(CONFIG_CHARON)
296 # define CARRIER_NAME "CHARON"
301 puts ( "Board: " MODULE_NAME " (TQ-Components GmbH)\n"
302 " on a " CARRIER_NAME " carrier board\n");
310 void flash_preinit(void)
313 * Now, when we are in RAM, enable flash write
314 * access for detection process.
315 * Note that CS_BOOT cannot be cleared when
316 * executing in flash.
318 *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
323 static struct pci_controller hose;
325 extern void pci_mpc5xxx_init(struct pci_controller *);
327 void pci_init_board(void)
329 pci_mpc5xxx_init(&hose);
333 #if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
335 #if defined (CONFIG_MINIFAP)
336 #define SM501_POWER_MODE0_GATE 0x00000040UL
337 #define SM501_POWER_MODE1_GATE 0x00000048UL
338 #define POWER_MODE_GATE_GPIO_PWM_I2C 0x00000040UL
339 #define SM501_GPIO_DATA_DIR_HIGH 0x0001000CUL
340 #define SM501_GPIO_DATA_HIGH 0x00010004UL
341 #define SM501_GPIO_51 0x00080000UL
342 #endif /* CONFIG MINIFAP */
344 void init_ide_reset (void)
346 debug ("init_ide_reset\n");
348 #if defined (CONFIG_MINIFAP)
349 /* Configure GPIO_51 of the SM501 grafic controller as ATA reset */
351 /* enable GPIO control (in both power modes) */
352 *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE0_GATE) |=
353 POWER_MODE_GATE_GPIO_PWM_I2C;
354 *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE1_GATE) |=
355 POWER_MODE_GATE_GPIO_PWM_I2C;
356 /* configure GPIO51 as output */
357 *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_HIGH) |=
360 /* Configure PSC1_4 as GPIO output for ATA reset */
361 *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
362 *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
364 /* by default the ATA reset is de-asserted */
365 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
369 void ide_set_reset (int idereset)
371 debug ("ide_reset(%d)\n", idereset);
373 #if defined (CONFIG_MINIFAP)
375 *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
378 *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
383 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
385 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
393 * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3
394 * is left open, no keypress is detected.
396 int post_hotkeys_pressed(void)
398 #ifdef CONFIG_STK52XX
399 struct mpc5xxx_gpio *gpio;
401 gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO;
404 * Configure PSC6_0 through PSC6_3 as GPIO.
406 gpio->port_config &= ~(0x00700000);
408 /* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */
409 gpio->simple_gpioe |= 0x20000000;
411 /* Configure GPIO_IRDA_1 as input */
412 gpio->simple_ddr &= ~(0x20000000);
414 return ((gpio->simple_ival & 0x20000000) ? 0 : 1);
421 #ifdef CONFIG_BOARD_EARLY_INIT_R
422 int board_early_init_r (void)
425 extern int usb_cpu_init(void);
427 #ifdef CONFIG_PS2MULT
428 ps2mult_early_init();
429 #endif /* CONFIG_PS2MULT */
431 #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
432 /* Low level USB init, required for proper kernel operation */
441 int silent_boot (void)
443 vu_long timer3_status;
445 /* Configure GPT3 as GPIO input */
446 *(vu_long *)MPC5XXX_GPT3_ENABLE = 0x00000004;
448 /* Read in TIMER_3 pin status */
449 timer3_status = *(vu_long *)MPC5XXX_GPT3_STATUS;
451 #ifdef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED
452 /* Force silent console mode if S1 switch
453 * is in closed position (TIMER_3 pin status is LOW). */
454 if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 0)
457 /* Force silent console mode if S1 switch
458 * is in open position (TIMER_3 pin status is HIGH). */
459 if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 1)
466 int board_early_init_f (void)
469 gd->flags |= GD_FLG_SILENT;
473 #endif /* CONFIG_FO300 */
475 #if defined(CONFIG_CHARON)
479 /* The TFP410 registers */
480 #define TFP410_REG_VEN_ID_L 0x00
481 #define TFP410_REG_VEN_ID_H 0x01
482 #define TFP410_REG_DEV_ID_L 0x02
483 #define TFP410_REG_DEV_ID_H 0x03
484 #define TFP410_REG_REV_ID 0x04
486 #define TFP410_REG_CTL_1_MODE 0x08
487 #define TFP410_REG_CTL_2_MODE 0x09
488 #define TFP410_REG_CTL_3_MODE 0x0A
490 #define TFP410_REG_CFG 0x0B
492 #define TFP410_REG_DE_DLY 0x32
493 #define TFP410_REG_DE_CTL 0x33
494 #define TFP410_REG_DE_TOP 0x34
495 #define TFP410_REG_DE_CNT_L 0x36
496 #define TFP410_REG_DE_CNT_H 0x37
497 #define TFP410_REG_DE_LIN_L 0x38
498 #define TFP410_REG_DE_LIN_H 0x39
500 #define TFP410_REG_H_RES_L 0x3A
501 #define TFP410_REG_H_RES_H 0x3B
502 #define TFP410_REG_V_RES_L 0x3C
503 #define TFP410_REG_V_RES_H 0x3D
505 static int tfp410_read_reg(int reg, uchar *buf)
507 if (i2c_read(CONFIG_SYS_TFP410_ADDR, reg, 1, buf, 1) != 0) {
508 puts ("Error reading the chip.\n");
514 static int tfp410_write_reg(int reg, uchar buf)
516 if (i2c_write(CONFIG_SYS_TFP410_ADDR, reg, 1, &buf, 1) != 0) {
517 puts ("Error writing the chip.\n");
523 typedef struct _tfp410_config {
528 static TFP410_CONFIG tfp410_configtbl[] = {
529 {TFP410_REG_CTL_1_MODE, 0x37},
530 {TFP410_REG_CTL_2_MODE, 0x20},
531 {TFP410_REG_CTL_3_MODE, 0x80},
532 {TFP410_REG_DE_DLY, 0x90},
533 {TFP410_REG_DE_CTL, 0x00},
534 {TFP410_REG_DE_TOP, 0x23},
535 {TFP410_REG_DE_CNT_H, 0x02},
536 {TFP410_REG_DE_CNT_L, 0x80},
537 {TFP410_REG_DE_LIN_H, 0x01},
538 {TFP410_REG_DE_LIN_L, 0xe0},
542 static int charon_last_stage_init(void)
544 volatile struct mpc5xxx_lpb *lpb =
545 (struct mpc5xxx_lpb *) MPC5XXX_LPB;
546 int oldbus = i2c_get_bus_num();
550 i2c_set_bus_num(CONFIG_SYS_TFP410_BUS);
553 if (tfp410_read_reg(TFP410_REG_DEV_ID_H, &buf) != 0)
557 if (tfp410_read_reg(TFP410_REG_DEV_ID_L, &buf) != 0)
561 /* OK, now init the chip */
562 while (tfp410_configtbl[i].reg != -1) {
565 ret = tfp410_write_reg(tfp410_configtbl[i].reg,
566 tfp410_configtbl[i].val);
571 printf("TFP410 initialized.\n");
572 i2c_set_bus_num(oldbus);
574 /* set deadcycle for cs3 to 0 */
575 setbits_be32(&lpb->cs_deadcycle, 0xffffcfff);
580 int last_stage_init (void)
583 * auto scan for really existing devices and re-set chip select
590 * Check for SRAM and SRAM size
593 /* save original SRAM content */
594 save = *(volatile u16 *)CONFIG_SYS_CS2_START;
597 /* write test pattern to SRAM */
598 *(volatile u16 *)CONFIG_SYS_CS2_START = 0xA5A5;
599 __asm__ volatile ("sync");
601 * Put a different pattern on the data lines: otherwise they may float
602 * long enough to read back what we wrote.
604 tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
606 puts ("!! possible error in SRAM detection\n");
608 if (*(volatile u16 *)CONFIG_SYS_CS2_START != 0xA5A5) {
609 /* no SRAM at all, disable cs */
610 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18);
611 *(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF;
612 *(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF;
614 __asm__ volatile ("sync");
615 } else if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0xA5A5) {
616 /* make sure that we access a mirrored address */
617 *(volatile u16 *)CONFIG_SYS_CS2_START = 0x1111;
618 __asm__ volatile ("sync");
619 if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0x1111) {
620 /* SRAM size = 512 kByte */
621 *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CONFIG_SYS_CS2_START,
623 __asm__ volatile ("sync");
624 puts ("SRAM: 512 kB\n");
627 puts ("!! possible error in SRAM detection\n");
629 puts ("SRAM: 1 MB\n");
631 /* restore origianl SRAM content */
633 *(volatile u16 *)CONFIG_SYS_CS2_START = save;
634 __asm__ volatile ("sync");
637 #ifndef CONFIG_TQM5200S /* The TQM5200S has no SM501 grafic controller */
639 * Check for Grafic Controller
642 /* save origianl FB content */
643 save = *(volatile u16 *)CONFIG_SYS_CS1_START;
646 /* write test pattern to FB memory */
647 *(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5;
648 __asm__ volatile ("sync");
650 * Put a different pattern on the data lines: otherwise they may float
651 * long enough to read back what we wrote.
653 tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
655 puts ("!! possible error in grafic controller detection\n");
657 if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) {
658 /* no grafic controller at all, disable cs */
659 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17);
660 *(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF;
661 *(vu_long *)MPC5XXX_CS1_STOP = 0x0000FFFF;
663 __asm__ volatile ("sync");
665 puts ("VGA: SMI501 (Voyager) with 8 MB\n");
667 /* restore origianl FB content */
669 *(volatile u16 *)CONFIG_SYS_CS1_START = save;
670 __asm__ volatile ("sync");
675 setenv("bootdelay", "0");
679 #endif /* !CONFIG_TQM5200S */
681 #if defined(CONFIG_CHARON)
682 charon_last_stage_init();
687 #ifdef CONFIG_VIDEO_SM501
690 #define DISPLAY_WIDTH 800
692 #define DISPLAY_WIDTH 640
694 #define DISPLAY_HEIGHT 480
696 #ifdef CONFIG_VIDEO_SM501_8BPP
697 #error CONFIG_VIDEO_SM501_8BPP not supported.
698 #endif /* CONFIG_VIDEO_SM501_8BPP */
700 #ifdef CONFIG_VIDEO_SM501_16BPP
701 #error CONFIG_VIDEO_SM501_16BPP not supported.
702 #endif /* CONFIG_VIDEO_SM501_16BPP */
703 #ifdef CONFIG_VIDEO_SM501_32BPP
704 static const SMI_REGS init_regs [] =
708 {0x00048, 0x00021807},
709 {0x0004C, 0x10090a01},
711 {0x00040, 0x00021807},
712 {0x00044, 0x10090a01},
714 {0x80200, 0x00010000},
716 {0x80208, 0x0A000A00},
717 {0x8020C, 0x02fa027f},
718 {0x80210, 0x004a028b},
719 {0x80214, 0x020c01df},
720 {0x80218, 0x000201e9},
721 {0x80200, 0x00013306},
722 #else /* panel + CRT */
725 {0x00048, 0x00021807},
726 {0x0004C, 0x301a0a01},
728 {0x00040, 0x00021807},
729 {0x00044, 0x091a0a01},
731 {0x80000, 0x0f013106},
732 {0x80004, 0xc428bb17},
733 {0x8000C, 0x00000000},
734 {0x80010, 0x0C800C80},
735 {0x80014, 0x03200000},
736 {0x80018, 0x01e00000},
737 {0x8001C, 0x00000000},
738 {0x80020, 0x01e00320},
739 {0x80024, 0x042a031f},
740 {0x80028, 0x0086034a},
741 {0x8002C, 0x020c01df},
742 {0x80030, 0x000201ea},
743 {0x80200, 0x00010000},
746 {0x00048, 0x00021807},
747 {0x0004C, 0x091a0a01},
749 {0x00040, 0x00021807},
750 {0x00044, 0x091a0a01},
752 {0x80000, 0x0f013106},
753 {0x80004, 0xc428bb17},
754 {0x8000C, 0x00000000},
755 {0x80010, 0x0a000a00},
756 {0x80014, 0x02800000},
757 {0x80018, 0x01e00000},
758 {0x8001C, 0x00000000},
759 {0x80020, 0x01e00280},
760 {0x80024, 0x02fa027f},
761 {0x80028, 0x004a028b},
762 {0x8002C, 0x020c01df},
763 {0x80030, 0x000201e9},
764 {0x80200, 0x00010000},
765 #endif /* #ifdef CONFIG_FO300 */
769 #endif /* CONFIG_VIDEO_SM501_32BPP */
771 #ifdef CONFIG_CONSOLE_EXTRA_INFO
773 * Return text to be printed besides the logo.
775 void video_get_info_str (int line_number, char *info)
777 if (line_number == 1) {
778 strcpy (info, " Board: TQM5200 (TQ-Components GmbH)");
779 #if defined (CONFIG_CHARON) || defined (CONFIG_FO300) || \
780 defined(CONFIG_STK52XX) || defined(CONFIG_TB5200)
781 } else if (line_number == 2) {
782 #if defined (CONFIG_CHARON)
783 strcpy (info, " on a CHARON carrier board");
785 #if defined (CONFIG_STK52XX)
786 strcpy (info, " on a STK52xx carrier board");
788 #if defined (CONFIG_TB5200)
789 strcpy (info, " on a TB5200 carrier board");
791 #if defined (CONFIG_FO300)
792 strcpy (info, " on a FO300 carrier board");
803 * Returns SM501 register base address. First thing called in the
804 * driver. Checks if SM501 is physically present.
806 unsigned int board_video_init (void)
812 * Check for Grafic Controller
815 /* save origianl FB content */
816 save = *(volatile u16 *)CONFIG_SYS_CS1_START;
819 /* write test pattern to FB memory */
820 *(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5;
821 __asm__ volatile ("sync");
823 * Put a different pattern on the data lines: otherwise they may float
824 * long enough to read back what we wrote.
826 tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
828 puts ("!! possible error in grafic controller detection\n");
830 if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) {
831 /* no grafic controller found */
835 ret = SM501_MMIO_BASE;
839 *(volatile u16 *)CONFIG_SYS_CS1_START = save;
840 __asm__ volatile ("sync");
846 * Returns SM501 framebuffer address
848 unsigned int board_video_get_fb (void)
850 return SM501_FB_BASE;
854 * Called after initializing the SM501 and before clearing the screen.
856 void board_validate_screen (unsigned int base)
861 * Return a pointer to the initialization sequence.
863 const SMI_REGS *board_get_regs (void)
868 int board_get_width (void)
870 return DISPLAY_WIDTH;
873 int board_get_height (void)
875 return DISPLAY_HEIGHT;
878 #endif /* CONFIG_VIDEO_SM501 */
880 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
881 void ft_board_setup(void *blob, bd_t *bd)
883 ft_cpu_setup(blob, bd);
884 #if defined(CONFIG_VIDEO)
885 fdt_add_edid(blob, "smi,sm501", edid_buf);
888 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
890 #if defined(CONFIG_RESET_PHY_R)
895 /* init Micrel KSZ8993 PHY */
896 miiphy_write("FEC", CONFIG_PHY_ADDR, 0x01, 0x09);
900 int board_eth_init(bd_t *bis)
902 cpu_eth_init(bis); /* Built in FEC comes first */
903 return pci_eth_init(bis);