2 * (C) Copyright 2003-2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
8 * (C) Copyright 2004-2006
9 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #include <asm/processor.h>
37 #ifdef CONFIG_VIDEO_SM501
41 #if defined(CONFIG_MPC5200_DDR)
42 #include "mt46v16m16-75.h"
44 #include "mt48lc16m16a2-75.h"
47 #ifdef CONFIG_OF_LIBFDT
48 #include <fdt_support.h>
49 #endif /* CONFIG_OF_LIBFDT */
51 DECLARE_GLOBAL_DATA_PTR;
54 void ps2mult_early_init(void);
57 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) && \
60 * EDID block has been generated using Phoenix EDID Designer 1.3.
61 * This tool creates a text file containing:
65 * 0x 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
66 * ------------------------------------------------
67 * 00 | 00 FF FF FF FF FF FF 00 04 21 00 00 00 00 00 00
68 * 10 | 01 00 01 03 00 00 00 00 00 00 00 00 00 00 00 00
69 * 20 | 00 00 00 21 00 00 01 01 01 01 01 01 01 01 01 01
70 * 30 | 01 01 01 01 01 01 64 00 00 00 00 00 00 00 00 00
71 * 40 | 00 00 00 00 00 00 00 00 00 00 00 10 00 00 00 00
72 * 50 | 00 00 00 00 00 00 00 00 00 00 00 00 00 10 00 00
73 * 60 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10
74 * 70 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 17
76 * Then this data has been manually converted to the char
79 static unsigned char edid_buf[128] = {
80 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
81 0x04, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
82 0x01, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00,
83 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
84 0x00, 0x00, 0x00, 0x21, 0x00, 0x00, 0x01, 0x01,
85 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
86 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x64, 0x00,
87 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
88 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
89 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00,
90 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
91 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00,
92 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
93 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
94 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
95 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x17,
99 #ifndef CONFIG_SYS_RAMBOOT
100 static void sdram_start (int hi_addr)
102 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
104 /* unlock mode register */
105 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
107 __asm__ volatile ("sync");
109 /* precharge all banks */
110 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
112 __asm__ volatile ("sync");
115 /* set mode register: extended mode */
116 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
117 __asm__ volatile ("sync");
119 /* set mode register: reset DLL */
120 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
121 __asm__ volatile ("sync");
124 /* precharge all banks */
125 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
127 __asm__ volatile ("sync");
130 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
132 __asm__ volatile ("sync");
134 /* set mode register */
135 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
136 __asm__ volatile ("sync");
138 /* normal operation */
139 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
140 __asm__ volatile ("sync");
145 * ATTENTION: Although partially referenced initdram does NOT make real use
146 * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
147 * is something else than 0x00000000.
150 phys_size_t initdram (int board_type)
156 #ifndef CONFIG_SYS_RAMBOOT
159 /* setup SDRAM chip selects */
160 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
161 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
162 __asm__ volatile ("sync");
164 /* setup config registers */
165 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
166 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
167 __asm__ volatile ("sync");
171 *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
172 __asm__ volatile ("sync");
175 /* find RAM size using SDRAM CS0 only */
177 test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
179 test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
187 /* memory smaller than 1MB is impossible */
188 if (dramsize < (1 << 20)) {
192 /* set SDRAM CS0 size according to the amount of RAM found */
194 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
195 __builtin_ffs(dramsize >> 20) - 1;
197 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
200 /* let SDRAM CS1 start right after CS0 */
201 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */
203 /* find RAM size using SDRAM CS1 only */
206 test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
209 test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
218 /* memory smaller than 1MB is impossible */
219 if (dramsize2 < (1 << 20)) {
223 /* set SDRAM CS1 size according to the amount of RAM found */
225 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
226 | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
228 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
231 #else /* CONFIG_SYS_RAMBOOT */
233 /* retrieve size of memory connected to SDRAM CS0 */
234 dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
235 if (dramsize >= 0x13) {
236 dramsize = (1 << (dramsize - 0x13)) << 20;
241 /* retrieve size of memory connected to SDRAM CS1 */
242 dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
243 if (dramsize2 >= 0x13) {
244 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
248 #endif /* CONFIG_SYS_RAMBOOT */
251 * On MPC5200B we need to set the special configuration delay in the
252 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
253 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
255 * "The SDelay should be written to a value of 0x00000004. It is
256 * required to account for changes caused by normal wafer processing
261 if ((SVR_MJREV(svr) >= 2) &&
262 (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
264 *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
265 __asm__ volatile ("sync");
268 #if defined(CONFIG_TQM5200_B)
269 return dramsize + dramsize2;
272 #endif /* CONFIG_TQM5200_B */
275 int checkboard (void)
277 #if defined(CONFIG_AEVFIFO)
278 puts ("Board: AEVFIFO\n");
282 #if defined(CONFIG_TQM5200S)
283 # define MODULE_NAME "TQM5200S"
285 # define MODULE_NAME "TQM5200"
288 #if defined(CONFIG_STK52XX)
289 # define CARRIER_NAME "STK52xx"
290 #elif defined(CONFIG_TB5200)
291 # define CARRIER_NAME "TB5200"
292 #elif defined(CONFIG_CAM5200)
293 # define CARRIER_NAME "CAM5200"
294 #elif defined(CONFIG_FO300)
295 # define CARRIER_NAME "FO300"
296 #elif defined(CONFIG_CHARON)
297 # define CARRIER_NAME "CHARON"
302 puts ( "Board: " MODULE_NAME " (TQ-Components GmbH)\n"
303 " on a " CARRIER_NAME " carrier board\n");
311 void flash_preinit(void)
314 * Now, when we are in RAM, enable flash write
315 * access for detection process.
316 * Note that CS_BOOT cannot be cleared when
317 * executing in flash.
319 *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
324 static struct pci_controller hose;
326 extern void pci_mpc5xxx_init(struct pci_controller *);
328 void pci_init_board(void)
330 pci_mpc5xxx_init(&hose);
334 #if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
336 #if defined (CONFIG_MINIFAP)
337 #define SM501_POWER_MODE0_GATE 0x00000040UL
338 #define SM501_POWER_MODE1_GATE 0x00000048UL
339 #define POWER_MODE_GATE_GPIO_PWM_I2C 0x00000040UL
340 #define SM501_GPIO_DATA_DIR_HIGH 0x0001000CUL
341 #define SM501_GPIO_DATA_HIGH 0x00010004UL
342 #define SM501_GPIO_51 0x00080000UL
343 #endif /* CONFIG MINIFAP */
345 void init_ide_reset (void)
347 debug ("init_ide_reset\n");
349 #if defined (CONFIG_MINIFAP)
350 /* Configure GPIO_51 of the SM501 grafic controller as ATA reset */
352 /* enable GPIO control (in both power modes) */
353 *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE0_GATE) |=
354 POWER_MODE_GATE_GPIO_PWM_I2C;
355 *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE1_GATE) |=
356 POWER_MODE_GATE_GPIO_PWM_I2C;
357 /* configure GPIO51 as output */
358 *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_HIGH) |=
361 /* Configure PSC1_4 as GPIO output for ATA reset */
362 *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
363 *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
365 /* by default the ATA reset is de-asserted */
366 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
370 void ide_set_reset (int idereset)
372 debug ("ide_reset(%d)\n", idereset);
374 #if defined (CONFIG_MINIFAP)
376 *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
379 *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
384 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
386 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
394 * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3
395 * is left open, no keypress is detected.
397 int post_hotkeys_pressed(void)
399 #ifdef CONFIG_STK52XX
400 struct mpc5xxx_gpio *gpio;
402 gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO;
405 * Configure PSC6_0 through PSC6_3 as GPIO.
407 gpio->port_config &= ~(0x00700000);
409 /* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */
410 gpio->simple_gpioe |= 0x20000000;
412 /* Configure GPIO_IRDA_1 as input */
413 gpio->simple_ddr &= ~(0x20000000);
415 return ((gpio->simple_ival & 0x20000000) ? 0 : 1);
422 #ifdef CONFIG_BOARD_EARLY_INIT_R
423 int board_early_init_r (void)
426 extern int usb_cpu_init(void);
428 #ifdef CONFIG_PS2MULT
429 ps2mult_early_init();
430 #endif /* CONFIG_PS2MULT */
432 #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
433 /* Low level USB init, required for proper kernel operation */
442 int silent_boot (void)
444 vu_long timer3_status;
446 /* Configure GPT3 as GPIO input */
447 *(vu_long *)MPC5XXX_GPT3_ENABLE = 0x00000004;
449 /* Read in TIMER_3 pin status */
450 timer3_status = *(vu_long *)MPC5XXX_GPT3_STATUS;
452 #ifdef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED
453 /* Force silent console mode if S1 switch
454 * is in closed position (TIMER_3 pin status is LOW). */
455 if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 0)
458 /* Force silent console mode if S1 switch
459 * is in open position (TIMER_3 pin status is HIGH). */
460 if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 1)
467 int board_early_init_f (void)
470 gd->flags |= GD_FLG_SILENT;
474 #endif /* CONFIG_FO300 */
476 #if defined(CONFIG_CHARON)
480 /* The TFP410 registers */
481 #define TFP410_REG_VEN_ID_L 0x00
482 #define TFP410_REG_VEN_ID_H 0x01
483 #define TFP410_REG_DEV_ID_L 0x02
484 #define TFP410_REG_DEV_ID_H 0x03
485 #define TFP410_REG_REV_ID 0x04
487 #define TFP410_REG_CTL_1_MODE 0x08
488 #define TFP410_REG_CTL_2_MODE 0x09
489 #define TFP410_REG_CTL_3_MODE 0x0A
491 #define TFP410_REG_CFG 0x0B
493 #define TFP410_REG_DE_DLY 0x32
494 #define TFP410_REG_DE_CTL 0x33
495 #define TFP410_REG_DE_TOP 0x34
496 #define TFP410_REG_DE_CNT_L 0x36
497 #define TFP410_REG_DE_CNT_H 0x37
498 #define TFP410_REG_DE_LIN_L 0x38
499 #define TFP410_REG_DE_LIN_H 0x39
501 #define TFP410_REG_H_RES_L 0x3A
502 #define TFP410_REG_H_RES_H 0x3B
503 #define TFP410_REG_V_RES_L 0x3C
504 #define TFP410_REG_V_RES_H 0x3D
506 static int tfp410_read_reg(int reg, uchar *buf)
508 if (i2c_read(CONFIG_SYS_TFP410_ADDR, reg, 1, buf, 1) != 0) {
509 puts ("Error reading the chip.\n");
515 static int tfp410_write_reg(int reg, uchar buf)
517 if (i2c_write(CONFIG_SYS_TFP410_ADDR, reg, 1, &buf, 1) != 0) {
518 puts ("Error writing the chip.\n");
524 typedef struct _tfp410_config {
529 static TFP410_CONFIG tfp410_configtbl[] = {
530 {TFP410_REG_CTL_1_MODE, 0x37},
531 {TFP410_REG_CTL_2_MODE, 0x20},
532 {TFP410_REG_CTL_3_MODE, 0x80},
533 {TFP410_REG_DE_DLY, 0x90},
534 {TFP410_REG_DE_CTL, 0x00},
535 {TFP410_REG_DE_TOP, 0x23},
536 {TFP410_REG_DE_CNT_H, 0x02},
537 {TFP410_REG_DE_CNT_L, 0x80},
538 {TFP410_REG_DE_LIN_H, 0x01},
539 {TFP410_REG_DE_LIN_L, 0xe0},
543 static int charon_last_stage_init(void)
545 volatile struct mpc5xxx_lpb *lpb =
546 (struct mpc5xxx_lpb *) MPC5XXX_LPB;
547 int oldbus = i2c_get_bus_num();
551 i2c_set_bus_num(CONFIG_SYS_TFP410_BUS);
554 if (tfp410_read_reg(TFP410_REG_DEV_ID_H, &buf) != 0)
558 if (tfp410_read_reg(TFP410_REG_DEV_ID_L, &buf) != 0)
562 /* OK, now init the chip */
563 while (tfp410_configtbl[i].reg != -1) {
566 ret = tfp410_write_reg(tfp410_configtbl[i].reg,
567 tfp410_configtbl[i].val);
572 printf("TFP410 initialized.\n");
573 i2c_set_bus_num(oldbus);
575 /* set deadcycle for cs3 to 0 */
576 setbits_be32(&lpb->cs_deadcycle, 0xffffcfff);
581 int last_stage_init (void)
584 * auto scan for really existing devices and re-set chip select
591 * Check for SRAM and SRAM size
594 /* save original SRAM content */
595 save = *(volatile u16 *)CONFIG_SYS_CS2_START;
598 /* write test pattern to SRAM */
599 *(volatile u16 *)CONFIG_SYS_CS2_START = 0xA5A5;
600 __asm__ volatile ("sync");
602 * Put a different pattern on the data lines: otherwise they may float
603 * long enough to read back what we wrote.
605 tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
607 puts ("!! possible error in SRAM detection\n");
609 if (*(volatile u16 *)CONFIG_SYS_CS2_START != 0xA5A5) {
610 /* no SRAM at all, disable cs */
611 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18);
612 *(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF;
613 *(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF;
615 __asm__ volatile ("sync");
616 } else if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0xA5A5) {
617 /* make sure that we access a mirrored address */
618 *(volatile u16 *)CONFIG_SYS_CS2_START = 0x1111;
619 __asm__ volatile ("sync");
620 if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0x1111) {
621 /* SRAM size = 512 kByte */
622 *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CONFIG_SYS_CS2_START,
624 __asm__ volatile ("sync");
625 puts ("SRAM: 512 kB\n");
628 puts ("!! possible error in SRAM detection\n");
630 puts ("SRAM: 1 MB\n");
632 /* restore origianl SRAM content */
634 *(volatile u16 *)CONFIG_SYS_CS2_START = save;
635 __asm__ volatile ("sync");
638 #ifndef CONFIG_TQM5200S /* The TQM5200S has no SM501 grafic controller */
640 * Check for Grafic Controller
643 /* save origianl FB content */
644 save = *(volatile u16 *)CONFIG_SYS_CS1_START;
647 /* write test pattern to FB memory */
648 *(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5;
649 __asm__ volatile ("sync");
651 * Put a different pattern on the data lines: otherwise they may float
652 * long enough to read back what we wrote.
654 tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
656 puts ("!! possible error in grafic controller detection\n");
658 if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) {
659 /* no grafic controller at all, disable cs */
660 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17);
661 *(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF;
662 *(vu_long *)MPC5XXX_CS1_STOP = 0x0000FFFF;
664 __asm__ volatile ("sync");
666 puts ("VGA: SMI501 (Voyager) with 8 MB\n");
668 /* restore origianl FB content */
670 *(volatile u16 *)CONFIG_SYS_CS1_START = save;
671 __asm__ volatile ("sync");
676 setenv("bootdelay", "0");
680 #endif /* !CONFIG_TQM5200S */
682 #if defined(CONFIG_CHARON)
683 charon_last_stage_init();
688 #ifdef CONFIG_VIDEO_SM501
691 #define DISPLAY_WIDTH 800
693 #define DISPLAY_WIDTH 640
695 #define DISPLAY_HEIGHT 480
697 #ifdef CONFIG_VIDEO_SM501_8BPP
698 #error CONFIG_VIDEO_SM501_8BPP not supported.
699 #endif /* CONFIG_VIDEO_SM501_8BPP */
701 #ifdef CONFIG_VIDEO_SM501_16BPP
702 #error CONFIG_VIDEO_SM501_16BPP not supported.
703 #endif /* CONFIG_VIDEO_SM501_16BPP */
704 #ifdef CONFIG_VIDEO_SM501_32BPP
705 static const SMI_REGS init_regs [] =
709 {0x00048, 0x00021807},
710 {0x0004C, 0x10090a01},
712 {0x00040, 0x00021807},
713 {0x00044, 0x10090a01},
715 {0x80200, 0x00010000},
717 {0x80208, 0x0A000A00},
718 {0x8020C, 0x02fa027f},
719 {0x80210, 0x004a028b},
720 {0x80214, 0x020c01df},
721 {0x80218, 0x000201e9},
722 {0x80200, 0x00013306},
723 #else /* panel + CRT */
726 {0x00048, 0x00021807},
727 {0x0004C, 0x301a0a01},
729 {0x00040, 0x00021807},
730 {0x00044, 0x091a0a01},
732 {0x80000, 0x0f013106},
733 {0x80004, 0xc428bb17},
734 {0x8000C, 0x00000000},
735 {0x80010, 0x0C800C80},
736 {0x80014, 0x03200000},
737 {0x80018, 0x01e00000},
738 {0x8001C, 0x00000000},
739 {0x80020, 0x01e00320},
740 {0x80024, 0x042a031f},
741 {0x80028, 0x0086034a},
742 {0x8002C, 0x020c01df},
743 {0x80030, 0x000201ea},
744 {0x80200, 0x00010000},
747 {0x00048, 0x00021807},
748 {0x0004C, 0x091a0a01},
750 {0x00040, 0x00021807},
751 {0x00044, 0x091a0a01},
753 {0x80000, 0x0f013106},
754 {0x80004, 0xc428bb17},
755 {0x8000C, 0x00000000},
756 {0x80010, 0x0a000a00},
757 {0x80014, 0x02800000},
758 {0x80018, 0x01e00000},
759 {0x8001C, 0x00000000},
760 {0x80020, 0x01e00280},
761 {0x80024, 0x02fa027f},
762 {0x80028, 0x004a028b},
763 {0x8002C, 0x020c01df},
764 {0x80030, 0x000201e9},
765 {0x80200, 0x00010000},
766 #endif /* #ifdef CONFIG_FO300 */
770 #endif /* CONFIG_VIDEO_SM501_32BPP */
772 #ifdef CONFIG_CONSOLE_EXTRA_INFO
774 * Return text to be printed besides the logo.
776 void video_get_info_str (int line_number, char *info)
778 if (line_number == 1) {
779 strcpy (info, " Board: TQM5200 (TQ-Components GmbH)");
780 #if defined (CONFIG_CHARON) || defined (CONFIG_FO300) || \
781 defined(CONFIG_STK52XX) || defined(CONFIG_TB5200)
782 } else if (line_number == 2) {
783 #if defined (CONFIG_CHARON)
784 strcpy (info, " on a CHARON carrier board");
786 #if defined (CONFIG_STK52XX)
787 strcpy (info, " on a STK52xx carrier board");
789 #if defined (CONFIG_TB5200)
790 strcpy (info, " on a TB5200 carrier board");
792 #if defined (CONFIG_FO300)
793 strcpy (info, " on a FO300 carrier board");
804 * Returns SM501 register base address. First thing called in the
805 * driver. Checks if SM501 is physically present.
807 unsigned int board_video_init (void)
813 * Check for Grafic Controller
816 /* save origianl FB content */
817 save = *(volatile u16 *)CONFIG_SYS_CS1_START;
820 /* write test pattern to FB memory */
821 *(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5;
822 __asm__ volatile ("sync");
824 * Put a different pattern on the data lines: otherwise they may float
825 * long enough to read back what we wrote.
827 tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
829 puts ("!! possible error in grafic controller detection\n");
831 if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) {
832 /* no grafic controller found */
836 ret = SM501_MMIO_BASE;
840 *(volatile u16 *)CONFIG_SYS_CS1_START = save;
841 __asm__ volatile ("sync");
847 * Returns SM501 framebuffer address
849 unsigned int board_video_get_fb (void)
851 return SM501_FB_BASE;
855 * Called after initializing the SM501 and before clearing the screen.
857 void board_validate_screen (unsigned int base)
862 * Return a pointer to the initialization sequence.
864 const SMI_REGS *board_get_regs (void)
869 int board_get_width (void)
871 return DISPLAY_WIDTH;
874 int board_get_height (void)
876 return DISPLAY_HEIGHT;
879 #endif /* CONFIG_VIDEO_SM501 */
881 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
882 void ft_board_setup(void *blob, bd_t *bd)
884 ft_cpu_setup(blob, bd);
885 #if defined(CONFIG_VIDEO)
886 fdt_add_edid(blob, "smi,sm501", edid_buf);
889 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
891 #if defined(CONFIG_RESET_PHY_R)
896 /* init Micrel KSZ8993 PHY */
897 miiphy_write("FEC", CONFIG_PHY_ADDR, 0x01, 0x09);
901 int board_eth_init(bd_t *bis)
903 cpu_eth_init(bis); /* Built in FEC comes first */
904 return pci_eth_init(bis);