1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2020 Toradex
5 * Generated code from MX8M_DDR_tool
6 * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga
8 * DDR calibration created with mscale_ddr_tool_v210_setup.exe using
9 * MX8M_Mini_LPDDR4_RPA_v14 Verdin iMX8MM V1.0.xlsx as of 1. Nov. 2019.
12 #include <linux/kernel.h>
13 #include <asm/arch/ddr.h>
15 struct dram_cfg_param ddr_ddrc_cfg[] = {
16 /** Initialize DDRC registers **/
19 {0x3d400000, 0xa1080020},
21 {0x3d400024, 0x3a980},
22 {0x3d400064, 0x5b00d2},
23 {0x3d4000d0, 0xc00305ba},
24 {0x3d4000d4, 0x940000},
25 {0x3d4000dc, 0xd4002d},
26 {0x3d4000e0, 0x310000},
27 {0x3d4000e8, 0x66004d},
28 {0x3d4000ec, 0x16004d},
29 {0x3d400100, 0x191e1920},
30 {0x3d400104, 0x60630},
31 {0x3d40010c, 0xb0b000},
32 {0x3d400110, 0xe04080e},
33 {0x3d400114, 0x2040c0c},
34 {0x3d400118, 0x1010007},
36 {0x3d400130, 0x20600},
37 {0x3d400134, 0xc100002},
39 {0x3d400144, 0x96004b},
40 {0x3d400180, 0x2ee0017},
41 {0x3d400184, 0x2605b8e},
43 {0x3d400190, 0x497820a},
44 {0x3d400194, 0x80303},
46 {0x3d4001a0, 0xe0400018},
47 {0x3d4001a4, 0xdf00e4},
48 {0x3d4001a8, 0x80000000},
53 {0x3d400108, 0x70e1617},
57 {0x3d400204, 0x80808},
58 {0x3d400214, 0x7070707},
59 {0x3d400218, 0x7070707},
60 {0x3d400250, 0x29001701},
62 {0x3d40025c, 0x4000030},
63 {0x3d400264, 0x900093e7},
64 {0x3d40026c, 0x2005574},
67 {0x3d400494, 0x2100e07},
68 {0x3d400498, 0x620096},
69 {0x3d40049c, 0x1100e07},
70 {0x3d4004a0, 0xc8012c},
73 {0x3d402050, 0x20d040},
74 {0x3d402064, 0xc001c},
75 {0x3d4020dc, 0x840000},
76 {0x3d4020e0, 0x310000},
77 {0x3d4020e8, 0x66004d},
78 {0x3d4020ec, 0x16004d},
79 {0x3d402100, 0xa040305},
80 {0x3d402104, 0x30407},
81 {0x3d402108, 0x203060b},
82 {0x3d40210c, 0x505000},
83 {0x3d402110, 0x2040202},
84 {0x3d402114, 0x2030202},
85 {0x3d402118, 0x1010004},
87 {0x3d402130, 0x20300},
88 {0x3d402134, 0xa100002},
90 {0x3d402144, 0x14000a},
91 {0x3d402180, 0x640004},
92 {0x3d402190, 0x3818200},
93 {0x3d402194, 0x80303},
98 {0x3d403050, 0x20d040},
99 {0x3d403064, 0x30007},
100 {0x3d4030dc, 0x840000},
101 {0x3d4030e0, 0x310000},
102 {0x3d4030e8, 0x66004d},
103 {0x3d4030ec, 0x16004d},
104 {0x3d403100, 0xa010102},
105 {0x3d403104, 0x30404},
106 {0x3d403108, 0x203060b},
107 {0x3d40310c, 0x505000},
108 {0x3d403110, 0x2040202},
109 {0x3d403114, 0x2030202},
110 {0x3d403118, 0x1010004},
112 {0x3d403130, 0x20300},
113 {0x3d403134, 0xa100002},
115 {0x3d403144, 0x50003},
116 {0x3d403180, 0x190004},
117 {0x3d403190, 0x3818200},
118 {0x3d403194, 0x80303},
124 /* PHY Initialize Configuration */
125 struct dram_cfg_param ddr_ddrphy_cfg[] = {
328 /* ddr phy trained csr */
329 struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
1051 /* P0 message block paremeter for training firmware */
1052 struct dram_cfg_param ddr_fsp0_cfg[] = {
1090 /* P1 message block paremeter for training firmware */
1091 struct dram_cfg_param ddr_fsp1_cfg[] = {
1130 /* P2 message block paremeter for training firmware */
1131 struct dram_cfg_param ddr_fsp2_cfg[] = {
1170 /* P0 2D message block paremeter for training firmware */
1171 struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
1210 /* DRAM PHY init engine image */
1211 struct dram_cfg_param ddr_phy_pie[] = {
1806 struct dram_fsp_msg ddr_dram_fsp_msg[] = {
1810 .fw_type = FW_1D_IMAGE,
1811 .fsp_cfg = ddr_fsp0_cfg,
1812 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
1817 .fw_type = FW_1D_IMAGE,
1818 .fsp_cfg = ddr_fsp1_cfg,
1819 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
1824 .fw_type = FW_1D_IMAGE,
1825 .fsp_cfg = ddr_fsp2_cfg,
1826 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
1831 .fw_type = FW_2D_IMAGE,
1832 .fsp_cfg = ddr_fsp0_2d_cfg,
1833 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
1837 /* ddr timing config params */
1838 struct dram_timing_info dram_timing = {
1839 .ddrc_cfg = ddr_ddrc_cfg,
1840 .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
1841 .ddrphy_cfg = ddr_ddrphy_cfg,
1842 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
1843 .fsp_msg = ddr_dram_fsp_msg,
1844 .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
1845 .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
1846 .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
1847 .ddrphy_pie = ddr_phy_pie,
1848 .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
1849 .fsp_table = { 3000, 400, 100, },