1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2015-2019 Toradex, Inc.
6 * Copyright 2013 Freescale Semiconductor, Inc.
11 #include <asm/arch/clock.h>
12 #include <asm/arch/crm_regs.h>
13 #include <asm/arch/ddrmc-vf610.h>
14 #include <asm/arch/imx-regs.h>
15 #include <asm/arch/iomux-vf610.h>
18 #include <fdt_support.h>
19 #include <fsl_esdhc.h>
20 #include <fsl_dcu_fb.h>
23 #include <jffs2/load_kernel.h>
30 #include "../common/tdx-common.h"
32 DECLARE_GLOBAL_DATA_PTR;
34 #define USB_PEN_GPIO 83
35 #define USB_CDET_GPIO 102
36 #define PTC0_GPIO_45 45
38 static struct ddrmc_cr_setting colibri_vf_cr_settings[] = {
40 { DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), 117 },
41 { DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 },
42 { DDRMC_CR120_AXI0_PRI1_RPRI(2) |
43 DDRMC_CR120_AXI0_PRI0_RPRI(2), 120 },
44 { DDRMC_CR121_AXI0_PRI3_RPRI(2) |
45 DDRMC_CR121_AXI0_PRI2_RPRI(2), 121 },
46 { DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
47 DDRMC_CR122_AXI0_PRIRLX(100), 122 },
48 { DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) |
49 DDRMC_CR123_AXI1_PRI2_RPRI(1), 123 },
50 { DDRMC_CR124_AXI1_PRIRLX(100), 124 },
51 { DDRMC_CR126_PHY_RDLAT(8), 126 },
52 { DDRMC_CR132_WRLAT_ADJ(5) |
53 DDRMC_CR132_RDLAT_ADJ(6), 132 },
54 { DDRMC_CR137_PHYCTL_DL(2), 137 },
55 { DDRMC_CR138_PHY_WRLV_MXDL(256) |
56 DDRMC_CR138_PHYDRAM_CK_EN(1), 138 },
57 { DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
58 DDRMC_CR139_PHY_WRLV_DLL(3) |
59 DDRMC_CR139_PHY_WRLV_EN(3), 139 },
60 { DDRMC_CR140_PHY_WRLV_WW(64), 140 },
61 { DDRMC_CR143_RDLV_GAT_MXDL(1536) |
62 DDRMC_CR143_RDLV_MXDL(128), 143 },
63 { DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) |
64 DDRMC_CR144_PHY_RDLV_DLL(3) |
65 DDRMC_CR144_PHY_RDLV_EN(3), 144 },
66 { DDRMC_CR145_PHY_RDLV_RR(64), 145 },
67 { DDRMC_CR146_PHY_RDLVL_RESP(64), 146 },
68 { DDRMC_CR147_RDLV_RESP_MASK(983040), 147 },
69 { DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), 148 },
70 { DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) |
71 DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), 151 },
73 { DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
74 DDRMC_CR154_PAD_ZQ_MODE(1) |
75 DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |
76 DDRMC_CR154_PAD_ZQ_HW_FOR(1), 154 },
77 { DDRMC_CR155_PAD_ODT_BYTE1(2) | DDRMC_CR155_PAD_ODT_BYTE0(2), 155 },
78 { DDRMC_CR158_TWR(6), 158 },
79 { DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) |
80 DDRMC_CR161_TODTH_WR(2), 161 },
87 static const struct ddr3_jedec_timings timings = {
90 .cke_inactive = 200000,
96 .tbst_int_interval = 0,
138 ddrmc_ctrl_init_ddr3(&timings, colibri_vf_cr_settings, NULL, 1, 2);
139 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
144 #ifdef CONFIG_VYBRID_GPIO
145 static void setup_iomux_gpio(void)
147 static const iomux_v3_cfg_t gpio_pads[] = {
148 VF610_PAD_PTA17__GPIO_7,
149 VF610_PAD_PTA20__GPIO_10,
150 VF610_PAD_PTA21__GPIO_11,
151 VF610_PAD_PTA30__GPIO_20,
152 VF610_PAD_PTA31__GPIO_21,
153 VF610_PAD_PTB0__GPIO_22,
154 VF610_PAD_PTB1__GPIO_23,
155 VF610_PAD_PTB6__GPIO_28,
156 VF610_PAD_PTB7__GPIO_29,
157 VF610_PAD_PTB8__GPIO_30,
158 VF610_PAD_PTB9__GPIO_31,
159 VF610_PAD_PTB12__GPIO_34,
160 VF610_PAD_PTB13__GPIO_35,
161 VF610_PAD_PTB16__GPIO_38,
162 VF610_PAD_PTB17__GPIO_39,
163 VF610_PAD_PTB18__GPIO_40,
164 VF610_PAD_PTB21__GPIO_43,
165 VF610_PAD_PTB22__GPIO_44,
166 VF610_PAD_PTC0__GPIO_45,
167 VF610_PAD_PTC1__GPIO_46,
168 VF610_PAD_PTC2__GPIO_47,
169 VF610_PAD_PTC3__GPIO_48,
170 VF610_PAD_PTC4__GPIO_49,
171 VF610_PAD_PTC5__GPIO_50,
172 VF610_PAD_PTC6__GPIO_51,
173 VF610_PAD_PTC7__GPIO_52,
174 VF610_PAD_PTC8__GPIO_53,
175 VF610_PAD_PTD31__GPIO_63,
176 VF610_PAD_PTD30__GPIO_64,
177 VF610_PAD_PTD29__GPIO_65,
178 VF610_PAD_PTD28__GPIO_66,
179 VF610_PAD_PTD27__GPIO_67,
180 VF610_PAD_PTD26__GPIO_68,
181 VF610_PAD_PTD25__GPIO_69,
182 VF610_PAD_PTD24__GPIO_70,
183 VF610_PAD_PTD9__GPIO_88,
184 VF610_PAD_PTD10__GPIO_89,
185 VF610_PAD_PTD11__GPIO_90,
186 VF610_PAD_PTD12__GPIO_91,
187 VF610_PAD_PTD13__GPIO_92,
188 VF610_PAD_PTB23__GPIO_93,
189 VF610_PAD_PTB26__GPIO_96,
190 VF610_PAD_PTB28__GPIO_98,
191 VF610_PAD_PTC30__GPIO_103,
192 VF610_PAD_PTA7__GPIO_134,
195 imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
199 #ifdef CONFIG_VIDEO_FSL_DCU_FB
200 static void setup_iomux_fsl_dcu(void)
202 static const iomux_v3_cfg_t dcu0_pads[] = {
203 VF610_PAD_PTE0__DCU0_HSYNC,
204 VF610_PAD_PTE1__DCU0_VSYNC,
205 VF610_PAD_PTE2__DCU0_PCLK,
206 VF610_PAD_PTE4__DCU0_DE,
207 VF610_PAD_PTE5__DCU0_R0,
208 VF610_PAD_PTE6__DCU0_R1,
209 VF610_PAD_PTE7__DCU0_R2,
210 VF610_PAD_PTE8__DCU0_R3,
211 VF610_PAD_PTE9__DCU0_R4,
212 VF610_PAD_PTE10__DCU0_R5,
213 VF610_PAD_PTE11__DCU0_R6,
214 VF610_PAD_PTE12__DCU0_R7,
215 VF610_PAD_PTE13__DCU0_G0,
216 VF610_PAD_PTE14__DCU0_G1,
217 VF610_PAD_PTE15__DCU0_G2,
218 VF610_PAD_PTE16__DCU0_G3,
219 VF610_PAD_PTE17__DCU0_G4,
220 VF610_PAD_PTE18__DCU0_G5,
221 VF610_PAD_PTE19__DCU0_G6,
222 VF610_PAD_PTE20__DCU0_G7,
223 VF610_PAD_PTE21__DCU0_B0,
224 VF610_PAD_PTE22__DCU0_B1,
225 VF610_PAD_PTE23__DCU0_B2,
226 VF610_PAD_PTE24__DCU0_B3,
227 VF610_PAD_PTE25__DCU0_B4,
228 VF610_PAD_PTE26__DCU0_B5,
229 VF610_PAD_PTE27__DCU0_B6,
230 VF610_PAD_PTE28__DCU0_B7,
233 imx_iomux_v3_setup_multiple_pads(dcu0_pads, ARRAY_SIZE(dcu0_pads));
236 static void setup_tcon(void)
238 setbits_le32(TCON0_BASE_ADDR, (1 << 29));
242 #ifdef CONFIG_FSL_ESDHC
243 struct fsl_esdhc_cfg esdhc_cfg[1] = {
247 int board_mmc_getcd(struct mmc *mmc)
249 /* eSDHC1 is always present */
253 int board_mmc_init(bd_t *bis)
255 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
257 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
261 static inline int is_colibri_vf61(void)
263 struct mscm *mscm = (struct mscm *)MSCM_BASE_ADDR;
266 * Detect board type by Level 2 Cache: VF50 don't have any
269 return !!mscm->cpxcfg1;
272 static void clock_init(void)
274 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
275 struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
276 u32 pfd_clk_sel, ddr_clk_sel;
278 clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,
279 CCM_CCGR0_UART0_CTRL_MASK);
280 #ifdef CONFIG_FSL_DSPI
281 setbits_le32(&ccm->ccgr0, CCM_CCGR0_DSPI1_CTRL_MASK);
283 clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,
284 CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK);
285 clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
286 CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK |
287 CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK |
288 CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK);
289 clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
290 CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK);
291 clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
292 CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
293 CCM_CCGR4_GPC_CTRL_MASK | CCM_CCGR4_I2C0_CTRL_MASK);
294 clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
295 CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK);
296 clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
297 CCM_CCGR7_SDHC1_CTRL_MASK);
298 clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
299 CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK);
300 clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK,
301 CCM_CCGR10_NFC_CTRL_MASK);
303 #ifdef CONFIG_USB_EHCI_VF
304 setbits_le32(&ccm->ccgr1, CCM_CCGR1_USBC0_CTRL_MASK);
305 setbits_le32(&ccm->ccgr7, CCM_CCGR7_USBC1_CTRL_MASK);
307 clrsetbits_le32(&anadig->pll3_ctrl, ANADIG_PLL3_CTRL_BYPASS |
308 ANADIG_PLL3_CTRL_POWERDOWN |
309 ANADIG_PLL3_CTRL_DIV_SELECT,
310 ANADIG_PLL3_CTRL_ENABLE);
311 clrsetbits_le32(&anadig->pll7_ctrl, ANADIG_PLL7_CTRL_BYPASS |
312 ANADIG_PLL7_CTRL_POWERDOWN |
313 ANADIG_PLL7_CTRL_DIV_SELECT,
314 ANADIG_PLL7_CTRL_ENABLE);
317 clrsetbits_le32(&anadig->pll5_ctrl, ANADIG_PLL5_CTRL_BYPASS |
318 ANADIG_PLL5_CTRL_POWERDOWN, ANADIG_PLL5_CTRL_ENABLE |
319 ANADIG_PLL5_CTRL_DIV_SELECT);
321 if (is_colibri_vf61()) {
322 clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL5_CTRL_BYPASS |
323 ANADIG_PLL2_CTRL_POWERDOWN,
324 ANADIG_PLL2_CTRL_ENABLE |
325 ANADIG_PLL2_CTRL_DIV_SELECT);
328 clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN,
329 ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT);
331 clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK,
332 CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5));
334 /* See "Typical PLL Configuration" */
335 if (is_colibri_vf61()) {
336 pfd_clk_sel = CCM_CCSR_PLL1_PFD_CLK_SEL(1);
337 ddr_clk_sel = CCM_CCSR_DDRC_CLK_SEL(0);
339 pfd_clk_sel = CCM_CCSR_PLL1_PFD_CLK_SEL(3);
340 ddr_clk_sel = CCM_CCSR_DDRC_CLK_SEL(1);
343 clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK, pfd_clk_sel |
344 CCM_CCSR_PLL2_PFD4_EN | CCM_CCSR_PLL2_PFD3_EN |
345 CCM_CCSR_PLL2_PFD2_EN | CCM_CCSR_PLL2_PFD1_EN |
346 CCM_CCSR_PLL1_PFD4_EN | CCM_CCSR_PLL1_PFD3_EN |
347 CCM_CCSR_PLL1_PFD2_EN | CCM_CCSR_PLL1_PFD1_EN |
348 ddr_clk_sel | CCM_CCSR_FAST_CLK_SEL(1) |
349 CCM_CCSR_SYS_CLK_SEL(4));
351 clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK,
352 CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |
353 CCM_CACRR_ARM_CLK_DIV(0));
354 clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,
355 CCM_CSCMR1_ESDHC1_CLK_SEL(3) |
356 CCM_CSCMR1_NFC_CLK_SEL(0));
357 clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK,
358 CCM_CSCDR1_RMII_CLK_EN);
359 clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,
360 CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) |
362 clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK,
363 CCM_CSCDR3_NFC_PRE_DIV(3));
364 clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
365 CCM_CSCMR2_RMII_CLK_SEL(2));
367 #ifdef CONFIG_VIDEO_FSL_DCU_FB
368 setbits_le32(&ccm->ccgr1, CCM_CCGR1_TCON0_CTRL_MASK);
369 setbits_le32(&ccm->ccgr3, CCM_CCGR3_DCU0_CTRL_MASK);
373 static void mscm_init(void)
375 struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR;
378 for (i = 0; i < MSCM_IRSPRC_NUM; i++)
379 writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]);
382 int board_phy_config(struct phy_device *phydev)
384 if (phydev->drv->config)
385 phydev->drv->config(phydev);
390 int board_early_init_f(void)
395 #ifdef CONFIG_VYBRID_GPIO
399 #ifdef CONFIG_VIDEO_FSL_DCU_FB
401 setup_iomux_fsl_dcu();
407 #ifdef CONFIG_BOARD_LATE_INIT
408 int board_late_init(void)
410 struct src *src = (struct src *)SRC_BASE_ADDR;
412 if (((src->sbmr2 & SRC_SBMR2_BMOD_MASK) >> SRC_SBMR2_BMOD_SHIFT)
413 == SRC_SBMR2_BMOD_SERIAL) {
414 printf("Serial Downloader recovery mode, disable autoboot\n");
415 env_set("bootdelay", "-1");
420 #endif /* CONFIG_BOARD_LATE_INIT */
424 struct scsc_reg *scsc = (struct scsc_reg *)SCSC_BASE_ADDR;
426 /* address of boot parameters */
427 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
430 * Enable external 32K Oscillator
432 * The internal clock experiences significant drift
433 * so we must use the external oscillator in order
434 * to maintain correct time in the hwclock
437 setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN);
439 #ifdef CONFIG_USB_EHCI_VF
440 gpio_request(USB_CDET_GPIO, "usb-cdet-gpio");
448 if (is_colibri_vf61())
449 puts("Board: Colibri VF61\n");
451 puts("Board: Colibri VF50\n");
456 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
457 int ft_board_setup(void *blob, bd_t *bd)
460 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
461 static const struct node_info nodes[] = {
462 { "fsl,vf610-nfc", MTD_DEV_TYPE_NAND, }, /* NAND flash */
465 /* Update partition nodes using info from mtdparts env var */
466 puts(" Updating MTD partitions...\n");
467 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
469 #ifdef CONFIG_VIDEO_FSL_DCU_FB
470 ret = fsl_dcu_fixedfb_setup(blob);
475 return ft_common_board_setup(blob, bd);
479 #ifdef CONFIG_USB_EHCI_VF
480 int board_ehci_hcd_init(int port)
484 /* USBC does not have PEN, also configured as USB client only */
487 gpio_request(USB_PEN_GPIO, "usb-pen-gpio");
488 gpio_direction_output(USB_PEN_GPIO, 0);
494 int board_usb_phy_mode(int port)
499 * Port 0 is used only in client mode on Colibri Vybrid modules
500 * Check for state of USB client gpio pin and accordingly return
501 * USB_INIT_DEVICE or USB_INIT_HOST.
503 if (gpio_get_value(USB_CDET_GPIO))
504 return USB_INIT_DEVICE;
506 return USB_INIT_HOST;
508 /* Port 1 is used only in host mode on Colibri Vybrid modules */
509 return USB_INIT_HOST;
512 * There are only two USB controllers on Vybrid. Ideally we will
513 * not reach here. However return USB_INIT_HOST if we do.
515 return USB_INIT_HOST;
521 * Backlight off before OS handover
523 void board_preboot_os(void)
525 gpio_request(PTC0_GPIO_45, "BL_ON");
526 gpio_direction_output(PTC0_GPIO_45, 0);