1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2015 Freescale Semiconductor, Inc.
6 * Refer doc/README.imximage for more details about how-to configure
7 * and create imximage boot image
9 * The syntax is taken as close as possible with the kwbimage
33 * Device Configuration Data (DCD)
35 * Each entry must have the format:
36 * Addr-type Address Value
39 * Addr-type register length (1,2 or 4 bytes)
40 * Address absolute address of the register
41 * value value to be stored in the register
45 DATA 4 0x30340004 0x4F400005
48 /* assuming MEMC_FREQ_RATIO = 2 */
50 DATA 4 0x30391000 0x00000002
52 DATA 4 0x307a0000 0x01040001
54 DATA 4 0x307a01a0 0x80400003
56 DATA 4 0x307a01a4 0x00100020
58 DATA 4 0x307a01a8 0x80100004
60 DATA 4 0x307a0064 0x00400046
62 DATA 4 0x307a0490 0x00000001
64 DATA 4 0x307a00d0 0x00020083
66 DATA 4 0x307a00d4 0x00690000
67 /* DDRC_INIT3 MR0/MR1 */
68 DATA 4 0x307a00dc 0x09300004
69 /* DDRC_INIT4 MR2/MR3 */
70 DATA 4 0x307a00e0 0x04480000
72 DATA 4 0x307a00e4 0x00100004
74 DATA 4 0x307a00f4 0x0000033f
76 DATA 4 0x307a0100 0x0910090a
78 DATA 4 0x307a0104 0x000d020e
80 DATA 4 0x307a0108 0x03040307
82 DATA 4 0x307a010c 0x00002006
84 DATA 4 0x307a0110 0x04020204
86 DATA 4 0x307a0114 0x03030202
88 DATA 4 0x307a0120 0x00000803
90 DATA 4 0x307a0180 0x00800020
92 DATA 4 0x307a0184 0x02001000
94 DATA 4 0x307a0190 0x02098204
96 DATA 4 0x307a0194 0x00030303
98 DATA 4 0x307a0200 0x0000001f
100 DATA 4 0x307a0204 0x00080808
102 DATA 4 0x307a0214 0x07070707
104 DATA 4 0x307a0218 0x07070707
106 DATA 4 0x307a0240 0x06000601
108 DATA 4 0x307a0244 0x00000001
110 DATA 4 0x30391000 0x00000000
111 /* DDR_PHY_PHY_CON0 */
112 DATA 4 0x30790000 0x17420f40
113 /* DDR_PHY_PHY_CON1 */
114 DATA 4 0x30790004 0x10210100
115 /* DDR_PHY_PHY_CON4 */
116 DATA 4 0x30790010 0x00060807
117 /* DDR_PHY_MDLL_CON0 */
118 DATA 4 0x307900b0 0x1010007e
119 /* DDR_PHY_DRVDS_CON0 */
120 DATA 4 0x3079009c 0x00000d6e
121 /* DDR_PHY_OFFSET_RD_CON0 */
122 DATA 4 0x30790020 0x08080808
123 /* DDR_PHY_OFFSET_WR_CON0 */
124 DATA 4 0x30790030 0x08080808
125 /* DDR_PHY_CMD_SDLL_CON0 */
126 DATA 4 0x30790050 0x01000010
127 DATA 4 0x30790050 0x00000010
129 /* DDR_PHY_ZQ_CON0 */
130 DATA 4 0x307900c0 0x0e407304
131 DATA 4 0x307900c0 0x0e447304
132 DATA 4 0x307900c0 0x0e447306
133 /* DDR_PHY_ZQ_CON1 */
134 CHECK_BITS_SET 4 0x307900c4 0x1
135 /* DDR_PHY_ZQ_CON0 */
136 DATA 4 0x307900c0 0x0e447304
137 DATA 4 0x307900c0 0x0e407304
140 DATA 4 0x30384130 0x00000000
141 /* IOMUXC_GPR_GPR8 */
142 DATA 4 0x30340020 0x00000178
144 DATA 4 0x30384130 0x00000002
145 /* DDR_PHY_LP_CON0 */
146 DATA 4 0x30790018 0x0000000f
149 CHECK_BITS_SET 4 0x307a0004 0x1