board/toradex/colibri_imx7/colibri_imx7.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2016-2018 Toradex AG
   4  */
   5
   6 #include <asm/arch/clock.h>
   7 #include <asm/arch/crm_regs.h>
   8 #include <asm/arch/imx-regs.h>
   9 #include <asm/arch/mx7-pins.h>
  10 #include <asm/arch/sys_proto.h>
  11 #include <asm/gpio.h>
  12 #include <asm/mach-imx/iomux-v3.h>
  13 #include <asm/io.h>
  14 #include <common.h>
  15 #include <dm.h>
  16 #include <dm/platform_data/serial_mxc.h>
  17 #include <fdt_support.h>
  18 #include <fsl_esdhc.h>
  19 #include <jffs2/load_kernel.h>
  20 #include <linux/sizes.h>
  21 #include <mmc.h>
  22 #include <miiphy.h>
  23 #include <mtd_node.h>
  24 #include <netdev.h>
  25 #include <power/pmic.h>
  26 #include <power/rn5t567_pmic.h>
  27 #include <usb.h>
  28 #include <usb/ehci-ci.h>
  29 #include "../common/tdx-common.h"
  30
  31 DECLARE_GLOBAL_DATA_PTR;
  32
  33 #define UART_PAD_CTRL  (PAD_CTL_DSE_3P3V_49OHM | \
  34         PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
  35
  36 #define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
  37         PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
  38
  39 #define ENET_PAD_CTRL  (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
  40 #define ENET_PAD_CTRL_MII  (PAD_CTL_DSE_3P3V_32OHM)
  41
  42 #define ENET_RX_PAD_CTRL  (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
  43
  44 #define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
  45         PAD_CTL_DSE_3P3V_49OHM)
  46
  47 #define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
  48
  49 #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
  50
  51 #define USB_CDET_GPIO   IMX_GPIO_NR(7, 14)
  52
  53 int dram_init(void)
  54 {
  55         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, imx_ddr_size());
  56
  57         return 0;
  58 }
  59
  60 static iomux_v3_cfg_t const uart1_pads[] = {
  61         MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  62         MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  63         MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
  64         MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
  65 };
  66
  67 static iomux_v3_cfg_t const usdhc1_pads[] = {
  68         MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  69         MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  70         MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  71         MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  72         MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  73         MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  74
  75         MX7D_PAD_GPIO1_IO00__GPIO1_IO0 | MUX_PAD_CTRL(NO_PAD_CTRL),
  76 };
  77
  78 #ifdef CONFIG_USB_EHCI_MX7
  79 static iomux_v3_cfg_t const usb_cdet_pads[] = {
  80         MX7D_PAD_ENET1_CRS__GPIO7_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
  81 };
  82 #endif
  83
  84 #ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND
  85 static iomux_v3_cfg_t const gpmi_pads[] = {
  86         MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  87         MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  88         MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  89         MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  90         MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  91         MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  92         MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  93         MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  94         MX7D_PAD_SD3_CLK__NAND_CLE      | MUX_PAD_CTRL(NAND_PAD_CTRL),
  95         MX7D_PAD_SD3_CMD__NAND_ALE      | MUX_PAD_CTRL(NAND_PAD_CTRL),
  96         MX7D_PAD_SD3_STROBE__NAND_RE_B  | MUX_PAD_CTRL(NAND_PAD_CTRL),
  97         MX7D_PAD_SD3_RESET_B__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  98         MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B       | MUX_PAD_CTRL(NAND_PAD_CTRL),
  99         MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B       | MUX_PAD_CTRL(NAND_PAD_CTRL),
 100         MX7D_PAD_SAI1_TX_DATA__NAND_READY_B     | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
 101 };
 102
 103 static void setup_gpmi_nand(void)
 104 {
 105         imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
 106
 107         /* NAND_USDHC_BUS_CLK is set in rom */
 108         set_clk_nand();
 109 }
 110 #endif
 111
 112 #ifdef CONFIG_TARGET_COLIBRI_IMX7_EMMC
 113 static iomux_v3_cfg_t const usdhc3_emmc_pads[] = {
 114         MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 115         MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 116         MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 117         MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 118         MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 119         MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 120         MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 121         MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 122         MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 123         MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 124         MX7D_PAD_SD3_STROBE__SD3_STROBE  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 125
 126         MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 127 };
 128 #endif
 129
 130 #ifdef CONFIG_VIDEO_MXS
 131 static iomux_v3_cfg_t const lcd_pads[] = {
 132         MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
 133         MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
 134         MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
 135         MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
 136         MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 137         MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 138         MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 139         MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 140         MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 141         MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 142         MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 143         MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 144         MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 145         MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 146         MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 147         MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 148         MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 149         MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 150         MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 151         MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 152         MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 153         MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 154 };
 155
 156 static iomux_v3_cfg_t const backlight_pads[] = {
 157         /* Backlight On */
 158         MX7D_PAD_SD1_WP__GPIO5_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL),
 159         /* Backlight PWM<A> (multiplexed pin) */
 160         MX7D_PAD_GPIO1_IO08__GPIO1_IO8   | MUX_PAD_CTRL(NO_PAD_CTRL),
 161         MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
 162 };
 163
 164 #define GPIO_BL_ON IMX_GPIO_NR(5, 1)
 165 #define GPIO_PWM_A IMX_GPIO_NR(1, 8)
 166
 167 static int setup_lcd(void)
 168 {
 169         imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
 170
 171         imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads));
 172
 173         /* Set BL_ON */
 174         gpio_request(GPIO_BL_ON, "BL_ON");
 175         gpio_direction_output(GPIO_BL_ON, 1);
 176
 177         /* Set PWM<A> to full brightness (assuming inversed polarity) */
 178         gpio_request(GPIO_PWM_A, "PWM<A>");
 179         gpio_direction_output(GPIO_PWM_A, 0);
 180
 181         return 0;
 182 }
 183 #endif
 184
 185 #ifdef CONFIG_FEC_MXC
 186 static iomux_v3_cfg_t const fec1_pads[] = {
 187 #ifndef CONFIG_COLIBRI_IMX7_EXT_PHYCLK
 188         MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 | MUX_PAD_CTRL(ENET_PAD_CTRL) | MUX_MODE_SION,
 189 #else
 190         MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 191 #endif
 192         MX7D_PAD_SD2_CD_B__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
 193         MX7D_PAD_SD2_WP__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
 194         MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 195         MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 196         MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 197         MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL   | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 198         MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 199         MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 200         MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
 201 };
 202
 203 static void setup_iomux_fec(void)
 204 {
 205         imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
 206 }
 207 #endif
 208
 209 static void setup_iomux_uart(void)
 210 {
 211         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 212 }
 213
 214 #ifdef CONFIG_FSL_ESDHC
 215
 216 #define USDHC1_CD_GPIO  IMX_GPIO_NR(1, 0)
 217
 218 static struct fsl_esdhc_cfg usdhc_cfg[] = {
 219 #ifdef CONFIG_TARGET_COLIBRI_IMX7_EMMC
 220         {USDHC3_BASE_ADDR},
 221 #endif
 222         {USDHC1_BASE_ADDR, 0, 4},
 223 };
 224
 225 int board_mmc_getcd(struct mmc *mmc)
 226 {
 227         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 228         int ret = 0;
 229
 230         switch (cfg->esdhc_base) {
 231         case USDHC1_BASE_ADDR:
 232                 ret = !gpio_get_value(USDHC1_CD_GPIO);
 233                 break;
 234 #ifdef CONFIG_TARGET_COLIBRI_IMX7_EMMC
 235         case USDHC3_BASE_ADDR:
 236                 ret = 1;
 237                 break;
 238 #endif
 239         }
 240
 241         return ret;
 242 }
 243
 244 int board_mmc_init(bd_t *bis)
 245 {
 246         int i, ret;
 247         /* USDHC1 is mmc0, USDHC3 is mmc1 */
 248         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 249                 switch (i) {
 250                 case 0:
 251                         imx_iomux_v3_setup_multiple_pads(
 252                                 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
 253                         gpio_request(USDHC1_CD_GPIO, "usdhc1_cd");
 254                         gpio_direction_input(USDHC1_CD_GPIO);
 255                         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 256                         break;
 257 #ifdef CONFIG_TARGET_COLIBRI_IMX7_EMMC
 258                 case 1:
 259                         imx_iomux_v3_setup_multiple_pads(usdhc3_emmc_pads,
 260                                 ARRAY_SIZE(usdhc3_emmc_pads));
 261                         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 262                         break;
 263 #endif
 264                 default:
 265                         printf("Warning: you configured more USDHC controllers"
 266                                 "(%d) than supported by the board\n", i + 1);
 267                         return -EINVAL;
 268                 }
 269
 270                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 271                 if (ret)
 272                         return ret;
 273         }
 274
 275         return 0;
 276 }
 277 #endif
 278
 279 #ifdef CONFIG_FEC_MXC
 280 int board_eth_init(bd_t *bis)
 281 {
 282         int ret;
 283
 284         setup_iomux_fec();
 285
 286         ret = fecmxc_initialize_multi(bis, 0,
 287                 CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
 288         if (ret)
 289                 printf("FEC1 MXC: %s:failed\n", __func__);
 290
 291         return ret;
 292 }
 293
 294 static int setup_fec(void)
 295 {
 296         struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
 297                 = (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
 298
 299 #ifndef CONFIG_COLIBRI_IMX7_EXT_PHYCLK
 300         /*
 301          * Use 50M anatop REF_CLK1 for ENET1, clear gpr1[13], set gpr1[17]
 302          * and output it on the pin
 303          */
 304         clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
 305                         IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK,
 306                         IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK);
 307 #else
 308         /* Use 50M external CLK for ENET1, set gpr1[13], clear gpr1[17] */
 309         clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
 310                         IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK,
 311                         IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK);
 312 #endif
 313
 314         return set_clk_enet(ENET_50MHZ);
 315 }
 316
 317 int board_phy_config(struct phy_device *phydev)
 318 {
 319         if (phydev->drv->config)
 320                 phydev->drv->config(phydev);
 321         return 0;
 322 }
 323 #endif
 324
 325 int board_early_init_f(void)
 326 {
 327         setup_iomux_uart();
 328
 329         return 0;
 330 }
 331
 332 int board_init(void)
 333 {
 334         /* address of boot parameters */
 335         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 336
 337 #ifdef CONFIG_FEC_MXC
 338         setup_fec();
 339 #endif
 340
 341 #ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND
 342         setup_gpmi_nand();
 343 #endif
 344
 345 #ifdef CONFIG_VIDEO_MXS
 346         setup_lcd();
 347 #endif
 348
 349 #ifdef CONFIG_USB_EHCI_MX7
 350         imx_iomux_v3_setup_multiple_pads(usb_cdet_pads, ARRAY_SIZE(usb_cdet_pads));
 351         gpio_request(USB_CDET_GPIO, "usb-cdet-gpio");
 352 #endif
 353
 354         return 0;
 355 }
 356
 357 #ifdef CONFIG_DM_PMIC
 358 int power_init_board(void)
 359 {
 360         struct udevice *dev;
 361         int reg, ver;
 362         int ret;
 363
 364
 365         ret = pmic_get("rn5t567", &dev);
 366         if (ret)
 367                 return ret;
 368         ver = pmic_reg_read(dev, RN5T567_LSIVER);
 369         reg = pmic_reg_read(dev, RN5T567_OTPVER);
 370
 371         printf("PMIC:  RN5T567 LSIVER=0x%02x OTPVER=0x%02x\n", ver, reg);
 372
 373         /* set judge and press timer of N_OE to minimal values */
 374         pmic_clrsetbits(dev, RN5T567_NOETIMSETCNT, 0x7, 0);
 375
 376         /* configure sleep slot for 3.3V Ethernet */
 377         reg = pmic_reg_read(dev, RN5T567_LDO1_SLOT);
 378         reg = (reg & 0xf0) | reg >> 4;
 379         pmic_reg_write(dev, RN5T567_LDO1_SLOT, reg);
 380
 381         /* disable DCDC2 discharge to avoid backfeeding through VFB2 */
 382         pmic_clrsetbits(dev, RN5T567_DC2CTL, 0x2, 0);
 383
 384         /* configure sleep slot for ARM rail */
 385         reg = pmic_reg_read(dev, RN5T567_DC2_SLOT);
 386         reg = (reg & 0xf0) | reg >> 4;
 387         pmic_reg_write(dev, RN5T567_DC2_SLOT, reg);
 388
 389         /* disable LDO2 discharge to avoid backfeeding from +V3.3_SD */
 390         pmic_clrsetbits(dev, RN5T567_LDODIS1, 0x2, 0);
 391
 392         return 0;
 393 }
 394
 395 void reset_cpu(ulong addr)
 396 {
 397         struct udevice *dev;
 398
 399         pmic_get("rn5t567", &dev);
 400
 401         /* Use PMIC to reset, set REPWRTIM to 0 and REPWRON to 1 */
 402         pmic_reg_write(dev, RN5T567_REPCNT, 0x1);
 403         pmic_reg_write(dev, RN5T567_SLPCNT, 0x1);
 404
 405         /*
 406          * Re-power factor detection on PMIC side is not instant. 1ms
 407          * proved to be enough time until reset takes effect.
 408          */
 409         mdelay(1);
 410 }
 411 #endif
 412
 413 int checkboard(void)
 414 {
 415         printf("Model: Toradex Colibri iMX7%c\n",
 416                is_cpu_type(MXC_CPU_MX7D) ? 'D' : 'S');
 417
 418         return 0;
 419 }
 420
 421 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 422 int ft_board_setup(void *blob, bd_t *bd)
 423 {
 424 #if defined(CONFIG_FDT_FIXUP_PARTITIONS)
 425         static const struct node_info nodes[] = {
 426                 { "fsl,imx7d-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
 427                 { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
 428         };
 429
 430         /* Update partition nodes using info from mtdparts env var */
 431         puts("   Updating MTD partitions...\n");
 432         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
 433 #endif
 434
 435         return ft_common_board_setup(blob, bd);
 436 }
 437 #endif
 438
 439 #ifdef CONFIG_USB_EHCI_MX7
 440 static iomux_v3_cfg_t const usb_otg2_pads[] = {
 441         MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
 442 };
 443
 444 int board_ehci_hcd_init(int port)
 445 {
 446         switch (port) {
 447         case 0:
 448                 break;
 449         case 1:
 450                 if (is_cpu_type(MXC_CPU_MX7S))
 451                         return -ENODEV;
 452
 453                 imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
 454                                                  ARRAY_SIZE(usb_otg2_pads));
 455                 break;
 456         default:
 457                 return -EINVAL;
 458         }
 459         return 0;
 460 }
 461
 462 int board_usb_phy_mode(int port)
 463 {
 464         switch (port) {
 465         case 0:
 466                 if (gpio_get_value(USB_CDET_GPIO))
 467                         return USB_INIT_DEVICE;
 468                 else
 469                         return USB_INIT_HOST;
 470         case 1:
 471         default:
 472                 return USB_INIT_HOST;
 473         }
 474 }
 475 #endif