board/toradex/colibri_imx7/colibri_imx7.c

   1 /*
   2  * Copyright (C) 2016 Toradex AG
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <asm/arch/clock.h>
   8 #include <asm/arch/crm_regs.h>
   9 #include <asm/arch/imx-regs.h>
  10 #include <asm/arch/mx7-pins.h>
  11 #include <asm/arch/sys_proto.h>
  12 #include <asm/gpio.h>
  13 #include <asm/imx-common/boot_mode.h>
  14 #include <asm/imx-common/iomux-v3.h>
  15 #include <asm/io.h>
  16 #include <common.h>
  17 #include <dm.h>
  18 #include <dm/platform_data/serial_mxc.h>
  19 #include <fsl_esdhc.h>
  20 #include <linux/sizes.h>
  21 #include <mmc.h>
  22 #include <miiphy.h>
  23 #include <netdev.h>
  24 #include <power/pmic.h>
  25 #include <power/rn5t567_pmic.h>
  26 #include <usb/ehci-ci.h>
  27
  28 DECLARE_GLOBAL_DATA_PTR;
  29
  30 #define UART_PAD_CTRL  (PAD_CTL_DSE_3P3V_49OHM | \
  31         PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
  32
  33 #define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
  34         PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
  35
  36 #define ENET_PAD_CTRL  (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
  37 #define ENET_PAD_CTRL_MII  (PAD_CTL_DSE_3P3V_32OHM)
  38
  39 #define ENET_RX_PAD_CTRL  (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
  40
  41 #define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
  42         PAD_CTL_DSE_3P3V_49OHM)
  43
  44 #define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
  45
  46 #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
  47
  48 int dram_init(void)
  49 {
  50         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  51
  52         return 0;
  53 }
  54
  55 static iomux_v3_cfg_t const uart1_pads[] = {
  56         MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  57         MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  58         MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
  59         MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
  60 };
  61
  62 static iomux_v3_cfg_t const usdhc1_pads[] = {
  63         MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  64         MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  65         MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  66         MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  67         MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  68         MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  69
  70         MX7D_PAD_GPIO1_IO00__GPIO1_IO0 | MUX_PAD_CTRL(NO_PAD_CTRL),
  71 };
  72
  73 #ifdef CONFIG_NAND_MXS
  74 static iomux_v3_cfg_t const gpmi_pads[] = {
  75         MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  76         MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  77         MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  78         MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  79         MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  80         MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  81         MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  82         MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  83         MX7D_PAD_SD3_CLK__NAND_CLE      | MUX_PAD_CTRL(NAND_PAD_CTRL),
  84         MX7D_PAD_SD3_CMD__NAND_ALE      | MUX_PAD_CTRL(NAND_PAD_CTRL),
  85         MX7D_PAD_SD3_STROBE__NAND_RE_B  | MUX_PAD_CTRL(NAND_PAD_CTRL),
  86         MX7D_PAD_SD3_RESET_B__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  87         MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B       | MUX_PAD_CTRL(NAND_PAD_CTRL),
  88         MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B       | MUX_PAD_CTRL(NAND_PAD_CTRL),
  89         MX7D_PAD_SAI1_TX_DATA__NAND_READY_B     | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
  90 };
  91
  92 static void setup_gpmi_nand(void)
  93 {
  94         imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
  95
  96         /* NAND_USDHC_BUS_CLK is set in rom */
  97         set_clk_nand();
  98 }
  99 #endif
 100
 101 static iomux_v3_cfg_t const usdhc3_emmc_pads[] = {
 102         MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 103         MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 104         MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 105         MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 106         MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 107         MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 108         MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 109         MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 110         MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 111         MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 112         MX7D_PAD_SD3_STROBE__SD3_STROBE  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 113
 114         MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 115 };
 116
 117 #ifdef CONFIG_VIDEO_MXS
 118 static iomux_v3_cfg_t const lcd_pads[] = {
 119         MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
 120         MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
 121         MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
 122         MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
 123         MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 124         MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 125         MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 126         MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 127         MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 128         MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 129         MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 130         MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 131         MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 132         MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 133         MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 134         MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 135         MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 136         MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 137         MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 138         MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 139         MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 140         MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 141 };
 142
 143 static iomux_v3_cfg_t const backlight_pads[] = {
 144         /* Backlight On */
 145         MX7D_PAD_SD1_WP__GPIO5_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL),
 146         /* Backlight PWM<A> (multiplexed pin) */
 147         MX7D_PAD_GPIO1_IO08__GPIO1_IO8   | MUX_PAD_CTRL(NO_PAD_CTRL),
 148         MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
 149 };
 150
 151 #define GPIO_BL_ON IMX_GPIO_NR(5, 1)
 152 #define GPIO_PWM_A IMX_GPIO_NR(1, 8)
 153
 154 static int setup_lcd(void)
 155 {
 156         imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
 157
 158         imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads));
 159
 160         /* Set BL_ON */
 161         gpio_request(GPIO_BL_ON, "BL_ON");
 162         gpio_direction_output(GPIO_BL_ON, 1);
 163
 164         /* Set PWM<A> to full brightness (assuming inversed polarity) */
 165         gpio_request(GPIO_PWM_A, "PWM<A>");
 166         gpio_direction_output(GPIO_PWM_A, 0);
 167
 168         return 0;
 169 }
 170 #endif
 171
 172 #ifdef CONFIG_FEC_MXC
 173 static iomux_v3_cfg_t const fec1_pads[] = {
 174 #ifndef CONFIG_COLIBRI_IMX7_EXT_PHYCLK
 175         MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 | MUX_PAD_CTRL(ENET_PAD_CTRL) | MUX_MODE_SION,
 176 #else
 177         MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 178 #endif
 179         MX7D_PAD_SD2_CD_B__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
 180         MX7D_PAD_SD2_WP__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
 181         MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 182         MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 183         MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 184         MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL   | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 185         MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 186         MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 187         MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
 188 };
 189
 190 static void setup_iomux_fec(void)
 191 {
 192         imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
 193 }
 194 #endif
 195
 196 static void setup_iomux_uart(void)
 197 {
 198         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 199 }
 200
 201 #ifdef CONFIG_FSL_ESDHC
 202
 203 #define USDHC1_CD_GPIO  IMX_GPIO_NR(1, 0)
 204
 205 static struct fsl_esdhc_cfg usdhc_cfg[] = {
 206         {USDHC1_BASE_ADDR, 0, 4},
 207 };
 208
 209 int board_mmc_getcd(struct mmc *mmc)
 210 {
 211         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 212         int ret = 0;
 213
 214         switch (cfg->esdhc_base) {
 215         case USDHC1_BASE_ADDR:
 216                 ret = !gpio_get_value(USDHC1_CD_GPIO);
 217                 break;
 218         }
 219
 220         return ret;
 221 }
 222
 223 int board_mmc_init(bd_t *bis)
 224 {
 225         int i, ret;
 226         /* USDHC1 is mmc0 */
 227         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 228                 switch (i) {
 229                 case 0:
 230                         imx_iomux_v3_setup_multiple_pads(
 231                                 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
 232                         gpio_request(USDHC1_CD_GPIO, "usdhc1_cd");
 233                         gpio_direction_input(USDHC1_CD_GPIO);
 234                         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 235                         break;
 236                 default:
 237                         printf("Warning: you configured more USDHC controllers"
 238                                 "(%d) than supported by the board\n", i + 1);
 239                         return -EINVAL;
 240                 }
 241
 242                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 243                 if (ret)
 244                         return ret;
 245         }
 246
 247         return 0;
 248 }
 249 #endif
 250
 251 #ifdef CONFIG_FEC_MXC
 252 int board_eth_init(bd_t *bis)
 253 {
 254         int ret;
 255
 256         setup_iomux_fec();
 257
 258         ret = fecmxc_initialize_multi(bis, 0,
 259                 CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
 260         if (ret)
 261                 printf("FEC1 MXC: %s:failed\n", __func__);
 262
 263         return ret;
 264 }
 265
 266 static int setup_fec(void)
 267 {
 268         struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
 269                 = (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
 270
 271 #ifndef CONFIG_COLIBRI_IMX7_EXT_PHYCLK
 272         /*
 273          * Use 50M anatop REF_CLK1 for ENET1, clear gpr1[13], set gpr1[17]
 274          * and output it on the pin
 275          */
 276         clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
 277                         IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK,
 278                         IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK);
 279 #else
 280         /* Use 50M external CLK for ENET1, set gpr1[13], clear gpr1[17] */
 281         clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
 282                         IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK,
 283                         IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK);
 284 #endif
 285
 286         return set_clk_enet(ENET_50MHz);
 287 }
 288
 289 int board_phy_config(struct phy_device *phydev)
 290 {
 291         if (phydev->drv->config)
 292                 phydev->drv->config(phydev);
 293         return 0;
 294 }
 295 #endif
 296
 297 int board_early_init_f(void)
 298 {
 299         setup_iomux_uart();
 300
 301         return 0;
 302 }
 303
 304 int board_init(void)
 305 {
 306         /* address of boot parameters */
 307         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 308
 309 #ifdef CONFIG_FEC_MXC
 310         setup_fec();
 311 #endif
 312
 313 #ifdef CONFIG_NAND_MXS
 314         setup_gpmi_nand();
 315 #endif
 316
 317 #ifdef CONFIG_VIDEO_MXS
 318         setup_lcd();
 319 #endif
 320
 321         return 0;
 322 }
 323
 324 #ifdef CONFIG_CMD_BMODE
 325 static const struct boot_mode board_boot_modes[] = {
 326         /* 4 bit bus width */
 327         {"nand", MAKE_CFGVAL(0x40, 0x34, 0x00, 0x00)},
 328         {"sd1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)},
 329         {NULL, 0},
 330 };
 331 #endif
 332
 333 int board_late_init(void)
 334 {
 335 #ifdef CONFIG_CMD_BMODE
 336         add_board_boot_modes(board_boot_modes);
 337 #endif
 338
 339         return 0;
 340 }
 341
 342 #ifdef CONFIG_DM_PMIC
 343 int power_init_board(void)
 344 {
 345         struct udevice *dev;
 346         int reg, ver;
 347         int ret;
 348
 349
 350         ret = pmic_get("rn5t567", &dev);
 351         if (ret)
 352                 return ret;
 353         ver = pmic_reg_read(dev, RN5T567_LSIVER);
 354         reg = pmic_reg_read(dev, RN5T567_OTPVER);
 355
 356         printf("PMIC:  RN5T567 LSIVER=0x%02x OTPVER=0x%02x\n", ver, reg);
 357
 358         /* set judge and press timer of N_OE to minimal values */
 359         pmic_clrsetbits(dev, RN5T567_NOETIMSETCNT, 0x7, 0);
 360
 361         return 0;
 362 }
 363
 364 void reset_cpu(ulong addr)
 365 {
 366         struct udevice *dev;
 367
 368         pmic_get("rn5t567", &dev);
 369
 370         /* Use PMIC to reset, set REPWRTIM to 0 and REPWRON to 1 */
 371         pmic_reg_write(dev, RN5T567_REPCNT, 0x1);
 372         pmic_reg_write(dev, RN5T567_SLPCNT, 0x1);
 373
 374         /*
 375          * Re-power factor detection on PMIC side is not instant. 1ms
 376          * proved to be enough time until reset takes effect.
 377          */
 378         mdelay(1);
 379 }
 380 #endif
 381
 382 int checkboard(void)
 383 {
 384         printf("Model: Toradex Colibri iMX7%c\n",
 385                is_cpu_type(MXC_CPU_MX7D) ? 'D' : 'S');
 386
 387         return 0;
 388 }
 389
 390 #ifdef CONFIG_USB_EHCI_MX7
 391 static iomux_v3_cfg_t const usb_otg2_pads[] = {
 392         MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
 393 };
 394
 395 int board_ehci_hcd_init(int port)
 396 {
 397         switch (port) {
 398         case 0:
 399                 break;
 400         case 1:
 401                 if (is_cpu_type(MXC_CPU_MX7S))
 402                         return -ENODEV;
 403
 404                 imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
 405                                                  ARRAY_SIZE(usb_otg2_pads));
 406                 break;
 407         default:
 408                 return -EINVAL;
 409         }
 410         return 0;
 411 }
 412 #endif