board/toradex/colibri_imx7/colibri_imx7.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2016-2018 Toradex AG
   4  */
   5
   6 #include <common.h>
   7 #include <cpu_func.h>
   8 #include <init.h>
   9 #include <asm/arch/clock.h>
  10 #include <asm/arch/crm_regs.h>
  11 #include <asm/arch/imx-regs.h>
  12 #include <asm/arch/mx7-pins.h>
  13 #include <asm/arch/sys_proto.h>
  14 #include <asm/gpio.h>
  15 #include <asm/mach-imx/iomux-v3.h>
  16 #include <asm/io.h>
  17 #include <common.h>
  18 #include <dm.h>
  19 #include <dm/platform_data/serial_mxc.h>
  20 #include <fdt_support.h>
  21 #include <fsl_esdhc_imx.h>
  22 #include <jffs2/load_kernel.h>
  23 #include <linux/sizes.h>
  24 #include <mmc.h>
  25 #include <miiphy.h>
  26 #include <mtd_node.h>
  27 #include <netdev.h>
  28 #include <power/pmic.h>
  29 #include <power/rn5t567_pmic.h>
  30 #include <usb.h>
  31 #include <usb/ehci-ci.h>
  32 #include "../common/tdx-common.h"
  33
  34 DECLARE_GLOBAL_DATA_PTR;
  35
  36 #define UART_PAD_CTRL  (PAD_CTL_DSE_3P3V_49OHM | \
  37         PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
  38
  39 #define ENET_PAD_CTRL  (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
  40 #define ENET_PAD_CTRL_MII  (PAD_CTL_DSE_3P3V_32OHM)
  41
  42 #define ENET_RX_PAD_CTRL  (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
  43
  44 #define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
  45         PAD_CTL_DSE_3P3V_49OHM)
  46
  47 #define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
  48
  49 #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
  50
  51 #define USB_CDET_GPIO   IMX_GPIO_NR(7, 14)
  52
  53 int dram_init(void)
  54 {
  55         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, imx_ddr_size());
  56
  57         return 0;
  58 }
  59
  60 static iomux_v3_cfg_t const uart1_pads[] = {
  61         MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  62         MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  63         MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
  64         MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
  65 };
  66
  67 #ifdef CONFIG_USB_EHCI_MX7
  68 static iomux_v3_cfg_t const usb_cdet_pads[] = {
  69         MX7D_PAD_ENET1_CRS__GPIO7_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
  70 };
  71 #endif
  72
  73 #ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND
  74 static iomux_v3_cfg_t const gpmi_pads[] = {
  75         MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  76         MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  77         MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  78         MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  79         MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  80         MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  81         MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  82         MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  83         MX7D_PAD_SD3_CLK__NAND_CLE      | MUX_PAD_CTRL(NAND_PAD_CTRL),
  84         MX7D_PAD_SD3_CMD__NAND_ALE      | MUX_PAD_CTRL(NAND_PAD_CTRL),
  85         MX7D_PAD_SD3_STROBE__NAND_RE_B  | MUX_PAD_CTRL(NAND_PAD_CTRL),
  86         MX7D_PAD_SD3_RESET_B__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  87         MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B       | MUX_PAD_CTRL(NAND_PAD_CTRL),
  88         MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B       | MUX_PAD_CTRL(NAND_PAD_CTRL),
  89         MX7D_PAD_SAI1_TX_DATA__NAND_READY_B     | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
  90 };
  91
  92 static void setup_gpmi_nand(void)
  93 {
  94         imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
  95
  96         /* NAND_USDHC_BUS_CLK is set in rom */
  97         set_clk_nand();
  98 }
  99 #endif
 100
 101 #ifdef CONFIG_VIDEO_MXS
 102 static iomux_v3_cfg_t const lcd_pads[] = {
 103         MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
 104         MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
 105         MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
 106         MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
 107         MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 108         MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 109         MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 110         MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 111         MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 112         MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 113         MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 114         MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 115         MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 116         MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 117         MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 118         MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 119         MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 120         MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 121         MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 122         MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 123         MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 124         MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 125 };
 126
 127 static iomux_v3_cfg_t const backlight_pads[] = {
 128         /* Backlight On */
 129         MX7D_PAD_SD1_WP__GPIO5_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL),
 130         /* Backlight PWM<A> (multiplexed pin) */
 131         MX7D_PAD_GPIO1_IO08__GPIO1_IO8   | MUX_PAD_CTRL(NO_PAD_CTRL),
 132         MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
 133 };
 134
 135 #define GPIO_BL_ON IMX_GPIO_NR(5, 1)
 136 #define GPIO_PWM_A IMX_GPIO_NR(1, 8)
 137
 138 static int setup_lcd(void)
 139 {
 140         imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
 141
 142         imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads));
 143
 144         /* Set BL_ON */
 145         gpio_request(GPIO_BL_ON, "BL_ON");
 146         gpio_direction_output(GPIO_BL_ON, 1);
 147
 148         /* Set PWM<A> to full brightness (assuming inversed polarity) */
 149         gpio_request(GPIO_PWM_A, "PWM<A>");
 150         gpio_direction_output(GPIO_PWM_A, 0);
 151
 152         return 0;
 153 }
 154 #endif
 155
 156 /*
 157  * Backlight off before OS handover
 158  */
 159 void board_preboot_os(void)
 160 {
 161         gpio_direction_output(GPIO_PWM_A, 1);
 162         gpio_direction_output(GPIO_BL_ON, 0);
 163 }
 164
 165 static void setup_iomux_uart(void)
 166 {
 167         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 168 }
 169
 170 #ifdef CONFIG_FEC_MXC
 171 static int setup_fec(void)
 172 {
 173         struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
 174                 = (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
 175
 176 #ifndef CONFIG_COLIBRI_IMX7_EXT_PHYCLK
 177         /*
 178          * Use 50M anatop REF_CLK1 for ENET1, clear gpr1[13], set gpr1[17]
 179          * and output it on the pin
 180          */
 181         clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
 182                         IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK,
 183                         IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK);
 184 #else
 185         /* Use 50M external CLK for ENET1, set gpr1[13], clear gpr1[17] */
 186         clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
 187                         IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK,
 188                         IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK);
 189 #endif
 190
 191         return set_clk_enet(ENET_50MHZ);
 192 }
 193
 194 #endif
 195
 196 int board_early_init_f(void)
 197 {
 198         setup_iomux_uart();
 199
 200         return 0;
 201 }
 202
 203 int board_init(void)
 204 {
 205         /* address of boot parameters */
 206         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 207
 208 #ifdef CONFIG_FEC_MXC
 209         setup_fec();
 210 #endif
 211
 212 #ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND
 213         setup_gpmi_nand();
 214 #endif
 215
 216 #ifdef CONFIG_VIDEO_MXS
 217         setup_lcd();
 218 #endif
 219
 220 #ifdef CONFIG_USB_EHCI_MX7
 221         imx_iomux_v3_setup_multiple_pads(usb_cdet_pads, ARRAY_SIZE(usb_cdet_pads));
 222         gpio_request(USB_CDET_GPIO, "usb-cdet-gpio");
 223 #endif
 224
 225         return 0;
 226 }
 227
 228 #ifdef CONFIG_DM_PMIC
 229 int power_init_board(void)
 230 {
 231         struct udevice *dev;
 232         int reg, ver;
 233         int ret;
 234
 235
 236         ret = pmic_get("rn5t567@33", &dev);
 237         if (ret)
 238                 return ret;
 239         ver = pmic_reg_read(dev, RN5T567_LSIVER);
 240         reg = pmic_reg_read(dev, RN5T567_OTPVER);
 241
 242         printf("PMIC:  RN5T567 LSIVER=0x%02x OTPVER=0x%02x\n", ver, reg);
 243
 244         /* set judge and press timer of N_OE to minimal values */
 245         pmic_clrsetbits(dev, RN5T567_NOETIMSETCNT, 0x7, 0);
 246
 247         /* configure sleep slot for 3.3V Ethernet */
 248         reg = pmic_reg_read(dev, RN5T567_LDO1_SLOT);
 249         reg = (reg & 0xf0) | reg >> 4;
 250         pmic_reg_write(dev, RN5T567_LDO1_SLOT, reg);
 251
 252         /* disable DCDC2 discharge to avoid backfeeding through VFB2 */
 253         pmic_clrsetbits(dev, RN5T567_DC2CTL, 0x2, 0);
 254
 255         /* configure sleep slot for ARM rail */
 256         reg = pmic_reg_read(dev, RN5T567_DC2_SLOT);
 257         reg = (reg & 0xf0) | reg >> 4;
 258         pmic_reg_write(dev, RN5T567_DC2_SLOT, reg);
 259
 260         /* disable LDO2 discharge to avoid backfeeding from +V3.3_SD */
 261         pmic_clrsetbits(dev, RN5T567_LDODIS1, 0x2, 0);
 262
 263         return 0;
 264 }
 265
 266 void reset_cpu(ulong addr)
 267 {
 268         struct udevice *dev;
 269
 270         pmic_get("rn5t567@33", &dev);
 271
 272         /* Use PMIC to reset, set REPWRTIM to 0 and REPWRON to 1 */
 273         pmic_reg_write(dev, RN5T567_REPCNT, 0x1);
 274         pmic_reg_write(dev, RN5T567_SLPCNT, 0x1);
 275
 276         /*
 277          * Re-power factor detection on PMIC side is not instant. 1ms
 278          * proved to be enough time until reset takes effect.
 279          */
 280         mdelay(1);
 281 }
 282 #endif
 283
 284 int checkboard(void)
 285 {
 286         printf("Model: Toradex Colibri iMX7%c\n",
 287                is_cpu_type(MXC_CPU_MX7D) ? 'D' : 'S');
 288
 289         return 0;
 290 }
 291
 292 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 293 int ft_board_setup(void *blob, bd_t *bd)
 294 {
 295 #if defined(CONFIG_IMX_BOOTAUX) && defined(CONFIG_ARCH_FIXUP_FDT_MEMORY)
 296         int up;
 297
 298         up = arch_auxiliary_core_check_up(0);
 299         if (up) {
 300                 int ret;
 301                 int areas = 1;
 302                 u64 start[2], size[2];
 303
 304                 /*
 305                  * Reserve 1MB of memory for M4 (1MiB is also the minimum
 306                  * alignment for Linux due to MMU section size restrictions).
 307                  */
 308                 start[0] = gd->bd->bi_dram[0].start;
 309                 size[0] = SZ_256M - SZ_1M;
 310
 311                 /* If needed, create a second entry for memory beyond 256M */
 312                 if (gd->bd->bi_dram[0].size > SZ_256M) {
 313                         start[1] = gd->bd->bi_dram[0].start + SZ_256M;
 314                         size[1] = gd->bd->bi_dram[0].size - SZ_256M;
 315                         areas = 2;
 316                 }
 317
 318                 ret = fdt_set_usable_memory(blob, start, size, areas);
 319                 if (ret) {
 320                         eprintf("Cannot set usable memory\n");
 321                         return ret;
 322                 }
 323         } else {
 324                 int off;
 325
 326                 off = fdt_node_offset_by_compatible(blob, -1,
 327                                                     "fsl,imx7d-rpmsg");
 328                 if (off > 0)
 329                         fdt_status_disabled(blob, off);
 330         }
 331 #endif
 332 #if defined(CONFIG_FDT_FIXUP_PARTITIONS)
 333         static const struct node_info nodes[] = {
 334                 { "fsl,imx7d-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
 335                 { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
 336         };
 337
 338         /* Update partition nodes using info from mtdparts env var */
 339         puts("   Updating MTD partitions...\n");
 340         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
 341 #endif
 342
 343         return ft_common_board_setup(blob, bd);
 344 }
 345 #endif
 346
 347 #ifdef CONFIG_USB_EHCI_MX7
 348 static iomux_v3_cfg_t const usb_otg2_pads[] = {
 349         MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
 350 };
 351
 352 int board_ehci_hcd_init(int port)
 353 {
 354         switch (port) {
 355         case 0:
 356                 break;
 357         case 1:
 358                 if (is_cpu_type(MXC_CPU_MX7S))
 359                         return -ENODEV;
 360
 361                 imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
 362                                                  ARRAY_SIZE(usb_otg2_pads));
 363                 break;
 364         default:
 365                 return -EINVAL;
 366         }
 367         return 0;
 368 }
 369
 370 int board_usb_phy_mode(int port)
 371 {
 372         switch (port) {
 373         case 0:
 374                 if (gpio_get_value(USB_CDET_GPIO))
 375                         return USB_INIT_DEVICE;
 376                 else
 377                         return USB_INIT_HOST;
 378         case 1:
 379         default:
 380                 return USB_INIT_HOST;
 381         }
 382 }
 383 #endif