board/toradex/colibri_imx7/colibri_imx7.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2016-2018 Toradex AG
   4  */
   5
   6 #include <cpu_func.h>
   7 #include <asm/arch/clock.h>
   8 #include <asm/arch/crm_regs.h>
   9 #include <asm/arch/imx-regs.h>
  10 #include <asm/arch/mx7-pins.h>
  11 #include <asm/arch/sys_proto.h>
  12 #include <asm/gpio.h>
  13 #include <asm/mach-imx/iomux-v3.h>
  14 #include <asm/io.h>
  15 #include <common.h>
  16 #include <dm.h>
  17 #include <dm/platform_data/serial_mxc.h>
  18 #include <fdt_support.h>
  19 #include <fsl_esdhc_imx.h>
  20 #include <jffs2/load_kernel.h>
  21 #include <linux/sizes.h>
  22 #include <mmc.h>
  23 #include <miiphy.h>
  24 #include <mtd_node.h>
  25 #include <netdev.h>
  26 #include <power/pmic.h>
  27 #include <power/rn5t567_pmic.h>
  28 #include <usb.h>
  29 #include <usb/ehci-ci.h>
  30 #include "../common/tdx-common.h"
  31
  32 DECLARE_GLOBAL_DATA_PTR;
  33
  34 #define UART_PAD_CTRL  (PAD_CTL_DSE_3P3V_49OHM | \
  35         PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
  36
  37 #define ENET_PAD_CTRL  (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
  38 #define ENET_PAD_CTRL_MII  (PAD_CTL_DSE_3P3V_32OHM)
  39
  40 #define ENET_RX_PAD_CTRL  (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
  41
  42 #define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
  43         PAD_CTL_DSE_3P3V_49OHM)
  44
  45 #define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
  46
  47 #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
  48
  49 #define USB_CDET_GPIO   IMX_GPIO_NR(7, 14)
  50
  51 int dram_init(void)
  52 {
  53         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, imx_ddr_size());
  54
  55         return 0;
  56 }
  57
  58 static iomux_v3_cfg_t const uart1_pads[] = {
  59         MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  60         MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  61         MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
  62         MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
  63 };
  64
  65 #ifdef CONFIG_USB_EHCI_MX7
  66 static iomux_v3_cfg_t const usb_cdet_pads[] = {
  67         MX7D_PAD_ENET1_CRS__GPIO7_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
  68 };
  69 #endif
  70
  71 #ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND
  72 static iomux_v3_cfg_t const gpmi_pads[] = {
  73         MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  74         MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  75         MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  76         MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  77         MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  78         MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  79         MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  80         MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  81         MX7D_PAD_SD3_CLK__NAND_CLE      | MUX_PAD_CTRL(NAND_PAD_CTRL),
  82         MX7D_PAD_SD3_CMD__NAND_ALE      | MUX_PAD_CTRL(NAND_PAD_CTRL),
  83         MX7D_PAD_SD3_STROBE__NAND_RE_B  | MUX_PAD_CTRL(NAND_PAD_CTRL),
  84         MX7D_PAD_SD3_RESET_B__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  85         MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B       | MUX_PAD_CTRL(NAND_PAD_CTRL),
  86         MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B       | MUX_PAD_CTRL(NAND_PAD_CTRL),
  87         MX7D_PAD_SAI1_TX_DATA__NAND_READY_B     | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
  88 };
  89
  90 static void setup_gpmi_nand(void)
  91 {
  92         imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
  93
  94         /* NAND_USDHC_BUS_CLK is set in rom */
  95         set_clk_nand();
  96 }
  97 #endif
  98
  99 #ifdef CONFIG_VIDEO_MXS
 100 static iomux_v3_cfg_t const lcd_pads[] = {
 101         MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
 102         MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
 103         MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
 104         MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
 105         MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 106         MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 107         MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 108         MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 109         MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 110         MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 111         MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 112         MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 113         MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 114         MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 115         MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 116         MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 117         MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 118         MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 119         MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 120         MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 121         MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 122         MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 123 };
 124
 125 static iomux_v3_cfg_t const backlight_pads[] = {
 126         /* Backlight On */
 127         MX7D_PAD_SD1_WP__GPIO5_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL),
 128         /* Backlight PWM<A> (multiplexed pin) */
 129         MX7D_PAD_GPIO1_IO08__GPIO1_IO8   | MUX_PAD_CTRL(NO_PAD_CTRL),
 130         MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
 131 };
 132
 133 #define GPIO_BL_ON IMX_GPIO_NR(5, 1)
 134 #define GPIO_PWM_A IMX_GPIO_NR(1, 8)
 135
 136 static int setup_lcd(void)
 137 {
 138         imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
 139
 140         imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads));
 141
 142         /* Set BL_ON */
 143         gpio_request(GPIO_BL_ON, "BL_ON");
 144         gpio_direction_output(GPIO_BL_ON, 1);
 145
 146         /* Set PWM<A> to full brightness (assuming inversed polarity) */
 147         gpio_request(GPIO_PWM_A, "PWM<A>");
 148         gpio_direction_output(GPIO_PWM_A, 0);
 149
 150         return 0;
 151 }
 152 #endif
 153
 154 /*
 155  * Backlight off before OS handover
 156  */
 157 void board_preboot_os(void)
 158 {
 159         gpio_direction_output(GPIO_PWM_A, 1);
 160         gpio_direction_output(GPIO_BL_ON, 0);
 161 }
 162
 163 static void setup_iomux_uart(void)
 164 {
 165         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 166 }
 167
 168 #ifdef CONFIG_FEC_MXC
 169 static int setup_fec(void)
 170 {
 171         struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
 172                 = (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
 173
 174 #ifndef CONFIG_COLIBRI_IMX7_EXT_PHYCLK
 175         /*
 176          * Use 50M anatop REF_CLK1 for ENET1, clear gpr1[13], set gpr1[17]
 177          * and output it on the pin
 178          */
 179         clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
 180                         IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK,
 181                         IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK);
 182 #else
 183         /* Use 50M external CLK for ENET1, set gpr1[13], clear gpr1[17] */
 184         clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
 185                         IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK,
 186                         IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK);
 187 #endif
 188
 189         return set_clk_enet(ENET_50MHZ);
 190 }
 191
 192 #endif
 193
 194 int board_early_init_f(void)
 195 {
 196         setup_iomux_uart();
 197
 198         return 0;
 199 }
 200
 201 int board_init(void)
 202 {
 203         /* address of boot parameters */
 204         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 205
 206 #ifdef CONFIG_FEC_MXC
 207         setup_fec();
 208 #endif
 209
 210 #ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND
 211         setup_gpmi_nand();
 212 #endif
 213
 214 #ifdef CONFIG_VIDEO_MXS
 215         setup_lcd();
 216 #endif
 217
 218 #ifdef CONFIG_USB_EHCI_MX7
 219         imx_iomux_v3_setup_multiple_pads(usb_cdet_pads, ARRAY_SIZE(usb_cdet_pads));
 220         gpio_request(USB_CDET_GPIO, "usb-cdet-gpio");
 221 #endif
 222
 223         return 0;
 224 }
 225
 226 #ifdef CONFIG_DM_PMIC
 227 int power_init_board(void)
 228 {
 229         struct udevice *dev;
 230         int reg, ver;
 231         int ret;
 232
 233
 234         ret = pmic_get("rn5t567@33", &dev);
 235         if (ret)
 236                 return ret;
 237         ver = pmic_reg_read(dev, RN5T567_LSIVER);
 238         reg = pmic_reg_read(dev, RN5T567_OTPVER);
 239
 240         printf("PMIC:  RN5T567 LSIVER=0x%02x OTPVER=0x%02x\n", ver, reg);
 241
 242         /* set judge and press timer of N_OE to minimal values */
 243         pmic_clrsetbits(dev, RN5T567_NOETIMSETCNT, 0x7, 0);
 244
 245         /* configure sleep slot for 3.3V Ethernet */
 246         reg = pmic_reg_read(dev, RN5T567_LDO1_SLOT);
 247         reg = (reg & 0xf0) | reg >> 4;
 248         pmic_reg_write(dev, RN5T567_LDO1_SLOT, reg);
 249
 250         /* disable DCDC2 discharge to avoid backfeeding through VFB2 */
 251         pmic_clrsetbits(dev, RN5T567_DC2CTL, 0x2, 0);
 252
 253         /* configure sleep slot for ARM rail */
 254         reg = pmic_reg_read(dev, RN5T567_DC2_SLOT);
 255         reg = (reg & 0xf0) | reg >> 4;
 256         pmic_reg_write(dev, RN5T567_DC2_SLOT, reg);
 257
 258         /* disable LDO2 discharge to avoid backfeeding from +V3.3_SD */
 259         pmic_clrsetbits(dev, RN5T567_LDODIS1, 0x2, 0);
 260
 261         return 0;
 262 }
 263
 264 void reset_cpu(ulong addr)
 265 {
 266         struct udevice *dev;
 267
 268         pmic_get("rn5t567@33", &dev);
 269
 270         /* Use PMIC to reset, set REPWRTIM to 0 and REPWRON to 1 */
 271         pmic_reg_write(dev, RN5T567_REPCNT, 0x1);
 272         pmic_reg_write(dev, RN5T567_SLPCNT, 0x1);
 273
 274         /*
 275          * Re-power factor detection on PMIC side is not instant. 1ms
 276          * proved to be enough time until reset takes effect.
 277          */
 278         mdelay(1);
 279 }
 280 #endif
 281
 282 int checkboard(void)
 283 {
 284         printf("Model: Toradex Colibri iMX7%c\n",
 285                is_cpu_type(MXC_CPU_MX7D) ? 'D' : 'S');
 286
 287         return 0;
 288 }
 289
 290 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 291 int ft_board_setup(void *blob, bd_t *bd)
 292 {
 293 #if defined(CONFIG_IMX_BOOTAUX) && defined(CONFIG_ARCH_FIXUP_FDT_MEMORY)
 294         int up;
 295
 296         up = arch_auxiliary_core_check_up(0);
 297         if (up) {
 298                 int ret;
 299                 int areas = 1;
 300                 u64 start[2], size[2];
 301
 302                 /*
 303                  * Reserve 1MB of memory for M4 (1MiB is also the minimum
 304                  * alignment for Linux due to MMU section size restrictions).
 305                  */
 306                 start[0] = gd->bd->bi_dram[0].start;
 307                 size[0] = SZ_256M - SZ_1M;
 308
 309                 /* If needed, create a second entry for memory beyond 256M */
 310                 if (gd->bd->bi_dram[0].size > SZ_256M) {
 311                         start[1] = gd->bd->bi_dram[0].start + SZ_256M;
 312                         size[1] = gd->bd->bi_dram[0].size - SZ_256M;
 313                         areas = 2;
 314                 }
 315
 316                 ret = fdt_set_usable_memory(blob, start, size, areas);
 317                 if (ret) {
 318                         eprintf("Cannot set usable memory\n");
 319                         return ret;
 320                 }
 321         } else {
 322                 int off;
 323
 324                 off = fdt_node_offset_by_compatible(blob, -1,
 325                                                     "fsl,imx7d-rpmsg");
 326                 if (off > 0)
 327                         fdt_status_disabled(blob, off);
 328         }
 329 #endif
 330 #if defined(CONFIG_FDT_FIXUP_PARTITIONS)
 331         static const struct node_info nodes[] = {
 332                 { "fsl,imx7d-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
 333                 { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
 334         };
 335
 336         /* Update partition nodes using info from mtdparts env var */
 337         puts("   Updating MTD partitions...\n");
 338         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
 339 #endif
 340
 341         return ft_common_board_setup(blob, bd);
 342 }
 343 #endif
 344
 345 #ifdef CONFIG_USB_EHCI_MX7
 346 static iomux_v3_cfg_t const usb_otg2_pads[] = {
 347         MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
 348 };
 349
 350 int board_ehci_hcd_init(int port)
 351 {
 352         switch (port) {
 353         case 0:
 354                 break;
 355         case 1:
 356                 if (is_cpu_type(MXC_CPU_MX7S))
 357                         return -ENODEV;
 358
 359                 imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
 360                                                  ARRAY_SIZE(usb_otg2_pads));
 361                 break;
 362         default:
 363                 return -EINVAL;
 364         }
 365         return 0;
 366 }
 367
 368 int board_usb_phy_mode(int port)
 369 {
 370         switch (port) {
 371         case 0:
 372                 if (gpio_get_value(USB_CDET_GPIO))
 373                         return USB_INIT_DEVICE;
 374                 else
 375                         return USB_INIT_HOST;
 376         case 1:
 377         default:
 378                 return USB_INIT_HOST;
 379         }
 380 }
 381 #endif