2 * Copyright (C) 2016 Toradex AG
4 * SPDX-License-Identifier: GPL-2.0+
7 #include <asm/arch/clock.h>
8 #include <asm/arch/crm_regs.h>
9 #include <asm/arch/imx-regs.h>
10 #include <asm/arch/mx7-pins.h>
11 #include <asm/arch/sys_proto.h>
13 #include <asm/imx-common/boot_mode.h>
14 #include <asm/imx-common/iomux-v3.h>
18 #include <dm/platform_data/serial_mxc.h>
19 #include <fsl_esdhc.h>
20 #include <linux/sizes.h>
24 #include <usb/ehci-ci.h>
26 DECLARE_GLOBAL_DATA_PTR;
28 #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
29 PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
31 #define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
32 PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
34 #define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
35 #define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM)
37 #define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
39 #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
40 PAD_CTL_DSE_3P3V_49OHM)
42 #define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
44 #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
48 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
53 static iomux_v3_cfg_t const uart1_pads[] = {
54 MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
55 MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
56 MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
57 MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
60 static iomux_v3_cfg_t const usdhc1_pads[] = {
61 MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
62 MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
63 MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
64 MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
65 MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
66 MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
68 MX7D_PAD_GPIO1_IO00__GPIO1_IO0 | MUX_PAD_CTRL(NO_PAD_CTRL),
71 #ifdef CONFIG_NAND_MXS
72 static iomux_v3_cfg_t const gpmi_pads[] = {
73 MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
74 MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
75 MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
76 MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
77 MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
78 MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
79 MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
80 MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
81 MX7D_PAD_SD3_CLK__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
82 MX7D_PAD_SD3_CMD__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
83 MX7D_PAD_SD3_STROBE__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
84 MX7D_PAD_SD3_RESET_B__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
85 MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
86 MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
87 MX7D_PAD_SAI1_TX_DATA__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
90 static void setup_gpmi_nand(void)
92 imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
94 /* NAND_USDHC_BUS_CLK is set in rom */
99 static iomux_v3_cfg_t const usdhc3_emmc_pads[] = {
100 MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
101 MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
102 MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
103 MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
104 MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
105 MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
106 MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
107 MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
108 MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
109 MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
110 MX7D_PAD_SD3_STROBE__SD3_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL),
112 MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
115 #ifdef CONFIG_VIDEO_MXS
116 static iomux_v3_cfg_t const lcd_pads[] = {
117 MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
118 MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
119 MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
120 MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
121 MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
122 MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
123 MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
124 MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
125 MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
126 MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
127 MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
128 MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
129 MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
130 MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
131 MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
132 MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
133 MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
134 MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
135 MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
136 MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
137 MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
138 MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
141 static iomux_v3_cfg_t const backlight_pads[] = {
143 MX7D_PAD_SD1_WP__GPIO5_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL),
144 /* Backlight PWM<A> (multiplexed pin) */
145 MX7D_PAD_GPIO1_IO08__GPIO1_IO8 | MUX_PAD_CTRL(NO_PAD_CTRL),
146 MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
149 #define GPIO_BL_ON IMX_GPIO_NR(5, 1)
150 #define GPIO_PWM_A IMX_GPIO_NR(1, 8)
152 static int setup_lcd(void)
154 imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
156 imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads));
159 gpio_request(GPIO_BL_ON, "BL_ON");
160 gpio_direction_output(GPIO_BL_ON, 1);
162 /* Set PWM<A> to full brightness (assuming inversed polarity) */
163 gpio_request(GPIO_PWM_A, "PWM<A>");
164 gpio_direction_output(GPIO_PWM_A, 0);
170 #ifdef CONFIG_FEC_MXC
171 static iomux_v3_cfg_t const fec1_pads[] = {
172 #ifndef CONFIG_COLIBRI_IMX7_EXT_PHYCLK
173 MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 | MUX_PAD_CTRL(ENET_PAD_CTRL) | MUX_MODE_SION,
175 MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
177 MX7D_PAD_SD2_CD_B__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
178 MX7D_PAD_SD2_WP__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
179 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
180 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
181 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
182 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
183 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
184 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
185 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
188 static void setup_iomux_fec(void)
190 imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
194 static void setup_iomux_uart(void)
196 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
199 #ifdef CONFIG_FSL_ESDHC
201 #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 0)
203 static struct fsl_esdhc_cfg usdhc_cfg[] = {
204 {USDHC1_BASE_ADDR, 0, 4},
207 int board_mmc_getcd(struct mmc *mmc)
209 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
212 switch (cfg->esdhc_base) {
213 case USDHC1_BASE_ADDR:
214 ret = !gpio_get_value(USDHC1_CD_GPIO);
221 int board_mmc_init(bd_t *bis)
225 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
228 imx_iomux_v3_setup_multiple_pads(
229 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
230 gpio_request(USDHC1_CD_GPIO, "usdhc1_cd");
231 gpio_direction_input(USDHC1_CD_GPIO);
232 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
235 printf("Warning: you configured more USDHC controllers"
236 "(%d) than supported by the board\n", i + 1);
240 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
249 #ifdef CONFIG_FEC_MXC
250 int board_eth_init(bd_t *bis)
256 ret = fecmxc_initialize_multi(bis, 0,
257 CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
259 printf("FEC1 MXC: %s:failed\n", __func__);
264 static int setup_fec(void)
266 struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
267 = (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
269 #ifndef CONFIG_COLIBRI_IMX7_EXT_PHYCLK
271 * Use 50M anatop REF_CLK1 for ENET1, clear gpr1[13], set gpr1[17]
272 * and output it on the pin
274 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
275 IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK,
276 IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK);
278 /* Use 50M external CLK for ENET1, set gpr1[13], clear gpr1[17] */
279 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
280 IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK,
281 IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK);
284 return set_clk_enet(ENET_50MHz);
287 int board_phy_config(struct phy_device *phydev)
289 if (phydev->drv->config)
290 phydev->drv->config(phydev);
295 int board_early_init_f(void)
304 /* address of boot parameters */
305 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
307 #ifdef CONFIG_FEC_MXC
311 #ifdef CONFIG_NAND_MXS
315 #ifdef CONFIG_VIDEO_MXS
322 #ifdef CONFIG_CMD_BMODE
323 static const struct boot_mode board_boot_modes[] = {
324 /* 4 bit bus width */
325 {"nand", MAKE_CFGVAL(0x40, 0x34, 0x00, 0x00)},
326 {"sd1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)},
331 int board_late_init(void)
333 #ifdef CONFIG_CMD_BMODE
334 add_board_boot_modes(board_boot_modes);
342 printf("Model: Toradex Colibri iMX7%c\n",
343 is_cpu_type(MXC_CPU_MX7D) ? 'D' : 'S');
348 #ifdef CONFIG_USB_EHCI_MX7
349 static iomux_v3_cfg_t const usb_otg2_pads[] = {
350 MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
353 int board_ehci_hcd_init(int port)
359 if (is_cpu_type(MXC_CPU_MX7S))
362 imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
363 ARRAY_SIZE(usb_otg2_pads));
372 static struct mxc_serial_platdata mxc_serial_plat = {
373 .reg = (struct mxc_uart *)UART1_IPS_BASE_ADDR,
377 U_BOOT_DEVICE(mxc_serial) = {
378 .name = "serial_mxc",
379 .platdata = &mxc_serial_plat,