2 * Copyright (C) 2016 Toradex AG
4 * SPDX-License-Identifier: GPL-2.0+
7 #include <asm/arch/clock.h>
8 #include <asm/arch/crm_regs.h>
9 #include <asm/arch/imx-regs.h>
10 #include <asm/arch/mx7-pins.h>
11 #include <asm/arch/sys_proto.h>
13 #include <asm/imx-common/boot_mode.h>
14 #include <asm/imx-common/iomux-v3.h>
18 #include <dm/platform_data/serial_mxc.h>
19 #include <fdt_support.h>
20 #include <fsl_esdhc.h>
21 #include <jffs2/load_kernel.h>
22 #include <linux/sizes.h>
27 #include <power/pmic.h>
28 #include <power/rn5t567_pmic.h>
30 #include <usb/ehci-ci.h>
31 #include "../common/tdx-common.h"
33 DECLARE_GLOBAL_DATA_PTR;
35 #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
36 PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
38 #define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
39 PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
41 #define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
42 #define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM)
44 #define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
46 #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
47 PAD_CTL_DSE_3P3V_49OHM)
49 #define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
51 #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
53 #define USB_CDET_GPIO IMX_GPIO_NR(7, 14)
57 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
62 static iomux_v3_cfg_t const uart1_pads[] = {
63 MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
64 MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
65 MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
66 MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
69 static iomux_v3_cfg_t const usdhc1_pads[] = {
70 MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
71 MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
72 MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
73 MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
74 MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
75 MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
77 MX7D_PAD_GPIO1_IO00__GPIO1_IO0 | MUX_PAD_CTRL(NO_PAD_CTRL),
80 #ifdef CONFIG_USB_EHCI_MX7
81 static iomux_v3_cfg_t const usb_cdet_pads[] = {
82 MX7D_PAD_ENET1_CRS__GPIO7_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
86 #ifdef CONFIG_NAND_MXS
87 static iomux_v3_cfg_t const gpmi_pads[] = {
88 MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
89 MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
90 MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
91 MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
92 MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
93 MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
94 MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
95 MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
96 MX7D_PAD_SD3_CLK__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
97 MX7D_PAD_SD3_CMD__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
98 MX7D_PAD_SD3_STROBE__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
99 MX7D_PAD_SD3_RESET_B__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
100 MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
101 MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
102 MX7D_PAD_SAI1_TX_DATA__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
105 static void setup_gpmi_nand(void)
107 imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
109 /* NAND_USDHC_BUS_CLK is set in rom */
114 static iomux_v3_cfg_t const usdhc3_emmc_pads[] = {
115 MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
116 MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
117 MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
118 MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
119 MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
120 MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
121 MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
122 MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
123 MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
124 MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
125 MX7D_PAD_SD3_STROBE__SD3_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL),
127 MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
130 #ifdef CONFIG_VIDEO_MXS
131 static iomux_v3_cfg_t const lcd_pads[] = {
132 MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
133 MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
134 MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
135 MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
136 MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
137 MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
138 MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
139 MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
140 MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
141 MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
142 MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
143 MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
144 MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
145 MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
146 MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
147 MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
148 MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
149 MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
150 MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
151 MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
152 MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
153 MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
156 static iomux_v3_cfg_t const backlight_pads[] = {
158 MX7D_PAD_SD1_WP__GPIO5_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL),
159 /* Backlight PWM<A> (multiplexed pin) */
160 MX7D_PAD_GPIO1_IO08__GPIO1_IO8 | MUX_PAD_CTRL(NO_PAD_CTRL),
161 MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
164 #define GPIO_BL_ON IMX_GPIO_NR(5, 1)
165 #define GPIO_PWM_A IMX_GPIO_NR(1, 8)
167 static int setup_lcd(void)
169 imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
171 imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads));
174 gpio_request(GPIO_BL_ON, "BL_ON");
175 gpio_direction_output(GPIO_BL_ON, 1);
177 /* Set PWM<A> to full brightness (assuming inversed polarity) */
178 gpio_request(GPIO_PWM_A, "PWM<A>");
179 gpio_direction_output(GPIO_PWM_A, 0);
185 #ifdef CONFIG_FEC_MXC
186 static iomux_v3_cfg_t const fec1_pads[] = {
187 #ifndef CONFIG_COLIBRI_IMX7_EXT_PHYCLK
188 MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 | MUX_PAD_CTRL(ENET_PAD_CTRL) | MUX_MODE_SION,
190 MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
192 MX7D_PAD_SD2_CD_B__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
193 MX7D_PAD_SD2_WP__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
194 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
195 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
196 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
197 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
198 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
199 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
200 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
203 static void setup_iomux_fec(void)
205 imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
209 static void setup_iomux_uart(void)
211 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
214 #ifdef CONFIG_FSL_ESDHC
216 #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 0)
218 static struct fsl_esdhc_cfg usdhc_cfg[] = {
219 {USDHC1_BASE_ADDR, 0, 4},
222 int board_mmc_getcd(struct mmc *mmc)
224 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
227 switch (cfg->esdhc_base) {
228 case USDHC1_BASE_ADDR:
229 ret = !gpio_get_value(USDHC1_CD_GPIO);
236 int board_mmc_init(bd_t *bis)
240 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
243 imx_iomux_v3_setup_multiple_pads(
244 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
245 gpio_request(USDHC1_CD_GPIO, "usdhc1_cd");
246 gpio_direction_input(USDHC1_CD_GPIO);
247 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
250 printf("Warning: you configured more USDHC controllers"
251 "(%d) than supported by the board\n", i + 1);
255 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
264 #ifdef CONFIG_FEC_MXC
265 int board_eth_init(bd_t *bis)
271 ret = fecmxc_initialize_multi(bis, 0,
272 CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
274 printf("FEC1 MXC: %s:failed\n", __func__);
279 static int setup_fec(void)
281 struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
282 = (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
284 #ifndef CONFIG_COLIBRI_IMX7_EXT_PHYCLK
286 * Use 50M anatop REF_CLK1 for ENET1, clear gpr1[13], set gpr1[17]
287 * and output it on the pin
289 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
290 IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK,
291 IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK);
293 /* Use 50M external CLK for ENET1, set gpr1[13], clear gpr1[17] */
294 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
295 IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK,
296 IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK);
299 return set_clk_enet(ENET_50MHz);
302 int board_phy_config(struct phy_device *phydev)
304 if (phydev->drv->config)
305 phydev->drv->config(phydev);
310 int board_early_init_f(void)
319 /* address of boot parameters */
320 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
322 #ifdef CONFIG_FEC_MXC
326 #ifdef CONFIG_NAND_MXS
330 #ifdef CONFIG_VIDEO_MXS
334 #ifdef CONFIG_USB_EHCI_MX7
335 imx_iomux_v3_setup_multiple_pads(usb_cdet_pads, ARRAY_SIZE(usb_cdet_pads));
336 gpio_request(USB_CDET_GPIO, "usb-cdet-gpio");
342 #ifdef CONFIG_CMD_BMODE
343 static const struct boot_mode board_boot_modes[] = {
344 /* 4 bit bus width */
345 {"nand", MAKE_CFGVAL(0x40, 0x34, 0x00, 0x00)},
346 {"sd1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)},
351 int board_late_init(void)
353 #ifdef CONFIG_CMD_BMODE
354 add_board_boot_modes(board_boot_modes);
360 #ifdef CONFIG_DM_PMIC
361 int power_init_board(void)
368 ret = pmic_get("rn5t567", &dev);
371 ver = pmic_reg_read(dev, RN5T567_LSIVER);
372 reg = pmic_reg_read(dev, RN5T567_OTPVER);
374 printf("PMIC: RN5T567 LSIVER=0x%02x OTPVER=0x%02x\n", ver, reg);
376 /* set judge and press timer of N_OE to minimal values */
377 pmic_clrsetbits(dev, RN5T567_NOETIMSETCNT, 0x7, 0);
379 /* configure sleep slot for 3.3V Ethernet */
380 reg = pmic_reg_read(dev, RN5T567_LDO1_SLOT);
381 reg = (reg & 0xf0) | reg >> 4;
382 pmic_reg_write(dev, RN5T567_LDO1_SLOT, reg);
384 /* disable DCDC2 discharge to avoid backfeeding through VFB2 */
385 pmic_clrsetbits(dev, RN5T567_DC2CTL, 0x2, 0);
387 /* configure sleep slot for ARM rail */
388 reg = pmic_reg_read(dev, RN5T567_DC2_SLOT);
389 reg = (reg & 0xf0) | reg >> 4;
390 pmic_reg_write(dev, RN5T567_DC2_SLOT, reg);
392 /* disable LDO2 discharge to avoid backfeeding from +V3.3_SD */
393 pmic_clrsetbits(dev, RN5T567_LDODIS1, 0x2, 0);
398 void reset_cpu(ulong addr)
402 pmic_get("rn5t567", &dev);
404 /* Use PMIC to reset, set REPWRTIM to 0 and REPWRON to 1 */
405 pmic_reg_write(dev, RN5T567_REPCNT, 0x1);
406 pmic_reg_write(dev, RN5T567_SLPCNT, 0x1);
409 * Re-power factor detection on PMIC side is not instant. 1ms
410 * proved to be enough time until reset takes effect.
418 printf("Model: Toradex Colibri iMX7%c\n",
419 is_cpu_type(MXC_CPU_MX7D) ? 'D' : 'S');
424 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
425 int ft_board_setup(void *blob, bd_t *bd)
427 #if defined(CONFIG_FDT_FIXUP_PARTITIONS)
428 static struct node_info nodes[] = {
429 { "fsl,imx7d-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
432 /* Update partition nodes using info from mtdparts env var */
433 puts(" Updating MTD partitions...\n");
434 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
437 return ft_common_board_setup(blob, bd);
441 #ifdef CONFIG_USB_EHCI_MX7
442 static iomux_v3_cfg_t const usb_otg2_pads[] = {
443 MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
446 int board_ehci_hcd_init(int port)
452 if (is_cpu_type(MXC_CPU_MX7S))
455 imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
456 ARRAY_SIZE(usb_otg2_pads));
464 int board_usb_phy_mode(int port)
468 if (gpio_get_value(USB_CDET_GPIO))
469 return USB_INIT_DEVICE;
471 return USB_INIT_HOST;
474 return USB_INIT_HOST;