board/toradex/colibri_imx6/pf0100.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2014-2019, Toradex AG
   4  */
   5
   6 /*
   7  * Helpers for Freescale PMIC PF0100
   8 */
   9
  10 #ifndef PF0100_H_
  11 #define PF0100_H_
  12
  13 /* bit definitions */
  14 #define PFUZE100_BIT_0                  (0x01 << 0)
  15 #define PFUZE100_BIT_1                  (0x01 << 1)
  16 #define PFUZE100_BIT_2                  (0x01 << 2)
  17 #define PFUZE100_BIT_3                  (0x01 << 3)
  18 #define PFUZE100_BIT_4                  (0x01 << 4)
  19 #define PFUZE100_BIT_5                  (0x01 << 5)
  20 #define PFUZE100_BIT_6                  (0x01 << 6)
  21 #define PFUZE100_BIT_7                  (0x01 << 7)
  22
  23 /* 7-bit I2C bus slave address */
  24 #define PFUZE100_I2C_ADDR               (0x08)
  25 /* Register Addresses */
  26 #define PFUZE100_DEVICEID               (0x0)
  27 #define PFUZE100_REVID                  (0x3)
  28 #define PFUZE100_INTSTAT3               (0xe)
  29 #define PFUZE100_BIT_OTP_ECCI           PFUZE100_BIT_7
  30 #define PFUZE100_SW1AMODE               (0x23)
  31 #define PFUZE100_SW1ACON                36
  32 #define PFUZE100_SW1ACON_SPEED_VAL      (0x1<<6)        /*default */
  33 #define PFUZE100_SW1ACON_SPEED_M        (0x3<<6)
  34 #define PFUZE100_SW1CCON                49
  35 #define PFUZE100_SW1CCON_SPEED_VAL      (0x1<<6)        /*default */
  36 #define PFUZE100_SW1CCON_SPEED_M        (0x3<<6)
  37 #define PFUZE100_SW1AVOL                32
  38 #define PFUZE100_SW1AVOL_VSEL_M         (0x3f<<0)
  39 #define PFUZE100_SW1CVOL                46
  40 #define PFUZE100_SW1CVOL_VSEL_M         (0x3f<<0)
  41 #define PFUZE100_VGEN1CTL               (0x6c)
  42 #define PFUZE100_VGEN1_VAL              (0x30 + 0x08) /* Always ON, 1.2V */
  43 #define PFUZE100_SWBSTCTL               (0x66)
  44 /* Always ON, Auto Switching Mode, 5.0V */
  45 #define PFUZE100_SWBST_VAL              (0x40 + 0x08 + 0x00)
  46
  47 /* chooses the extended page (registers 0x80..0xff) */
  48 #define PFUZE100_PAGE_REGISTER          0x7f
  49 #define PFUZE100_PAGE_REGISTER_PAGE_M   (0x1f << 0)
  50 #define PFUZE100_PAGE_REGISTER_PAGE1    (0x01 & PFUZE100_PAGE_REGISTER_PAGE_M)
  51 #define PFUZE100_PAGE_REGISTER_PAGE2    (0x02 & PFUZE100_PAGE_REGISTER_PAGE_M)
  52
  53 /* extended page 1 */
  54 #define PFUZE100_OTP_ECC_SE1            0x8a
  55 #define PFUZE100_BIT_ECC1_SE            PFUZE100_BIT_0
  56 #define PFUZE100_BIT_ECC2_SE            PFUZE100_BIT_1
  57 #define PFUZE100_BIT_ECC3_SE            PFUZE100_BIT_2
  58 #define PFUZE100_BIT_ECC4_SE            PFUZE100_BIT_3
  59 #define PFUZE100_BIT_ECC5_SE            PFUZE100_BIT_4
  60 #define PFUZE100_BITS_ECC_SE1           ((PFUZE100_BIT_ECC1_SE) | \
  61                                         (PFUZE100_BIT_ECC2_SE) | \
  62                                         (PFUZE100_BIT_ECC3_SE) | \
  63                                         (PFUZE100_BIT_ECC4_SE) | \
  64                                         (PFUZE100_BIT_ECC5_SE))
  65 #define PFUZE100_OTP_ECC_SE2            0x8b
  66 #define PFUZE100_BIT_ECC6_SE            PFUZE100_BIT_0
  67 #define PFUZE100_BIT_ECC7_SE            PFUZE100_BIT_1
  68 #define PFUZE100_BIT_ECC8_SE            PFUZE100_BIT_2
  69 #define PFUZE100_BIT_ECC9_SE            PFUZE100_BIT_3
  70 #define PFUZE100_BIT_ECC10_SE           PFUZE100_BIT_4
  71 #define PFUZE100_BITS_ECC_SE2           ((PFUZE100_BIT_ECC6_SE) | \
  72                                         (PFUZE100_BIT_ECC7_SE) | \
  73                                         (PFUZE100_BIT_ECC8_SE) | \
  74                                         (PFUZE100_BIT_ECC9_SE) | \
  75                                         (PFUZE100_BIT_ECC10_SE))
  76 #define PFUZE100_OTP_ECC_DE1            0x8c
  77 #define PFUZE100_BIT_ECC1_DE            PFUZE100_BIT_0
  78 #define PFUZE100_BIT_ECC2_DE            PFUZE100_BIT_1
  79 #define PFUZE100_BIT_ECC3_DE            PFUZE100_BIT_2
  80 #define PFUZE100_BIT_ECC4_DE            PFUZE100_BIT_3
  81 #define PFUZE100_BIT_ECC5_DE            PFUZE100_BIT_4
  82 #define PFUZE100_BITS_ECC_DE1           ((PFUZE100_BIT_ECC1_DE) | \
  83                                         (PFUZE100_BIT_ECC2_DE) | \
  84                                         (PFUZE100_BIT_ECC3_DE) | \
  85                                         (PFUZE100_BIT_ECC4_DE) | \
  86                                         (PFUZE100_BIT_ECC5_DE))
  87 #define PFUZE100_OTP_ECC_DE2            0x8d
  88 #define PFUZE100_BIT_ECC6_DE            PFUZE100_BIT_0
  89 #define PFUZE100_BIT_ECC7_DE            PFUZE100_BIT_1
  90 #define PFUZE100_BIT_ECC8_DE            PFUZE100_BIT_2
  91 #define PFUZE100_BIT_ECC9_DE            PFUZE100_BIT_3
  92 #define PFUZE100_BIT_ECC10_DE           PFUZE100_BIT_4
  93 #define PFUZE100_BITS_ECC_DE2           ((PFUZE100_BIT_ECC6_DE) | \
  94                                         (PFUZE100_BIT_ECC7_DE) | \
  95                                         (PFUZE100_BIT_ECC8_DE) | \
  96                                         (PFUZE100_BIT_ECC9_DE) | \
  97                                         (PFUZE100_BIT_ECC10_DE))
  98 #define PFUZE100_FUSE_POR1              0xe4
  99 #define PFUZE100_FUSE_POR2              0xe5
 100 #define PFUZE100_FUSE_POR3              0xe6
 101 #define PFUZE100_FUSE_POR_M             (0x1 << 1)
 102
 103 /* output some informational messages, return the number FUSE_POR=1 */
 104 /* i.e. 0: unprogrammed, 3: programmed, other: undefined prog. state */
 105 unsigned pmic_init(void);
 106
 107 #endif /* PF0100_H_ */