board/toradex/colibri_imx6/colibri_imx6.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
   4  * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
   5  * Copyright (C) 2014-2019, Toradex AG
   6  * copied from nitrogen6x
   7  */
   8
   9 #include <common.h>
  10 #include <dm.h>
  11
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/crm_regs.h>
  14 #include <asm/arch/imx-regs.h>
  15 #include <asm/arch/mx6-ddr.h>
  16 #include <asm/arch/mx6-pins.h>
  17 #include <asm/arch/mxc_hdmi.h>
  18 #include <asm/arch/sys_proto.h>
  19 #include <asm/bootm.h>
  20 #include <asm/gpio.h>
  21 #include <asm/mach-imx/boot_mode.h>
  22 #include <asm/mach-imx/iomux-v3.h>
  23 #include <asm/mach-imx/sata.h>
  24 #include <asm/mach-imx/video.h>
  25 #include <dm/platform_data/serial_mxc.h>
  26 #include <environment.h>
  27 #include <fsl_esdhc.h>
  28 #include <imx_thermal.h>
  29 #include <micrel.h>
  30 #include <miiphy.h>
  31 #include <netdev.h>
  32
  33 #include "../common/tdx-cfg-block.h"
  34 #ifdef CONFIG_TDX_CMD_IMX_MFGR
  35 #include "pf0100.h"
  36 #endif
  37
  38 DECLARE_GLOBAL_DATA_PTR;
  39
  40 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  41         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  42         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  43
  44 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  45         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm |                 \
  46         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  47
  48 #define USDHC_EMMC_PAD_CTRL (PAD_CTL_PUS_47K_UP |               \
  49         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  50         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  51
  52 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  53         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  54
  55 #define WEAK_PULLUP     (PAD_CTL_PUS_100K_UP |                  \
  56         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  57         PAD_CTL_SRE_SLOW)
  58
  59 #define NO_PULLUP       (                                       \
  60         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  61         PAD_CTL_SRE_SLOW)
  62
  63 #define WEAK_PULLDOWN   (PAD_CTL_PUS_100K_DOWN |                \
  64         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  65         PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
  66
  67 #define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST)
  68
  69 int dram_init(void)
  70 {
  71         /* use the DDR controllers configured size */
  72         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  73                                     (ulong)imx_ddr_size());
  74
  75         return 0;
  76 }
  77
  78 /* Colibri UARTA */
  79 iomux_v3_cfg_t const uart1_pads[] = {
  80         MX6_PAD_CSI0_DAT10__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  81         MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  82 };
  83
  84 #if defined(CONFIG_FSL_ESDHC) && defined(CONFIG_SPL_BUILD)
  85 /* Colibri MMC */
  86 iomux_v3_cfg_t const usdhc1_pads[] = {
  87         MX6_PAD_SD1_CLK__SD1_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  88         MX6_PAD_SD1_CMD__SD1_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  89         MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  90         MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  91         MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  92         MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  93         MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
  94 #       define GPIO_MMC_CD IMX_GPIO_NR(2, 5)
  95 };
  96
  97 /* eMMC */
  98 iomux_v3_cfg_t const usdhc3_pads[] = {
  99         MX6_PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 100         MX6_PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 101         MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 102         MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 103         MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 104         MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 105         MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 106         MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 107         MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 108         MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 109         MX6_PAD_SD3_RST__SD3_RESET  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 110 };
 111 #endif /* CONFIG_FSL_ESDHC & CONFIG_SPL_BUILD */
 112
 113 iomux_v3_cfg_t const enet_pads[] = {
 114         MX6_PAD_ENET_MDC__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
 115         MX6_PAD_ENET_MDIO__ENET_MDIO            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 116         MX6_PAD_ENET_RXD0__ENET_RX_DATA0        | MUX_PAD_CTRL(ENET_PAD_CTRL),
 117         MX6_PAD_ENET_RXD1__ENET_RX_DATA1        | MUX_PAD_CTRL(ENET_PAD_CTRL),
 118         MX6_PAD_ENET_RX_ER__ENET_RX_ER          | MUX_PAD_CTRL(ENET_PAD_CTRL),
 119         MX6_PAD_ENET_TX_EN__ENET_TX_EN          | MUX_PAD_CTRL(ENET_PAD_CTRL),
 120         MX6_PAD_ENET_TXD0__ENET_TX_DATA0        | MUX_PAD_CTRL(ENET_PAD_CTRL),
 121         MX6_PAD_ENET_TXD1__ENET_TX_DATA1        | MUX_PAD_CTRL(ENET_PAD_CTRL),
 122         MX6_PAD_ENET_CRS_DV__ENET_RX_EN         | MUX_PAD_CTRL(ENET_PAD_CTRL),
 123         MX6_PAD_GPIO_16__ENET_REF_CLK           | MUX_PAD_CTRL(ENET_PAD_CTRL),
 124 };
 125
 126 static void setup_iomux_enet(void)
 127 {
 128         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
 129 }
 130
 131 /* mux auxiliary pins to GPIO, so they can be used from the U-Boot cmdline */
 132 iomux_v3_cfg_t const gpio_pads[] = {
 133         /* ADDRESS[17:18] [25] used as GPIO */
 134         MX6_PAD_KEY_ROW2__GPIO4_IO11    | MUX_PAD_CTRL(WEAK_PULLUP) |
 135                                           MUX_MODE_SION,
 136         MX6_PAD_KEY_COL2__GPIO4_IO10    | MUX_PAD_CTRL(WEAK_PULLUP) |
 137                                           MUX_MODE_SION,
 138         MX6_PAD_NANDF_D1__GPIO2_IO01    | MUX_PAD_CTRL(WEAK_PULLUP) |
 139                                           MUX_MODE_SION,
 140         /* ADDRESS[19:24] used as GPIO */
 141         MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(WEAK_PULLUP) |
 142                                           MUX_MODE_SION,
 143         MX6_PAD_DISP0_DAT22__GPIO5_IO16 | MUX_PAD_CTRL(WEAK_PULLUP) |
 144                                           MUX_MODE_SION,
 145         MX6_PAD_DISP0_DAT21__GPIO5_IO15 | MUX_PAD_CTRL(WEAK_PULLUP) |
 146                                           MUX_MODE_SION,
 147         MX6_PAD_DISP0_DAT20__GPIO5_IO14 | MUX_PAD_CTRL(WEAK_PULLUP) |
 148                                           MUX_MODE_SION,
 149         MX6_PAD_DISP0_DAT19__GPIO5_IO13 | MUX_PAD_CTRL(WEAK_PULLUP) |
 150                                           MUX_MODE_SION,
 151         MX6_PAD_DISP0_DAT18__GPIO5_IO12 | MUX_PAD_CTRL(WEAK_PULLUP) |
 152                                           MUX_MODE_SION,
 153         /* DATA[16:29] [31]      used as GPIO */
 154         MX6_PAD_EIM_LBA__GPIO2_IO27     | MUX_PAD_CTRL(WEAK_PULLUP) |
 155                                           MUX_MODE_SION,
 156         MX6_PAD_EIM_BCLK__GPIO6_IO31    | MUX_PAD_CTRL(WEAK_PULLUP) |
 157                                           MUX_MODE_SION,
 158         MX6_PAD_NANDF_CS3__GPIO6_IO16   | MUX_PAD_CTRL(WEAK_PULLUP) |
 159                                           MUX_MODE_SION,
 160         MX6_PAD_NANDF_CS1__GPIO6_IO14   | MUX_PAD_CTRL(WEAK_PULLUP) |
 161                                           MUX_MODE_SION,
 162         MX6_PAD_NANDF_RB0__GPIO6_IO10   | MUX_PAD_CTRL(WEAK_PULLUP) |
 163                                           MUX_MODE_SION,
 164         MX6_PAD_NANDF_ALE__GPIO6_IO08   | MUX_PAD_CTRL(WEAK_PULLUP) |
 165                                           MUX_MODE_SION,
 166         MX6_PAD_NANDF_WP_B__GPIO6_IO09  | MUX_PAD_CTRL(WEAK_PULLUP) |
 167                                           MUX_MODE_SION,
 168         MX6_PAD_NANDF_CS0__GPIO6_IO11   | MUX_PAD_CTRL(WEAK_PULLUP) |
 169                                           MUX_MODE_SION,
 170         MX6_PAD_NANDF_CLE__GPIO6_IO07   | MUX_PAD_CTRL(WEAK_PULLUP) |
 171                                           MUX_MODE_SION,
 172         MX6_PAD_GPIO_19__GPIO4_IO05     | MUX_PAD_CTRL(WEAK_PULLUP) |
 173                                           MUX_MODE_SION,
 174         MX6_PAD_CSI0_MCLK__GPIO5_IO19   | MUX_PAD_CTRL(WEAK_PULLUP) |
 175                                           MUX_MODE_SION,
 176         MX6_PAD_CSI0_PIXCLK__GPIO5_IO18 | MUX_PAD_CTRL(WEAK_PULLUP) |
 177                                           MUX_MODE_SION,
 178         MX6_PAD_GPIO_4__GPIO1_IO04      | MUX_PAD_CTRL(WEAK_PULLUP) |
 179                                           MUX_MODE_SION,
 180         MX6_PAD_GPIO_5__GPIO1_IO05      | MUX_PAD_CTRL(WEAK_PULLUP) |
 181                                           MUX_MODE_SION,
 182         MX6_PAD_GPIO_2__GPIO1_IO02      | MUX_PAD_CTRL(WEAK_PULLUP) |
 183                                           MUX_MODE_SION,
 184         /* DQM[0:3]      used as GPIO */
 185         MX6_PAD_EIM_EB0__GPIO2_IO28     | MUX_PAD_CTRL(WEAK_PULLUP) |
 186                                           MUX_MODE_SION,
 187         MX6_PAD_EIM_EB1__GPIO2_IO29     | MUX_PAD_CTRL(WEAK_PULLUP) |
 188                                           MUX_MODE_SION,
 189         MX6_PAD_SD2_DAT2__GPIO1_IO13    | MUX_PAD_CTRL(WEAK_PULLUP) |
 190                                           MUX_MODE_SION,
 191         MX6_PAD_NANDF_D0__GPIO2_IO00    | MUX_PAD_CTRL(WEAK_PULLUP) |
 192                                           MUX_MODE_SION,
 193         /* RDY  used as GPIO */
 194         MX6_PAD_EIM_WAIT__GPIO5_IO00    | MUX_PAD_CTRL(WEAK_PULLUP) |
 195                                           MUX_MODE_SION,
 196         /* ADDRESS[16] DATA[30]  used as GPIO */
 197         MX6_PAD_KEY_ROW4__GPIO4_IO15    | MUX_PAD_CTRL(WEAK_PULLDOWN) |
 198                                           MUX_MODE_SION,
 199         MX6_PAD_KEY_COL4__GPIO4_IO14    | MUX_PAD_CTRL(WEAK_PULLUP) |
 200                                           MUX_MODE_SION,
 201         /* CSI pins used as GPIO */
 202         MX6_PAD_EIM_A24__GPIO5_IO04     | MUX_PAD_CTRL(WEAK_PULLUP) |
 203                                           MUX_MODE_SION,
 204         MX6_PAD_SD2_CMD__GPIO1_IO11     | MUX_PAD_CTRL(WEAK_PULLUP) |
 205                                           MUX_MODE_SION,
 206         MX6_PAD_NANDF_CS2__GPIO6_IO15   | MUX_PAD_CTRL(WEAK_PULLUP) |
 207                                           MUX_MODE_SION,
 208         MX6_PAD_EIM_D18__GPIO3_IO18     | MUX_PAD_CTRL(WEAK_PULLUP) |
 209                                           MUX_MODE_SION,
 210         MX6_PAD_EIM_A19__GPIO2_IO19     | MUX_PAD_CTRL(WEAK_PULLUP) |
 211                                           MUX_MODE_SION,
 212         MX6_PAD_EIM_D29__GPIO3_IO29     | MUX_PAD_CTRL(WEAK_PULLDOWN) |
 213                                           MUX_MODE_SION,
 214         MX6_PAD_EIM_A23__GPIO6_IO06     | MUX_PAD_CTRL(WEAK_PULLUP) |
 215                                           MUX_MODE_SION,
 216         MX6_PAD_EIM_A20__GPIO2_IO18     | MUX_PAD_CTRL(WEAK_PULLUP) |
 217                                           MUX_MODE_SION,
 218         MX6_PAD_EIM_A17__GPIO2_IO21     | MUX_PAD_CTRL(WEAK_PULLUP) |
 219                                           MUX_MODE_SION,
 220         MX6_PAD_EIM_A18__GPIO2_IO20     | MUX_PAD_CTRL(WEAK_PULLUP) |
 221                                           MUX_MODE_SION,
 222         MX6_PAD_EIM_EB3__GPIO2_IO31     | MUX_PAD_CTRL(WEAK_PULLUP) |
 223                                           MUX_MODE_SION,
 224         MX6_PAD_EIM_D17__GPIO3_IO17     | MUX_PAD_CTRL(WEAK_PULLUP) |
 225                                           MUX_MODE_SION,
 226         MX6_PAD_SD2_DAT0__GPIO1_IO15    | MUX_PAD_CTRL(WEAK_PULLUP) |
 227                                           MUX_MODE_SION,
 228         /* GPIO */
 229         MX6_PAD_EIM_D26__GPIO3_IO26     | MUX_PAD_CTRL(WEAK_PULLUP) |
 230                                           MUX_MODE_SION,
 231         MX6_PAD_EIM_D27__GPIO3_IO27     | MUX_PAD_CTRL(WEAK_PULLUP) |
 232                                           MUX_MODE_SION,
 233         MX6_PAD_NANDF_D6__GPIO2_IO06    | MUX_PAD_CTRL(WEAK_PULLUP) |
 234                                           MUX_MODE_SION,
 235         MX6_PAD_NANDF_D3__GPIO2_IO03    | MUX_PAD_CTRL(WEAK_PULLUP) |
 236                                           MUX_MODE_SION,
 237         MX6_PAD_ENET_REF_CLK__GPIO1_IO23 | MUX_PAD_CTRL(WEAK_PULLUP) |
 238                                           MUX_MODE_SION,
 239         MX6_PAD_DI0_PIN4__GPIO4_IO20    | MUX_PAD_CTRL(WEAK_PULLUP) |
 240                                           MUX_MODE_SION,
 241         MX6_PAD_SD4_DAT3__GPIO2_IO11    | MUX_PAD_CTRL(WEAK_PULLUP) |
 242                                           MUX_MODE_SION,
 243         MX6_PAD_NANDF_D4__GPIO2_IO04    | MUX_PAD_CTRL(WEAK_PULLUP) |
 244                                           MUX_MODE_SION,
 245         MX6_PAD_SD4_DAT0__GPIO2_IO08    | MUX_PAD_CTRL(WEAK_PULLUP) |
 246                                           MUX_MODE_SION,
 247         MX6_PAD_GPIO_7__GPIO1_IO07      | MUX_PAD_CTRL(WEAK_PULLUP) |
 248                                           MUX_MODE_SION,
 249         MX6_PAD_GPIO_8__GPIO1_IO08      | MUX_PAD_CTRL(WEAK_PULLUP) |
 250                                           MUX_MODE_SION,
 251         /* USBH_OC */
 252         MX6_PAD_EIM_D30__GPIO3_IO30     | MUX_PAD_CTRL(WEAK_PULLUP),
 253         /* USBC_ID */
 254         MX6_PAD_NANDF_D2__GPIO2_IO02    | MUX_PAD_CTRL(WEAK_PULLUP),
 255         /* USBC_DET */
 256         MX6_PAD_GPIO_17__GPIO7_IO12     | MUX_PAD_CTRL(WEAK_PULLUP),
 257 };
 258
 259 static void setup_iomux_gpio(void)
 260 {
 261         imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
 262 }
 263
 264 iomux_v3_cfg_t const usb_pads[] = {
 265         /* USBH_PEN */
 266         MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
 267 #       define GPIO_USBH_EN IMX_GPIO_NR(3, 31)
 268 };
 269
 270 /*
 271  * UARTs are used in DTE mode, switch the mode on all UARTs before
 272  * any pinmuxing connects a (DCE) output to a transceiver output.
 273  */
 274 #define UCR3            0x88    /* FIFO Control Register */
 275 #define UCR3_RI         BIT(8)  /* RIDELT DTE mode */
 276 #define UCR3_DCD        BIT(9)  /* DCDDELT DTE mode */
 277 #define UFCR            0x90    /* FIFO Control Register */
 278 #define UFCR_DCEDTE     BIT(6)  /* DCE=0 */
 279
 280 static void setup_dtemode_uart(void)
 281 {
 282         setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
 283         setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
 284         setbits_le32((u32 *)(UART3_BASE + UFCR), UFCR_DCEDTE);
 285
 286         clrbits_le32((u32 *)(UART1_BASE + UCR3), UCR3_DCD | UCR3_RI);
 287         clrbits_le32((u32 *)(UART2_BASE + UCR3), UCR3_DCD | UCR3_RI);
 288         clrbits_le32((u32 *)(UART3_BASE + UCR3), UCR3_DCD | UCR3_RI);
 289 }
 290
 291 static void setup_iomux_uart(void)
 292 {
 293         setup_dtemode_uart();
 294         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 295 }
 296
 297 #ifdef CONFIG_USB_EHCI_MX6
 298 int board_ehci_hcd_init(int port)
 299 {
 300         imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
 301         return 0;
 302 }
 303 #endif
 304
 305 #if defined(CONFIG_FSL_ESDHC) && defined(CONFIG_SPL_BUILD)
 306 /* use the following sequence: eMMC, MMC */
 307 struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
 308         {USDHC3_BASE_ADDR},
 309         {USDHC1_BASE_ADDR},
 310 };
 311
 312 int board_mmc_getcd(struct mmc *mmc)
 313 {
 314         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 315         int ret = true; /* default: assume inserted */
 316
 317         switch (cfg->esdhc_base) {
 318         case USDHC1_BASE_ADDR:
 319                 gpio_request(GPIO_MMC_CD, "MMC_CD");
 320                 gpio_direction_input(GPIO_MMC_CD);
 321                 ret = !gpio_get_value(GPIO_MMC_CD);
 322                 break;
 323         }
 324
 325         return ret;
 326 }
 327
 328 int board_mmc_init(bd_t *bis)
 329 {
 330         struct src *psrc = (struct src *)SRC_BASE_ADDR;
 331         unsigned reg = readl(&psrc->sbmr1) >> 11;
 332         /*
 333          * Upon reading BOOT_CFG register the following map is done:
 334          * Bit 11 and 12 of BOOT_CFG register can determine the current
 335          * mmc port
 336          * 0x1                  SD1
 337          * 0x2                  SD2
 338          * 0x3                  SD4
 339          */
 340
 341         switch (reg & 0x3) {
 342         case 0x0:
 343                 imx_iomux_v3_setup_multiple_pads(
 344                         usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
 345                 usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
 346                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 347                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 348                 break;
 349         case 0x2:
 350                 imx_iomux_v3_setup_multiple_pads(
 351                         usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 352                 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
 353                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 354                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 355                 break;
 356         default:
 357                 puts("MMC boot device not available");
 358         }
 359
 360         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 361 }
 362 #endif /* CONFIG_FSL_ESDHC & CONFIG_SPL_BUILD */
 363
 364 int board_phy_config(struct phy_device *phydev)
 365 {
 366         if (phydev->drv->config)
 367                 phydev->drv->config(phydev);
 368
 369         return 0;
 370 }
 371
 372 int board_eth_init(bd_t *bis)
 373 {
 374         struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 375         uint32_t base = IMX_FEC_BASE;
 376         struct mii_dev *bus = NULL;
 377         struct phy_device *phydev = NULL;
 378         int ret;
 379
 380         /* provide the PHY clock from the i.MX 6 */
 381         ret = enable_fec_anatop_clock(0, ENET_50MHZ);
 382         if (ret)
 383                 return ret;
 384
 385         /* set gpr1[ENET_CLK_SEL] */
 386         setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
 387
 388         setup_iomux_enet();
 389
 390 #ifdef CONFIG_FEC_MXC
 391         bus = fec_get_miibus(base, -1);
 392         if (!bus)
 393                 return 0;
 394
 395         /* scan PHY 1..7 */
 396         phydev = phy_find_by_mask(bus, 0xff, PHY_INTERFACE_MODE_RMII);
 397         if (!phydev) {
 398                 free(bus);
 399                 puts("no PHY found\n");
 400                 return 0;
 401         }
 402
 403         phy_reset(phydev);
 404         printf("using PHY at %d\n", phydev->addr);
 405         ret = fec_probe(bis, -1, base, bus, phydev);
 406         if (ret) {
 407                 printf("FEC MXC: %s:failed\n", __func__);
 408                 free(phydev);
 409                 free(bus);
 410         }
 411 #endif /* CONFIG_FEC_MXC */
 412
 413         return 0;
 414 }
 415
 416 static iomux_v3_cfg_t const pwr_intb_pads[] = {
 417         /*
 418          * the bootrom sets the iomux to vselect, potentially connecting
 419          * two outputs. Set this back to GPIO
 420          */
 421         MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)
 422 };
 423
 424 #if defined(CONFIG_VIDEO_IPUV3)
 425
 426 static iomux_v3_cfg_t const backlight_pads[] = {
 427         /* Backlight On */
 428         MX6_PAD_EIM_D26__GPIO3_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
 429 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 26)
 430         /* Backlight PWM, used as GPIO in U-Boot */
 431         MX6_PAD_EIM_A22__GPIO2_IO16  | MUX_PAD_CTRL(NO_PULLUP),
 432         MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL) |
 433                                        MUX_MODE_SION,
 434 #define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 9)
 435 };
 436
 437 static iomux_v3_cfg_t const rgb_pads[] = {
 438         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(OUTPUT_RGB),
 439         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(OUTPUT_RGB),
 440         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(OUTPUT_RGB),
 441         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(OUTPUT_RGB),
 442         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(OUTPUT_RGB),
 443         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(OUTPUT_RGB),
 444         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(OUTPUT_RGB),
 445         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(OUTPUT_RGB),
 446         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(OUTPUT_RGB),
 447         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(OUTPUT_RGB),
 448         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(OUTPUT_RGB),
 449         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(OUTPUT_RGB),
 450         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(OUTPUT_RGB),
 451         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(OUTPUT_RGB),
 452         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(OUTPUT_RGB),
 453         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(OUTPUT_RGB),
 454         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(OUTPUT_RGB),
 455         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(OUTPUT_RGB),
 456         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(OUTPUT_RGB),
 457         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(OUTPUT_RGB),
 458         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(OUTPUT_RGB),
 459         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(OUTPUT_RGB),
 460 };
 461
 462 static void do_enable_hdmi(struct display_info_t const *dev)
 463 {
 464         imx_enable_hdmi_phy();
 465 }
 466
 467 static void enable_rgb(struct display_info_t const *dev)
 468 {
 469         imx_iomux_v3_setup_multiple_pads(
 470                 rgb_pads,
 471                 ARRAY_SIZE(rgb_pads));
 472         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 473         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
 474 }
 475
 476 static int detect_default(struct display_info_t const *dev)
 477 {
 478         (void) dev;
 479         return 1;
 480 }
 481
 482 struct display_info_t const displays[] = {{
 483         .bus    = -1,
 484         .addr   = 0,
 485         .pixfmt = IPU_PIX_FMT_RGB24,
 486         .detect = detect_hdmi,
 487         .enable = do_enable_hdmi,
 488         .mode   = {
 489                 .name           = "HDMI",
 490                 .refresh        = 60,
 491                 .xres           = 1024,
 492                 .yres           = 768,
 493                 .pixclock       = 15385,
 494                 .left_margin    = 220,
 495                 .right_margin   = 40,
 496                 .upper_margin   = 21,
 497                 .lower_margin   = 7,
 498                 .hsync_len      = 60,
 499                 .vsync_len      = 10,
 500                 .sync           = FB_SYNC_EXT,
 501                 .vmode          = FB_VMODE_NONINTERLACED
 502 } }, {
 503         .bus    = -1,
 504         .addr   = 0,
 505         .pixfmt = IPU_PIX_FMT_RGB666,
 506         .detect = detect_default,
 507         .enable = enable_rgb,
 508         .mode   = {
 509                 .name           = "vga-rgb",
 510                 .refresh        = 60,
 511                 .xres           = 640,
 512                 .yres           = 480,
 513                 .pixclock       = 33000,
 514                 .left_margin    = 48,
 515                 .right_margin   = 16,
 516                 .upper_margin   = 31,
 517                 .lower_margin   = 11,
 518                 .hsync_len      = 96,
 519                 .vsync_len      = 2,
 520                 .sync           = 0,
 521                 .vmode          = FB_VMODE_NONINTERLACED
 522 } }, {
 523         .bus    = -1,
 524         .addr   = 0,
 525         .pixfmt = IPU_PIX_FMT_RGB666,
 526         .enable = enable_rgb,
 527         .mode   = {
 528                 .name           = "wvga-rgb",
 529                 .refresh        = 60,
 530                 .xres           = 800,
 531                 .yres           = 480,
 532                 .pixclock       = 25000,
 533                 .left_margin    = 40,
 534                 .right_margin   = 88,
 535                 .upper_margin   = 33,
 536                 .lower_margin   = 10,
 537                 .hsync_len      = 128,
 538                 .vsync_len      = 2,
 539                 .sync           = 0,
 540                 .vmode          = FB_VMODE_NONINTERLACED
 541 } } };
 542 size_t display_count = ARRAY_SIZE(displays);
 543
 544 static void setup_display(void)
 545 {
 546         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 547         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 548         int reg;
 549
 550         enable_ipu_clock();
 551         imx_setup_hdmi();
 552         /* Turn on LDB0,IPU,IPU DI0 clocks */
 553         reg = __raw_readl(&mxc_ccm->CCGR3);
 554         reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
 555         writel(reg, &mxc_ccm->CCGR3);
 556
 557         /* set LDB0, LDB1 clk select to 011/011 */
 558         reg = readl(&mxc_ccm->cs2cdr);
 559         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 560                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 561         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 562               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 563         writel(reg, &mxc_ccm->cs2cdr);
 564
 565         reg = readl(&mxc_ccm->cscmr2);
 566         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 567         writel(reg, &mxc_ccm->cscmr2);
 568
 569         reg = readl(&mxc_ccm->chsccdr);
 570         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 571                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 572         writel(reg, &mxc_ccm->chsccdr);
 573
 574         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 575              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 576              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 577              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 578              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 579              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 580              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 581              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 582              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 583         writel(reg, &iomux->gpr[2]);
 584
 585         reg = readl(&iomux->gpr[3]);
 586         reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
 587                         |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
 588             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 589                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 590         writel(reg, &iomux->gpr[3]);
 591
 592         /* backlight unconditionally on for now */
 593         imx_iomux_v3_setup_multiple_pads(backlight_pads,
 594                                          ARRAY_SIZE(backlight_pads));
 595         /* use 0 for EDT 7", use 1 for LG fullHD panel */
 596         gpio_request(RGB_BACKLIGHTPWM_GP, "PWM<A>");
 597         gpio_request(RGB_BACKLIGHT_GP, "BL_ON");
 598         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
 599         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 600 }
 601
 602 /*
 603  * Backlight off before OS handover
 604  */
 605 void board_preboot_os(void)
 606 {
 607         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 1);
 608         gpio_direction_output(RGB_BACKLIGHT_GP, 0);
 609 }
 610 #endif /* defined(CONFIG_VIDEO_IPUV3) */
 611
 612 int board_early_init_f(void)
 613 {
 614         imx_iomux_v3_setup_multiple_pads(pwr_intb_pads,
 615                                          ARRAY_SIZE(pwr_intb_pads));
 616         setup_iomux_uart();
 617
 618         return 0;
 619 }
 620
 621 /*
 622  * Do not overwrite the console
 623  * Use always serial for U-Boot console
 624  */
 625 int overwrite_console(void)
 626 {
 627         return 1;
 628 }
 629
 630 int board_init(void)
 631 {
 632         /* address of boot parameters */
 633         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 634
 635 #if defined(CONFIG_VIDEO_IPUV3)
 636         setup_display();
 637 #endif
 638
 639 #ifdef CONFIG_TDX_CMD_IMX_MFGR
 640         (void) pmic_init();
 641 #endif
 642
 643 #ifdef CONFIG_SATA
 644         setup_sata();
 645 #endif
 646
 647         setup_iomux_gpio();
 648
 649         return 0;
 650 }
 651
 652 #ifdef CONFIG_BOARD_LATE_INIT
 653 int board_late_init(void)
 654 {
 655 #if defined(CONFIG_REVISION_TAG) && \
 656     defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
 657         char env_str[256];
 658         u32 rev;
 659
 660         rev = get_board_rev();
 661         snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev);
 662         env_set("board_rev", env_str);
 663 #endif
 664
 665         return 0;
 666 }
 667 #endif /* CONFIG_BOARD_LATE_INIT */
 668
 669 int checkboard(void)
 670 {
 671         char it[] = " IT";
 672         int minc, maxc;
 673
 674         switch (get_cpu_temp_grade(&minc, &maxc)) {
 675         case TEMP_AUTOMOTIVE:
 676         case TEMP_INDUSTRIAL:
 677                 break;
 678         case TEMP_EXTCOMMERCIAL:
 679         default:
 680                 it[0] = 0;
 681         };
 682         printf("Model: Toradex Colibri iMX6 %s %sMB%s\n",
 683                is_cpu_type(MXC_CPU_MX6DL) ? "DualLite" : "Solo",
 684                (gd->ram_size == 0x20000000) ? "512" : "256", it);
 685         return 0;
 686 }
 687
 688 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 689 int ft_board_setup(void *blob, bd_t *bd)
 690 {
 691         return ft_common_board_setup(blob, bd);
 692 }
 693 #endif
 694
 695 #ifdef CONFIG_CMD_BMODE
 696 static const struct boot_mode board_boot_modes[] = {
 697         {"mmc", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
 698         {NULL,  0},
 699 };
 700 #endif
 701
 702 int misc_init_r(void)
 703 {
 704 #ifdef CONFIG_CMD_BMODE
 705         add_board_boot_modes(board_boot_modes);
 706 #endif
 707         return 0;
 708 }
 709
 710 #ifdef CONFIG_LDO_BYPASS_CHECK
 711 /* TODO, use external pmic, for now always ldo_enable */
 712 void ldo_mode_set(int ldo_bypass)
 713 {
 714         return;
 715 }
 716 #endif
 717
 718 #ifdef CONFIG_SPL_BUILD
 719 #include <spl.h>
 720 #include <linux/libfdt.h>
 721 #include "asm/arch/mx6dl-ddr.h"
 722 #include "asm/arch/iomux.h"
 723 #include "asm/arch/crm_regs.h"
 724
 725 static int mx6s_dcd_table[] = {
 726 /* ddr-setup.cfg */
 727
 728 MX6_IOM_DRAM_SDQS0, 0x00000030,
 729 MX6_IOM_DRAM_SDQS1, 0x00000030,
 730 MX6_IOM_DRAM_SDQS2, 0x00000030,
 731 MX6_IOM_DRAM_SDQS3, 0x00000030,
 732 MX6_IOM_DRAM_SDQS4, 0x00000030,
 733 MX6_IOM_DRAM_SDQS5, 0x00000030,
 734 MX6_IOM_DRAM_SDQS6, 0x00000030,
 735 MX6_IOM_DRAM_SDQS7, 0x00000030,
 736
 737 MX6_IOM_GRP_B0DS, 0x00000030,
 738 MX6_IOM_GRP_B1DS, 0x00000030,
 739 MX6_IOM_GRP_B2DS, 0x00000030,
 740 MX6_IOM_GRP_B3DS, 0x00000030,
 741 MX6_IOM_GRP_B4DS, 0x00000030,
 742 MX6_IOM_GRP_B5DS, 0x00000030,
 743 MX6_IOM_GRP_B6DS, 0x00000030,
 744 MX6_IOM_GRP_B7DS, 0x00000030,
 745 MX6_IOM_GRP_ADDDS, 0x00000030,
 746 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 747 MX6_IOM_GRP_CTLDS, 0x00000030,
 748
 749 MX6_IOM_DRAM_DQM0, 0x00020030,
 750 MX6_IOM_DRAM_DQM1, 0x00020030,
 751 MX6_IOM_DRAM_DQM2, 0x00020030,
 752 MX6_IOM_DRAM_DQM3, 0x00020030,
 753 MX6_IOM_DRAM_DQM4, 0x00020030,
 754 MX6_IOM_DRAM_DQM5, 0x00020030,
 755 MX6_IOM_DRAM_DQM6, 0x00020030,
 756 MX6_IOM_DRAM_DQM7, 0x00020030,
 757
 758 MX6_IOM_DRAM_CAS, 0x00020030,
 759 MX6_IOM_DRAM_RAS, 0x00020030,
 760 MX6_IOM_DRAM_SDCLK_0, 0x00020030,
 761 MX6_IOM_DRAM_SDCLK_1, 0x00020030,
 762
 763 MX6_IOM_DRAM_RESET, 0x00020030,
 764 MX6_IOM_DRAM_SDCKE0, 0x00003000,
 765 MX6_IOM_DRAM_SDCKE1, 0x00003000,
 766
 767 MX6_IOM_DRAM_SDODT0, 0x00003030,
 768 MX6_IOM_DRAM_SDODT1, 0x00003030,
 769
 770 /* (differential input) */
 771 MX6_IOM_DDRMODE_CTL, 0x00020000,
 772 /* (differential input) */
 773 MX6_IOM_GRP_DDRMODE, 0x00020000,
 774 /* disable ddr pullups */
 775 MX6_IOM_GRP_DDRPKE, 0x00000000,
 776 MX6_IOM_DRAM_SDBA2, 0x00000000,
 777 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 778 MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
 779
 780 /* Read data DQ Byte0-3 delay */
 781 MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
 782 MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
 783 MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
 784 MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
 785 MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
 786 MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
 787 MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
 788 MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
 789
 790 /*
 791  * MDMISC       mirroring       interleaved (row/bank/col)
 792  */
 793 /* TODO: check what the RALAT field does */
 794 MX6_MMDC_P0_MDMISC, 0x00081740,
 795
 796 /*
 797  * MDSCR        con_req
 798  */
 799 MX6_MMDC_P0_MDSCR, 0x00008000,
 800
 801
 802 /* 800mhz_2x64mx16.cfg */
 803
 804 MX6_MMDC_P0_MDPDC, 0x0002002D,
 805 MX6_MMDC_P0_MDCFG0, 0x2C305503,
 806 MX6_MMDC_P0_MDCFG1, 0xB66D8D63,
 807 MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
 808 MX6_MMDC_P0_MDRWD, 0x000026D2,
 809 MX6_MMDC_P0_MDOR, 0x00301023,
 810 MX6_MMDC_P0_MDOTC, 0x00333030,
 811 MX6_MMDC_P0_MDPDC, 0x0002556D,
 812 /* CS0 End: 7MSB of ((0x10000000, + 512M) -1) >> 25 */
 813 MX6_MMDC_P0_MDASP, 0x00000017,
 814 /* DDR3 DATA BUS SIZE: 64BIT */
 815 /* MX6_MMDC_P0_MDCTL, 0x821A0000, */
 816 /* DDR3 DATA BUS SIZE: 32BIT */
 817 MX6_MMDC_P0_MDCTL, 0x82190000,
 818
 819 /* Write commands to DDR */
 820 /* Load Mode Registers */
 821 /* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
 822 /* MX6_MMDC_P0_MDSCR, 0x04408032, */
 823 MX6_MMDC_P0_MDSCR, 0x04008032,
 824 MX6_MMDC_P0_MDSCR, 0x00008033,
 825 MX6_MMDC_P0_MDSCR, 0x00048031,
 826 MX6_MMDC_P0_MDSCR, 0x13208030,
 827 /* ZQ calibration */
 828 MX6_MMDC_P0_MDSCR, 0x04008040,
 829
 830 MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
 831 MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
 832 MX6_MMDC_P0_MDREF, 0x00005800,
 833
 834 MX6_MMDC_P0_MPODTCTRL, 0x00000000,
 835 MX6_MMDC_P1_MPODTCTRL, 0x00000000,
 836
 837 MX6_MMDC_P0_MPDGCTRL0, 0x42360232,
 838 MX6_MMDC_P0_MPDGCTRL1, 0x021F022A,
 839 MX6_MMDC_P1_MPDGCTRL0, 0x421E0224,
 840 MX6_MMDC_P1_MPDGCTRL1, 0x02110218,
 841
 842 MX6_MMDC_P0_MPRDDLCTL, 0x41434344,
 843 MX6_MMDC_P1_MPRDDLCTL, 0x4345423E,
 844 MX6_MMDC_P0_MPWRDLCTL, 0x39383339,
 845 MX6_MMDC_P1_MPWRDLCTL, 0x3E363930,
 846
 847 MX6_MMDC_P0_MPWLDECTRL0, 0x00340039,
 848 MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D,
 849 MX6_MMDC_P1_MPWLDECTRL0, 0x00120019,
 850 MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D,
 851
 852 MX6_MMDC_P0_MPMUR0, 0x00000800,
 853 MX6_MMDC_P1_MPMUR0, 0x00000800,
 854 MX6_MMDC_P0_MDSCR, 0x00000000,
 855 MX6_MMDC_P0_MAPSR, 0x00011006,
 856 };
 857
 858 static int mx6dl_dcd_table[] = {
 859 /* ddr-setup.cfg */
 860
 861 MX6_IOM_DRAM_SDQS0, 0x00000030,
 862 MX6_IOM_DRAM_SDQS1, 0x00000030,
 863 MX6_IOM_DRAM_SDQS2, 0x00000030,
 864 MX6_IOM_DRAM_SDQS3, 0x00000030,
 865 MX6_IOM_DRAM_SDQS4, 0x00000030,
 866 MX6_IOM_DRAM_SDQS5, 0x00000030,
 867 MX6_IOM_DRAM_SDQS6, 0x00000030,
 868 MX6_IOM_DRAM_SDQS7, 0x00000030,
 869
 870 MX6_IOM_GRP_B0DS, 0x00000030,
 871 MX6_IOM_GRP_B1DS, 0x00000030,
 872 MX6_IOM_GRP_B2DS, 0x00000030,
 873 MX6_IOM_GRP_B3DS, 0x00000030,
 874 MX6_IOM_GRP_B4DS, 0x00000030,
 875 MX6_IOM_GRP_B5DS, 0x00000030,
 876 MX6_IOM_GRP_B6DS, 0x00000030,
 877 MX6_IOM_GRP_B7DS, 0x00000030,
 878 MX6_IOM_GRP_ADDDS, 0x00000030,
 879 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 880 MX6_IOM_GRP_CTLDS, 0x00000030,
 881
 882 MX6_IOM_DRAM_DQM0, 0x00020030,
 883 MX6_IOM_DRAM_DQM1, 0x00020030,
 884 MX6_IOM_DRAM_DQM2, 0x00020030,
 885 MX6_IOM_DRAM_DQM3, 0x00020030,
 886 MX6_IOM_DRAM_DQM4, 0x00020030,
 887 MX6_IOM_DRAM_DQM5, 0x00020030,
 888 MX6_IOM_DRAM_DQM6, 0x00020030,
 889 MX6_IOM_DRAM_DQM7, 0x00020030,
 890
 891 MX6_IOM_DRAM_CAS, 0x00020030,
 892 MX6_IOM_DRAM_RAS, 0x00020030,
 893 MX6_IOM_DRAM_SDCLK_0, 0x00020030,
 894 MX6_IOM_DRAM_SDCLK_1, 0x00020030,
 895
 896 MX6_IOM_DRAM_RESET, 0x00020030,
 897 MX6_IOM_DRAM_SDCKE0, 0x00003000,
 898 MX6_IOM_DRAM_SDCKE1, 0x00003000,
 899
 900 MX6_IOM_DRAM_SDODT0, 0x00003030,
 901 MX6_IOM_DRAM_SDODT1, 0x00003030,
 902
 903 /* (differential input) */
 904 MX6_IOM_DDRMODE_CTL, 0x00020000,
 905 /* (differential input) */
 906 MX6_IOM_GRP_DDRMODE, 0x00020000,
 907 /* disable ddr pullups */
 908 MX6_IOM_GRP_DDRPKE, 0x00000000,
 909 MX6_IOM_DRAM_SDBA2, 0x00000000,
 910 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 911 MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
 912
 913 /* Read data DQ Byte0-3 delay */
 914 MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
 915 MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
 916 MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
 917 MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
 918 MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
 919 MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
 920 MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
 921 MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
 922
 923 /*
 924  * MDMISC       mirroring       interleaved (row/bank/col)
 925  */
 926 /* TODO: check what the RALAT field does */
 927 MX6_MMDC_P0_MDMISC, 0x00081740,
 928
 929 /*
 930  * MDSCR        con_req
 931  */
 932 MX6_MMDC_P0_MDSCR, 0x00008000,
 933
 934
 935 /* 800mhz_2x64mx16.cfg */
 936
 937 MX6_MMDC_P0_MDPDC, 0x0002002D,
 938 MX6_MMDC_P0_MDCFG0, 0x2C305503,
 939 MX6_MMDC_P0_MDCFG1, 0xB66D8D63,
 940 MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
 941 MX6_MMDC_P0_MDRWD, 0x000026D2,
 942 MX6_MMDC_P0_MDOR, 0x00301023,
 943 MX6_MMDC_P0_MDOTC, 0x00333030,
 944 MX6_MMDC_P0_MDPDC, 0x0002556D,
 945 /* CS0 End: 7MSB of ((0x10000000, + 512M) -1) >> 25 */
 946 MX6_MMDC_P0_MDASP, 0x00000017,
 947 /* DDR3 DATA BUS SIZE: 64BIT */
 948 MX6_MMDC_P0_MDCTL, 0x821A0000,
 949 /* DDR3 DATA BUS SIZE: 32BIT */
 950 /* MX6_MMDC_P0_MDCTL, 0x82190000, */
 951
 952 /* Write commands to DDR */
 953 /* Load Mode Registers */
 954 /* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
 955 /* MX6_MMDC_P0_MDSCR, 0x04408032, */
 956 MX6_MMDC_P0_MDSCR, 0x04008032,
 957 MX6_MMDC_P0_MDSCR, 0x00008033,
 958 MX6_MMDC_P0_MDSCR, 0x00048031,
 959 MX6_MMDC_P0_MDSCR, 0x13208030,
 960 /* ZQ calibration */
 961 MX6_MMDC_P0_MDSCR, 0x04008040,
 962
 963 MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
 964 MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
 965 MX6_MMDC_P0_MDREF, 0x00005800,
 966
 967 MX6_MMDC_P0_MPODTCTRL, 0x00000000,
 968 MX6_MMDC_P1_MPODTCTRL, 0x00000000,
 969
 970 MX6_MMDC_P0_MPDGCTRL0, 0x42360232,
 971 MX6_MMDC_P0_MPDGCTRL1, 0x021F022A,
 972 MX6_MMDC_P1_MPDGCTRL0, 0x421E0224,
 973 MX6_MMDC_P1_MPDGCTRL1, 0x02110218,
 974
 975 MX6_MMDC_P0_MPRDDLCTL, 0x41434344,
 976 MX6_MMDC_P1_MPRDDLCTL, 0x4345423E,
 977 MX6_MMDC_P0_MPWRDLCTL, 0x39383339,
 978 MX6_MMDC_P1_MPWRDLCTL, 0x3E363930,
 979
 980 MX6_MMDC_P0_MPWLDECTRL0, 0x00340039,
 981 MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D,
 982 MX6_MMDC_P1_MPWLDECTRL0, 0x00120019,
 983 MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D,
 984
 985 MX6_MMDC_P0_MPMUR0, 0x00000800,
 986 MX6_MMDC_P1_MPMUR0, 0x00000800,
 987 MX6_MMDC_P0_MDSCR, 0x00000000,
 988 MX6_MMDC_P0_MAPSR, 0x00011006,
 989 };
 990
 991 static void ccgr_init(void)
 992 {
 993         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 994
 995         writel(0x00C03F3F, &ccm->CCGR0);
 996         writel(0x0030FC03, &ccm->CCGR1);
 997         writel(0x0FFFFFF3, &ccm->CCGR2);
 998         writel(0x3FF0300F, &ccm->CCGR3);
 999         writel(0x00FFF300, &ccm->CCGR4);
1000         writel(0x0F0000F3, &ccm->CCGR5);
1001         writel(0x000003FF, &ccm->CCGR6);
1002
1003 /*
1004  * Setup CCM_CCOSR register as follows:
1005  *
1006  * cko1_en  = 1    --> CKO1 enabled
1007  * cko1_div = 111  --> divide by 8
1008  * cko1_sel = 1011 --> ahb_clk_root
1009  *
1010  * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
1011  */
1012         writel(0x000000FB, &ccm->ccosr);
1013 }
1014
1015 static void ddr_init(int *table, int size)
1016 {
1017         int i;
1018
1019         for (i = 0; i < size / 2 ; i++)
1020                 writel(table[2 * i + 1], table[2 * i]);
1021 }
1022
1023 static void spl_dram_init(void)
1024 {
1025         int minc, maxc;
1026
1027         switch (get_cpu_temp_grade(&minc, &maxc)) {
1028         case TEMP_COMMERCIAL:
1029         case TEMP_EXTCOMMERCIAL:
1030                 if (is_cpu_type(MXC_CPU_MX6DL)) {
1031                         puts("Commercial temperature grade DDR3 timings, 64bit bus width.\n");
1032                         ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
1033                 } else {
1034                         puts("Commercial temperature grade DDR3 timings, 32bit bus width.\n");
1035                         ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
1036                 }
1037                 break;
1038         case TEMP_INDUSTRIAL:
1039         case TEMP_AUTOMOTIVE:
1040         default:
1041                 if (is_cpu_type(MXC_CPU_MX6DL)) {
1042                         puts("Industrial temperature grade DDR3 timings, 64bit bus width.\n");
1043                         ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
1044                 } else {
1045                         puts("Industrial temperature grade DDR3 timings, 32bit bus width.\n");
1046                         ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
1047                 }
1048                 break;
1049         };
1050         udelay(100);
1051 }
1052
1053 void board_init_f(ulong dummy)
1054 {
1055         /* setup AIPS and disable watchdog */
1056         arch_cpu_init();
1057
1058         ccgr_init();
1059         gpr_init();
1060
1061         /* iomux */
1062         board_early_init_f();
1063
1064         /* setup GP timer */
1065         timer_init();
1066
1067         /* UART clocks enabled and gd valid - init serial console */
1068         preloader_console_init();
1069
1070         /* Make sure we use dte mode */
1071         setup_dtemode_uart();
1072
1073         /* DDR initialization */
1074         spl_dram_init();
1075
1076         /* Clear the BSS. */
1077         memset(__bss_start, 0, __bss_end - __bss_start);
1078
1079         /* load/boot image from boot device */
1080         board_init_r(NULL, 0);
1081 }
1082
1083 void reset_cpu(ulong addr)
1084 {
1085 }
1086
1087 #endif /* CONFIG_SPL_BUILD */
1088
1089 static struct mxc_serial_platdata mxc_serial_plat = {
1090         .reg = (struct mxc_uart *)UART1_BASE,
1091         .use_dte = true,
1092 };
1093
1094 U_BOOT_DEVICE(mxc_serial) = {
1095         .name = "serial_mxc",
1096         .platdata = &mxc_serial_plat,
1097 };