board/toradex/colibri_imx6/colibri_imx6.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
   4  * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
   5  * Copyright (C) 2014-2019, Toradex AG
   6  * copied from nitrogen6x
   7  */
   8
   9 #include <common.h>
  10 #include <dm.h>
  11
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/crm_regs.h>
  14 #include <asm/arch/imx-regs.h>
  15 #include <asm/arch/mx6-ddr.h>
  16 #include <asm/arch/mx6-pins.h>
  17 #include <asm/arch/mxc_hdmi.h>
  18 #include <asm/arch/sys_proto.h>
  19 #include <asm/bootm.h>
  20 #include <asm/gpio.h>
  21 #include <asm/mach-imx/boot_mode.h>
  22 #include <asm/mach-imx/iomux-v3.h>
  23 #include <asm/mach-imx/sata.h>
  24 #include <asm/mach-imx/video.h>
  25 #include <dm/platform_data/serial_mxc.h>
  26 #include <environment.h>
  27 #include <fsl_esdhc.h>
  28 #include <imx_thermal.h>
  29 #include <micrel.h>
  30 #include <miiphy.h>
  31 #include <netdev.h>
  32
  33 #include "../common/tdx-cfg-block.h"
  34 #ifdef CONFIG_TDX_CMD_IMX_MFGR
  35 #include "pf0100.h"
  36 #endif
  37
  38 DECLARE_GLOBAL_DATA_PTR;
  39
  40 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  41         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  42         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  43
  44 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  45         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  46         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  47
  48 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  49         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  50
  51 #define WEAK_PULLUP     (PAD_CTL_PUS_100K_UP |                  \
  52         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  53         PAD_CTL_SRE_SLOW)
  54
  55 #define NO_PULLUP       (                                       \
  56         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  57         PAD_CTL_SRE_SLOW)
  58
  59 #define WEAK_PULLDOWN   (PAD_CTL_PUS_100K_DOWN |                \
  60         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  61         PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
  62
  63 #define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST)
  64
  65 int dram_init(void)
  66 {
  67         /* use the DDR controllers configured size */
  68         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  69                                     (ulong)imx_ddr_size());
  70
  71         return 0;
  72 }
  73
  74 /* Colibri UARTA */
  75 iomux_v3_cfg_t const uart1_pads[] = {
  76         MX6_PAD_CSI0_DAT10__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  77         MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  78 };
  79
  80 #if defined(CONFIG_FSL_ESDHC) && defined(CONFIG_SPL_BUILD)
  81 /* Colibri MMC */
  82 iomux_v3_cfg_t const usdhc1_pads[] = {
  83         MX6_PAD_SD1_CLK__SD1_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  84         MX6_PAD_SD1_CMD__SD1_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  85         MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  86         MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  87         MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  88         MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  89         MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
  90 #       define GPIO_MMC_CD IMX_GPIO_NR(2, 5)
  91 };
  92
  93 /* eMMC */
  94 iomux_v3_cfg_t const usdhc3_pads[] = {
  95         MX6_PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  96         MX6_PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  97         MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  98         MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  99         MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 100         MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 101         MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 102         MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 103         MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 104         MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 105         MX6_PAD_SD3_RST__SD3_RESET  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 106 };
 107 #endif /* CONFIG_FSL_ESDHC & CONFIG_SPL_BUILD */
 108
 109 iomux_v3_cfg_t const enet_pads[] = {
 110         MX6_PAD_ENET_MDC__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
 111         MX6_PAD_ENET_MDIO__ENET_MDIO            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 112         MX6_PAD_ENET_RXD0__ENET_RX_DATA0        | MUX_PAD_CTRL(ENET_PAD_CTRL),
 113         MX6_PAD_ENET_RXD1__ENET_RX_DATA1        | MUX_PAD_CTRL(ENET_PAD_CTRL),
 114         MX6_PAD_ENET_RX_ER__ENET_RX_ER          | MUX_PAD_CTRL(ENET_PAD_CTRL),
 115         MX6_PAD_ENET_TX_EN__ENET_TX_EN          | MUX_PAD_CTRL(ENET_PAD_CTRL),
 116         MX6_PAD_ENET_TXD0__ENET_TX_DATA0        | MUX_PAD_CTRL(ENET_PAD_CTRL),
 117         MX6_PAD_ENET_TXD1__ENET_TX_DATA1        | MUX_PAD_CTRL(ENET_PAD_CTRL),
 118         MX6_PAD_ENET_CRS_DV__ENET_RX_EN         | MUX_PAD_CTRL(ENET_PAD_CTRL),
 119         MX6_PAD_GPIO_16__ENET_REF_CLK           | MUX_PAD_CTRL(ENET_PAD_CTRL),
 120 };
 121
 122 static void setup_iomux_enet(void)
 123 {
 124         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
 125 }
 126
 127 /* mux auxiliary pins to GPIO, so they can be used from the U-Boot cmdline */
 128 iomux_v3_cfg_t const gpio_pads[] = {
 129         /* ADDRESS[17:18] [25] used as GPIO */
 130         MX6_PAD_KEY_ROW2__GPIO4_IO11    | MUX_PAD_CTRL(WEAK_PULLUP) |
 131                                           MUX_MODE_SION,
 132         MX6_PAD_KEY_COL2__GPIO4_IO10    | MUX_PAD_CTRL(WEAK_PULLUP) |
 133                                           MUX_MODE_SION,
 134         MX6_PAD_NANDF_D1__GPIO2_IO01    | MUX_PAD_CTRL(WEAK_PULLUP) |
 135                                           MUX_MODE_SION,
 136         /* ADDRESS[19:24] used as GPIO */
 137         MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(WEAK_PULLUP) |
 138                                           MUX_MODE_SION,
 139         MX6_PAD_DISP0_DAT22__GPIO5_IO16 | MUX_PAD_CTRL(WEAK_PULLUP) |
 140                                           MUX_MODE_SION,
 141         MX6_PAD_DISP0_DAT21__GPIO5_IO15 | MUX_PAD_CTRL(WEAK_PULLUP) |
 142                                           MUX_MODE_SION,
 143         MX6_PAD_DISP0_DAT20__GPIO5_IO14 | MUX_PAD_CTRL(WEAK_PULLUP) |
 144                                           MUX_MODE_SION,
 145         MX6_PAD_DISP0_DAT19__GPIO5_IO13 | MUX_PAD_CTRL(WEAK_PULLUP) |
 146                                           MUX_MODE_SION,
 147         MX6_PAD_DISP0_DAT18__GPIO5_IO12 | MUX_PAD_CTRL(WEAK_PULLUP) |
 148                                           MUX_MODE_SION,
 149         /* DATA[16:29] [31]      used as GPIO */
 150         MX6_PAD_EIM_LBA__GPIO2_IO27     | MUX_PAD_CTRL(WEAK_PULLUP) |
 151                                           MUX_MODE_SION,
 152         MX6_PAD_EIM_BCLK__GPIO6_IO31    | MUX_PAD_CTRL(WEAK_PULLUP) |
 153                                           MUX_MODE_SION,
 154         MX6_PAD_NANDF_CS3__GPIO6_IO16   | MUX_PAD_CTRL(WEAK_PULLUP) |
 155                                           MUX_MODE_SION,
 156         MX6_PAD_NANDF_CS1__GPIO6_IO14   | MUX_PAD_CTRL(WEAK_PULLUP) |
 157                                           MUX_MODE_SION,
 158         MX6_PAD_NANDF_RB0__GPIO6_IO10   | MUX_PAD_CTRL(WEAK_PULLUP) |
 159                                           MUX_MODE_SION,
 160         MX6_PAD_NANDF_ALE__GPIO6_IO08   | MUX_PAD_CTRL(WEAK_PULLUP) |
 161                                           MUX_MODE_SION,
 162         MX6_PAD_NANDF_WP_B__GPIO6_IO09  | MUX_PAD_CTRL(WEAK_PULLUP) |
 163                                           MUX_MODE_SION,
 164         MX6_PAD_NANDF_CS0__GPIO6_IO11   | MUX_PAD_CTRL(WEAK_PULLUP) |
 165                                           MUX_MODE_SION,
 166         MX6_PAD_NANDF_CLE__GPIO6_IO07   | MUX_PAD_CTRL(WEAK_PULLUP) |
 167                                           MUX_MODE_SION,
 168         MX6_PAD_GPIO_19__GPIO4_IO05     | MUX_PAD_CTRL(WEAK_PULLUP) |
 169                                           MUX_MODE_SION,
 170         MX6_PAD_CSI0_MCLK__GPIO5_IO19   | MUX_PAD_CTRL(WEAK_PULLUP) |
 171                                           MUX_MODE_SION,
 172         MX6_PAD_CSI0_PIXCLK__GPIO5_IO18 | MUX_PAD_CTRL(WEAK_PULLUP) |
 173                                           MUX_MODE_SION,
 174         MX6_PAD_GPIO_4__GPIO1_IO04      | MUX_PAD_CTRL(WEAK_PULLUP) |
 175                                           MUX_MODE_SION,
 176         MX6_PAD_GPIO_5__GPIO1_IO05      | MUX_PAD_CTRL(WEAK_PULLUP) |
 177                                           MUX_MODE_SION,
 178         MX6_PAD_GPIO_2__GPIO1_IO02      | MUX_PAD_CTRL(WEAK_PULLUP) |
 179                                           MUX_MODE_SION,
 180         /* DQM[0:3]      used as GPIO */
 181         MX6_PAD_EIM_EB0__GPIO2_IO28     | MUX_PAD_CTRL(WEAK_PULLUP) |
 182                                           MUX_MODE_SION,
 183         MX6_PAD_EIM_EB1__GPIO2_IO29     | MUX_PAD_CTRL(WEAK_PULLUP) |
 184                                           MUX_MODE_SION,
 185         MX6_PAD_SD2_DAT2__GPIO1_IO13    | MUX_PAD_CTRL(WEAK_PULLUP) |
 186                                           MUX_MODE_SION,
 187         MX6_PAD_NANDF_D0__GPIO2_IO00    | MUX_PAD_CTRL(WEAK_PULLUP) |
 188                                           MUX_MODE_SION,
 189         /* RDY  used as GPIO */
 190         MX6_PAD_EIM_WAIT__GPIO5_IO00    | MUX_PAD_CTRL(WEAK_PULLUP) |
 191                                           MUX_MODE_SION,
 192         /* ADDRESS[16] DATA[30]  used as GPIO */
 193         MX6_PAD_KEY_ROW4__GPIO4_IO15    | MUX_PAD_CTRL(WEAK_PULLDOWN) |
 194                                           MUX_MODE_SION,
 195         MX6_PAD_KEY_COL4__GPIO4_IO14    | MUX_PAD_CTRL(WEAK_PULLUP) |
 196                                           MUX_MODE_SION,
 197         /* CSI pins used as GPIO */
 198         MX6_PAD_EIM_A24__GPIO5_IO04     | MUX_PAD_CTRL(WEAK_PULLUP) |
 199                                           MUX_MODE_SION,
 200         MX6_PAD_SD2_CMD__GPIO1_IO11     | MUX_PAD_CTRL(WEAK_PULLUP) |
 201                                           MUX_MODE_SION,
 202         MX6_PAD_NANDF_CS2__GPIO6_IO15   | MUX_PAD_CTRL(WEAK_PULLUP) |
 203                                           MUX_MODE_SION,
 204         MX6_PAD_EIM_D18__GPIO3_IO18     | MUX_PAD_CTRL(WEAK_PULLUP) |
 205                                           MUX_MODE_SION,
 206         MX6_PAD_EIM_A19__GPIO2_IO19     | MUX_PAD_CTRL(WEAK_PULLUP) |
 207                                           MUX_MODE_SION,
 208         MX6_PAD_EIM_D29__GPIO3_IO29     | MUX_PAD_CTRL(WEAK_PULLDOWN) |
 209                                           MUX_MODE_SION,
 210         MX6_PAD_EIM_A23__GPIO6_IO06     | MUX_PAD_CTRL(WEAK_PULLUP) |
 211                                           MUX_MODE_SION,
 212         MX6_PAD_EIM_A20__GPIO2_IO18     | MUX_PAD_CTRL(WEAK_PULLUP) |
 213                                           MUX_MODE_SION,
 214         MX6_PAD_EIM_A17__GPIO2_IO21     | MUX_PAD_CTRL(WEAK_PULLUP) |
 215                                           MUX_MODE_SION,
 216         MX6_PAD_EIM_A18__GPIO2_IO20     | MUX_PAD_CTRL(WEAK_PULLUP) |
 217                                           MUX_MODE_SION,
 218         MX6_PAD_EIM_EB3__GPIO2_IO31     | MUX_PAD_CTRL(WEAK_PULLUP) |
 219                                           MUX_MODE_SION,
 220         MX6_PAD_EIM_D17__GPIO3_IO17     | MUX_PAD_CTRL(WEAK_PULLUP) |
 221                                           MUX_MODE_SION,
 222         MX6_PAD_SD2_DAT0__GPIO1_IO15    | MUX_PAD_CTRL(WEAK_PULLUP) |
 223                                           MUX_MODE_SION,
 224         /* GPIO */
 225         MX6_PAD_EIM_D26__GPIO3_IO26     | MUX_PAD_CTRL(WEAK_PULLUP) |
 226                                           MUX_MODE_SION,
 227         MX6_PAD_EIM_D27__GPIO3_IO27     | MUX_PAD_CTRL(WEAK_PULLUP) |
 228                                           MUX_MODE_SION,
 229         MX6_PAD_NANDF_D6__GPIO2_IO06    | MUX_PAD_CTRL(WEAK_PULLUP) |
 230                                           MUX_MODE_SION,
 231         MX6_PAD_NANDF_D3__GPIO2_IO03    | MUX_PAD_CTRL(WEAK_PULLUP) |
 232                                           MUX_MODE_SION,
 233         MX6_PAD_ENET_REF_CLK__GPIO1_IO23 | MUX_PAD_CTRL(WEAK_PULLUP) |
 234                                           MUX_MODE_SION,
 235         MX6_PAD_DI0_PIN4__GPIO4_IO20    | MUX_PAD_CTRL(WEAK_PULLUP) |
 236                                           MUX_MODE_SION,
 237         MX6_PAD_SD4_DAT3__GPIO2_IO11    | MUX_PAD_CTRL(WEAK_PULLUP) |
 238                                           MUX_MODE_SION,
 239         MX6_PAD_NANDF_D4__GPIO2_IO04    | MUX_PAD_CTRL(WEAK_PULLUP) |
 240                                           MUX_MODE_SION,
 241         MX6_PAD_SD4_DAT0__GPIO2_IO08    | MUX_PAD_CTRL(WEAK_PULLUP) |
 242                                           MUX_MODE_SION,
 243         MX6_PAD_GPIO_7__GPIO1_IO07      | MUX_PAD_CTRL(WEAK_PULLUP) |
 244                                           MUX_MODE_SION,
 245         MX6_PAD_GPIO_8__GPIO1_IO08      | MUX_PAD_CTRL(WEAK_PULLUP) |
 246                                           MUX_MODE_SION,
 247         /* USBH_OC */
 248         MX6_PAD_EIM_D30__GPIO3_IO30     | MUX_PAD_CTRL(WEAK_PULLUP),
 249         /* USBC_ID */
 250         MX6_PAD_NANDF_D2__GPIO2_IO02    | MUX_PAD_CTRL(WEAK_PULLUP),
 251         /* USBC_DET */
 252         MX6_PAD_GPIO_17__GPIO7_IO12     | MUX_PAD_CTRL(WEAK_PULLUP),
 253 };
 254
 255 static void setup_iomux_gpio(void)
 256 {
 257         imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
 258 }
 259
 260 iomux_v3_cfg_t const usb_pads[] = {
 261         /* USBH_PEN */
 262         MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
 263 #       define GPIO_USBH_EN IMX_GPIO_NR(3, 31)
 264 };
 265
 266 /*
 267  * UARTs are used in DTE mode, switch the mode on all UARTs before
 268  * any pinmuxing connects a (DCE) output to a transceiver output.
 269  */
 270 #define UFCR            0x90    /* FIFO Control Register */
 271 #define UFCR_DCEDTE     (1<<6)  /* DCE=0 */
 272
 273 static void setup_dtemode_uart(void)
 274 {
 275         setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
 276         setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
 277         setbits_le32((u32 *)(UART3_BASE + UFCR), UFCR_DCEDTE);
 278 }
 279
 280 static void setup_iomux_uart(void)
 281 {
 282         setup_dtemode_uart();
 283         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 284 }
 285
 286 #ifdef CONFIG_USB_EHCI_MX6
 287 int board_ehci_hcd_init(int port)
 288 {
 289         imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
 290         return 0;
 291 }
 292 #endif
 293
 294 #if defined(CONFIG_FSL_ESDHC) && defined(CONFIG_SPL_BUILD)
 295 /* use the following sequence: eMMC, MMC */
 296 struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
 297         {USDHC3_BASE_ADDR},
 298         {USDHC1_BASE_ADDR},
 299 };
 300
 301 int board_mmc_getcd(struct mmc *mmc)
 302 {
 303         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 304         int ret = true; /* default: assume inserted */
 305
 306         switch (cfg->esdhc_base) {
 307         case USDHC1_BASE_ADDR:
 308                 gpio_request(GPIO_MMC_CD, "MMC_CD");
 309                 gpio_direction_input(GPIO_MMC_CD);
 310                 ret = !gpio_get_value(GPIO_MMC_CD);
 311                 break;
 312         }
 313
 314         return ret;
 315 }
 316
 317 int board_mmc_init(bd_t *bis)
 318 {
 319         struct src *psrc = (struct src *)SRC_BASE_ADDR;
 320         unsigned reg = readl(&psrc->sbmr1) >> 11;
 321         /*
 322          * Upon reading BOOT_CFG register the following map is done:
 323          * Bit 11 and 12 of BOOT_CFG register can determine the current
 324          * mmc port
 325          * 0x1                  SD1
 326          * 0x2                  SD2
 327          * 0x3                  SD4
 328          */
 329
 330         switch (reg & 0x3) {
 331         case 0x0:
 332                 imx_iomux_v3_setup_multiple_pads(
 333                         usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
 334                 usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
 335                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 336                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 337                 break;
 338         case 0x2:
 339                 imx_iomux_v3_setup_multiple_pads(
 340                         usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 341                 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
 342                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 343                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 344                 break;
 345         default:
 346                 puts("MMC boot device not available");
 347         }
 348
 349         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 350 }
 351 #endif /* CONFIG_FSL_ESDHC & CONFIG_SPL_BUILD */
 352
 353 int board_phy_config(struct phy_device *phydev)
 354 {
 355         if (phydev->drv->config)
 356                 phydev->drv->config(phydev);
 357
 358         return 0;
 359 }
 360
 361 int board_eth_init(bd_t *bis)
 362 {
 363         struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 364         uint32_t base = IMX_FEC_BASE;
 365         struct mii_dev *bus = NULL;
 366         struct phy_device *phydev = NULL;
 367         int ret;
 368
 369         /* provide the PHY clock from the i.MX 6 */
 370         ret = enable_fec_anatop_clock(0, ENET_50MHZ);
 371         if (ret)
 372                 return ret;
 373
 374         /* set gpr1[ENET_CLK_SEL] */
 375         setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
 376
 377         setup_iomux_enet();
 378
 379 #ifdef CONFIG_FEC_MXC
 380         bus = fec_get_miibus(base, -1);
 381         if (!bus)
 382                 return 0;
 383
 384         /* scan PHY 1..7 */
 385         phydev = phy_find_by_mask(bus, 0xff, PHY_INTERFACE_MODE_RMII);
 386         if (!phydev) {
 387                 free(bus);
 388                 puts("no PHY found\n");
 389                 return 0;
 390         }
 391
 392         phy_reset(phydev);
 393         printf("using PHY at %d\n", phydev->addr);
 394         ret = fec_probe(bis, -1, base, bus, phydev);
 395         if (ret) {
 396                 printf("FEC MXC: %s:failed\n", __func__);
 397                 free(phydev);
 398                 free(bus);
 399         }
 400 #endif /* CONFIG_FEC_MXC */
 401
 402         return 0;
 403 }
 404
 405 static iomux_v3_cfg_t const pwr_intb_pads[] = {
 406         /*
 407          * the bootrom sets the iomux to vselect, potentially connecting
 408          * two outputs. Set this back to GPIO
 409          */
 410         MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)
 411 };
 412
 413 #if defined(CONFIG_VIDEO_IPUV3)
 414
 415 static iomux_v3_cfg_t const backlight_pads[] = {
 416         /* Backlight On */
 417         MX6_PAD_EIM_D26__GPIO3_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
 418 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 26)
 419         /* Backlight PWM, used as GPIO in U-Boot */
 420         MX6_PAD_EIM_A22__GPIO2_IO16  | MUX_PAD_CTRL(NO_PULLUP),
 421         MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL) |
 422                                        MUX_MODE_SION,
 423 #define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 9)
 424 };
 425
 426 static iomux_v3_cfg_t const rgb_pads[] = {
 427         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(OUTPUT_RGB),
 428         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(OUTPUT_RGB),
 429         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(OUTPUT_RGB),
 430         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(OUTPUT_RGB),
 431         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(OUTPUT_RGB),
 432         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(OUTPUT_RGB),
 433         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(OUTPUT_RGB),
 434         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(OUTPUT_RGB),
 435         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(OUTPUT_RGB),
 436         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(OUTPUT_RGB),
 437         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(OUTPUT_RGB),
 438         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(OUTPUT_RGB),
 439         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(OUTPUT_RGB),
 440         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(OUTPUT_RGB),
 441         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(OUTPUT_RGB),
 442         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(OUTPUT_RGB),
 443         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(OUTPUT_RGB),
 444         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(OUTPUT_RGB),
 445         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(OUTPUT_RGB),
 446         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(OUTPUT_RGB),
 447         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(OUTPUT_RGB),
 448         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(OUTPUT_RGB),
 449 };
 450
 451 static void do_enable_hdmi(struct display_info_t const *dev)
 452 {
 453         imx_enable_hdmi_phy();
 454 }
 455
 456 static void enable_rgb(struct display_info_t const *dev)
 457 {
 458         imx_iomux_v3_setup_multiple_pads(
 459                 rgb_pads,
 460                 ARRAY_SIZE(rgb_pads));
 461         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 462         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
 463 }
 464
 465 static int detect_default(struct display_info_t const *dev)
 466 {
 467         (void) dev;
 468         return 1;
 469 }
 470
 471 struct display_info_t const displays[] = {{
 472         .bus    = -1,
 473         .addr   = 0,
 474         .pixfmt = IPU_PIX_FMT_RGB24,
 475         .detect = detect_hdmi,
 476         .enable = do_enable_hdmi,
 477         .mode   = {
 478                 .name           = "HDMI",
 479                 .refresh        = 60,
 480                 .xres           = 1024,
 481                 .yres           = 768,
 482                 .pixclock       = 15385,
 483                 .left_margin    = 220,
 484                 .right_margin   = 40,
 485                 .upper_margin   = 21,
 486                 .lower_margin   = 7,
 487                 .hsync_len      = 60,
 488                 .vsync_len      = 10,
 489                 .sync           = FB_SYNC_EXT,
 490                 .vmode          = FB_VMODE_NONINTERLACED
 491 } }, {
 492         .bus    = -1,
 493         .addr   = 0,
 494         .pixfmt = IPU_PIX_FMT_RGB666,
 495         .detect = detect_default,
 496         .enable = enable_rgb,
 497         .mode   = {
 498                 .name           = "vga-rgb",
 499                 .refresh        = 60,
 500                 .xres           = 640,
 501                 .yres           = 480,
 502                 .pixclock       = 33000,
 503                 .left_margin    = 48,
 504                 .right_margin   = 16,
 505                 .upper_margin   = 31,
 506                 .lower_margin   = 11,
 507                 .hsync_len      = 96,
 508                 .vsync_len      = 2,
 509                 .sync           = 0,
 510                 .vmode          = FB_VMODE_NONINTERLACED
 511 } }, {
 512         .bus    = -1,
 513         .addr   = 0,
 514         .pixfmt = IPU_PIX_FMT_RGB666,
 515         .enable = enable_rgb,
 516         .mode   = {
 517                 .name           = "wvga-rgb",
 518                 .refresh        = 60,
 519                 .xres           = 800,
 520                 .yres           = 480,
 521                 .pixclock       = 25000,
 522                 .left_margin    = 40,
 523                 .right_margin   = 88,
 524                 .upper_margin   = 33,
 525                 .lower_margin   = 10,
 526                 .hsync_len      = 128,
 527                 .vsync_len      = 2,
 528                 .sync           = 0,
 529                 .vmode          = FB_VMODE_NONINTERLACED
 530 } } };
 531 size_t display_count = ARRAY_SIZE(displays);
 532
 533 static void setup_display(void)
 534 {
 535         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 536         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 537         int reg;
 538
 539         enable_ipu_clock();
 540         imx_setup_hdmi();
 541         /* Turn on LDB0,IPU,IPU DI0 clocks */
 542         reg = __raw_readl(&mxc_ccm->CCGR3);
 543         reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
 544         writel(reg, &mxc_ccm->CCGR3);
 545
 546         /* set LDB0, LDB1 clk select to 011/011 */
 547         reg = readl(&mxc_ccm->cs2cdr);
 548         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 549                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 550         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 551               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 552         writel(reg, &mxc_ccm->cs2cdr);
 553
 554         reg = readl(&mxc_ccm->cscmr2);
 555         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 556         writel(reg, &mxc_ccm->cscmr2);
 557
 558         reg = readl(&mxc_ccm->chsccdr);
 559         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 560                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 561         writel(reg, &mxc_ccm->chsccdr);
 562
 563         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 564              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 565              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 566              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 567              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 568              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 569              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 570              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 571              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 572         writel(reg, &iomux->gpr[2]);
 573
 574         reg = readl(&iomux->gpr[3]);
 575         reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
 576                         |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
 577             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 578                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 579         writel(reg, &iomux->gpr[3]);
 580
 581         /* backlight unconditionally on for now */
 582         imx_iomux_v3_setup_multiple_pads(backlight_pads,
 583                                          ARRAY_SIZE(backlight_pads));
 584         /* use 0 for EDT 7", use 1 for LG fullHD panel */
 585         gpio_request(RGB_BACKLIGHTPWM_GP, "PWM<A>");
 586         gpio_request(RGB_BACKLIGHT_GP, "BL_ON");
 587         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
 588         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 589 }
 590
 591 /*
 592  * Backlight off before OS handover
 593  */
 594 void board_preboot_os(void)
 595 {
 596         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 1);
 597         gpio_direction_output(RGB_BACKLIGHT_GP, 0);
 598 }
 599 #endif /* defined(CONFIG_VIDEO_IPUV3) */
 600
 601 int board_early_init_f(void)
 602 {
 603         imx_iomux_v3_setup_multiple_pads(pwr_intb_pads,
 604                                          ARRAY_SIZE(pwr_intb_pads));
 605         setup_iomux_uart();
 606
 607         return 0;
 608 }
 609
 610 /*
 611  * Do not overwrite the console
 612  * Use always serial for U-Boot console
 613  */
 614 int overwrite_console(void)
 615 {
 616         return 1;
 617 }
 618
 619 int board_init(void)
 620 {
 621         /* address of boot parameters */
 622         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 623
 624 #if defined(CONFIG_VIDEO_IPUV3)
 625         setup_display();
 626 #endif
 627
 628 #ifdef CONFIG_TDX_CMD_IMX_MFGR
 629         (void) pmic_init();
 630 #endif
 631
 632 #ifdef CONFIG_SATA
 633         setup_sata();
 634 #endif
 635
 636         setup_iomux_gpio();
 637
 638         return 0;
 639 }
 640
 641 #ifdef CONFIG_BOARD_LATE_INIT
 642 int board_late_init(void)
 643 {
 644 #if defined(CONFIG_REVISION_TAG) && \
 645     defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
 646         char env_str[256];
 647         u32 rev;
 648
 649         rev = get_board_rev();
 650         snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev);
 651         env_set("board_rev", env_str);
 652 #endif
 653
 654         return 0;
 655 }
 656 #endif /* CONFIG_BOARD_LATE_INIT */
 657
 658 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_SYSTEM_SETUP)
 659 int ft_system_setup(void *blob, bd_t *bd)
 660 {
 661         return 0;
 662 }
 663 #endif
 664
 665 int checkboard(void)
 666 {
 667         char it[] = " IT";
 668         int minc, maxc;
 669
 670         switch (get_cpu_temp_grade(&minc, &maxc)) {
 671         case TEMP_AUTOMOTIVE:
 672         case TEMP_INDUSTRIAL:
 673                 break;
 674         case TEMP_EXTCOMMERCIAL:
 675         default:
 676                 it[0] = 0;
 677         };
 678         printf("Model: Toradex Colibri iMX6 %s %sMB%s\n",
 679                is_cpu_type(MXC_CPU_MX6DL) ? "DualLite" : "Solo",
 680                (gd->ram_size == 0x20000000) ? "512" : "256", it);
 681         return 0;
 682 }
 683
 684 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 685 int ft_board_setup(void *blob, bd_t *bd)
 686 {
 687         return ft_common_board_setup(blob, bd);
 688 }
 689 #endif
 690
 691 #ifdef CONFIG_CMD_BMODE
 692 static const struct boot_mode board_boot_modes[] = {
 693         {"mmc", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
 694         {NULL,  0},
 695 };
 696 #endif
 697
 698 int misc_init_r(void)
 699 {
 700 #ifdef CONFIG_CMD_BMODE
 701         add_board_boot_modes(board_boot_modes);
 702 #endif
 703         return 0;
 704 }
 705
 706 #ifdef CONFIG_LDO_BYPASS_CHECK
 707 /* TODO, use external pmic, for now always ldo_enable */
 708 void ldo_mode_set(int ldo_bypass)
 709 {
 710         return;
 711 }
 712 #endif
 713
 714 #ifdef CONFIG_SPL_BUILD
 715 #include <spl.h>
 716 #include <linux/libfdt.h>
 717 #include "asm/arch/mx6dl-ddr.h"
 718 #include "asm/arch/iomux.h"
 719 #include "asm/arch/crm_regs.h"
 720
 721 static int mx6s_dcd_table[] = {
 722 /* ddr-setup.cfg */
 723
 724 MX6_IOM_DRAM_SDQS0, 0x00000030,
 725 MX6_IOM_DRAM_SDQS1, 0x00000030,
 726 MX6_IOM_DRAM_SDQS2, 0x00000030,
 727 MX6_IOM_DRAM_SDQS3, 0x00000030,
 728 MX6_IOM_DRAM_SDQS4, 0x00000030,
 729 MX6_IOM_DRAM_SDQS5, 0x00000030,
 730 MX6_IOM_DRAM_SDQS6, 0x00000030,
 731 MX6_IOM_DRAM_SDQS7, 0x00000030,
 732
 733 MX6_IOM_GRP_B0DS, 0x00000030,
 734 MX6_IOM_GRP_B1DS, 0x00000030,
 735 MX6_IOM_GRP_B2DS, 0x00000030,
 736 MX6_IOM_GRP_B3DS, 0x00000030,
 737 MX6_IOM_GRP_B4DS, 0x00000030,
 738 MX6_IOM_GRP_B5DS, 0x00000030,
 739 MX6_IOM_GRP_B6DS, 0x00000030,
 740 MX6_IOM_GRP_B7DS, 0x00000030,
 741 MX6_IOM_GRP_ADDDS, 0x00000030,
 742 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 743 MX6_IOM_GRP_CTLDS, 0x00000030,
 744
 745 MX6_IOM_DRAM_DQM0, 0x00020030,
 746 MX6_IOM_DRAM_DQM1, 0x00020030,
 747 MX6_IOM_DRAM_DQM2, 0x00020030,
 748 MX6_IOM_DRAM_DQM3, 0x00020030,
 749 MX6_IOM_DRAM_DQM4, 0x00020030,
 750 MX6_IOM_DRAM_DQM5, 0x00020030,
 751 MX6_IOM_DRAM_DQM6, 0x00020030,
 752 MX6_IOM_DRAM_DQM7, 0x00020030,
 753
 754 MX6_IOM_DRAM_CAS, 0x00020030,
 755 MX6_IOM_DRAM_RAS, 0x00020030,
 756 MX6_IOM_DRAM_SDCLK_0, 0x00020030,
 757 MX6_IOM_DRAM_SDCLK_1, 0x00020030,
 758
 759 MX6_IOM_DRAM_RESET, 0x00020030,
 760 MX6_IOM_DRAM_SDCKE0, 0x00003000,
 761 MX6_IOM_DRAM_SDCKE1, 0x00003000,
 762
 763 MX6_IOM_DRAM_SDODT0, 0x00003030,
 764 MX6_IOM_DRAM_SDODT1, 0x00003030,
 765
 766 /* (differential input) */
 767 MX6_IOM_DDRMODE_CTL, 0x00020000,
 768 /* (differential input) */
 769 MX6_IOM_GRP_DDRMODE, 0x00020000,
 770 /* disable ddr pullups */
 771 MX6_IOM_GRP_DDRPKE, 0x00000000,
 772 MX6_IOM_DRAM_SDBA2, 0x00000000,
 773 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 774 MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
 775
 776 /* Read data DQ Byte0-3 delay */
 777 MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
 778 MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
 779 MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
 780 MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
 781 MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
 782 MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
 783 MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
 784 MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
 785
 786 /*
 787  * MDMISC       mirroring       interleaved (row/bank/col)
 788  */
 789 /* TODO: check what the RALAT field does */
 790 MX6_MMDC_P0_MDMISC, 0x00081740,
 791
 792 /*
 793  * MDSCR        con_req
 794  */
 795 MX6_MMDC_P0_MDSCR, 0x00008000,
 796
 797
 798 /* 800mhz_2x64mx16.cfg */
 799
 800 MX6_MMDC_P0_MDPDC, 0x0002002D,
 801 MX6_MMDC_P0_MDCFG0, 0x2C305503,
 802 MX6_MMDC_P0_MDCFG1, 0xB66D8D63,
 803 MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
 804 MX6_MMDC_P0_MDRWD, 0x000026D2,
 805 MX6_MMDC_P0_MDOR, 0x00301023,
 806 MX6_MMDC_P0_MDOTC, 0x00333030,
 807 MX6_MMDC_P0_MDPDC, 0x0002556D,
 808 /* CS0 End: 7MSB of ((0x10000000, + 512M) -1) >> 25 */
 809 MX6_MMDC_P0_MDASP, 0x00000017,
 810 /* DDR3 DATA BUS SIZE: 64BIT */
 811 /* MX6_MMDC_P0_MDCTL, 0x821A0000, */
 812 /* DDR3 DATA BUS SIZE: 32BIT */
 813 MX6_MMDC_P0_MDCTL, 0x82190000,
 814
 815 /* Write commands to DDR */
 816 /* Load Mode Registers */
 817 /* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
 818 /* MX6_MMDC_P0_MDSCR, 0x04408032, */
 819 MX6_MMDC_P0_MDSCR, 0x04008032,
 820 MX6_MMDC_P0_MDSCR, 0x00008033,
 821 MX6_MMDC_P0_MDSCR, 0x00048031,
 822 MX6_MMDC_P0_MDSCR, 0x13208030,
 823 /* ZQ calibration */
 824 MX6_MMDC_P0_MDSCR, 0x04008040,
 825
 826 MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
 827 MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
 828 MX6_MMDC_P0_MDREF, 0x00005800,
 829
 830 MX6_MMDC_P0_MPODTCTRL, 0x00000000,
 831 MX6_MMDC_P1_MPODTCTRL, 0x00000000,
 832
 833 MX6_MMDC_P0_MPDGCTRL0, 0x42360232,
 834 MX6_MMDC_P0_MPDGCTRL1, 0x021F022A,
 835 MX6_MMDC_P1_MPDGCTRL0, 0x421E0224,
 836 MX6_MMDC_P1_MPDGCTRL1, 0x02110218,
 837
 838 MX6_MMDC_P0_MPRDDLCTL, 0x41434344,
 839 MX6_MMDC_P1_MPRDDLCTL, 0x4345423E,
 840 MX6_MMDC_P0_MPWRDLCTL, 0x39383339,
 841 MX6_MMDC_P1_MPWRDLCTL, 0x3E363930,
 842
 843 MX6_MMDC_P0_MPWLDECTRL0, 0x00340039,
 844 MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D,
 845 MX6_MMDC_P1_MPWLDECTRL0, 0x00120019,
 846 MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D,
 847
 848 MX6_MMDC_P0_MPMUR0, 0x00000800,
 849 MX6_MMDC_P1_MPMUR0, 0x00000800,
 850 MX6_MMDC_P0_MDSCR, 0x00000000,
 851 MX6_MMDC_P0_MAPSR, 0x00011006,
 852 };
 853
 854 static int mx6dl_dcd_table[] = {
 855 /* ddr-setup.cfg */
 856
 857 MX6_IOM_DRAM_SDQS0, 0x00000030,
 858 MX6_IOM_DRAM_SDQS1, 0x00000030,
 859 MX6_IOM_DRAM_SDQS2, 0x00000030,
 860 MX6_IOM_DRAM_SDQS3, 0x00000030,
 861 MX6_IOM_DRAM_SDQS4, 0x00000030,
 862 MX6_IOM_DRAM_SDQS5, 0x00000030,
 863 MX6_IOM_DRAM_SDQS6, 0x00000030,
 864 MX6_IOM_DRAM_SDQS7, 0x00000030,
 865
 866 MX6_IOM_GRP_B0DS, 0x00000030,
 867 MX6_IOM_GRP_B1DS, 0x00000030,
 868 MX6_IOM_GRP_B2DS, 0x00000030,
 869 MX6_IOM_GRP_B3DS, 0x00000030,
 870 MX6_IOM_GRP_B4DS, 0x00000030,
 871 MX6_IOM_GRP_B5DS, 0x00000030,
 872 MX6_IOM_GRP_B6DS, 0x00000030,
 873 MX6_IOM_GRP_B7DS, 0x00000030,
 874 MX6_IOM_GRP_ADDDS, 0x00000030,
 875 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 876 MX6_IOM_GRP_CTLDS, 0x00000030,
 877
 878 MX6_IOM_DRAM_DQM0, 0x00020030,
 879 MX6_IOM_DRAM_DQM1, 0x00020030,
 880 MX6_IOM_DRAM_DQM2, 0x00020030,
 881 MX6_IOM_DRAM_DQM3, 0x00020030,
 882 MX6_IOM_DRAM_DQM4, 0x00020030,
 883 MX6_IOM_DRAM_DQM5, 0x00020030,
 884 MX6_IOM_DRAM_DQM6, 0x00020030,
 885 MX6_IOM_DRAM_DQM7, 0x00020030,
 886
 887 MX6_IOM_DRAM_CAS, 0x00020030,
 888 MX6_IOM_DRAM_RAS, 0x00020030,
 889 MX6_IOM_DRAM_SDCLK_0, 0x00020030,
 890 MX6_IOM_DRAM_SDCLK_1, 0x00020030,
 891
 892 MX6_IOM_DRAM_RESET, 0x00020030,
 893 MX6_IOM_DRAM_SDCKE0, 0x00003000,
 894 MX6_IOM_DRAM_SDCKE1, 0x00003000,
 895
 896 MX6_IOM_DRAM_SDODT0, 0x00003030,
 897 MX6_IOM_DRAM_SDODT1, 0x00003030,
 898
 899 /* (differential input) */
 900 MX6_IOM_DDRMODE_CTL, 0x00020000,
 901 /* (differential input) */
 902 MX6_IOM_GRP_DDRMODE, 0x00020000,
 903 /* disable ddr pullups */
 904 MX6_IOM_GRP_DDRPKE, 0x00000000,
 905 MX6_IOM_DRAM_SDBA2, 0x00000000,
 906 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 907 MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
 908
 909 /* Read data DQ Byte0-3 delay */
 910 MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
 911 MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
 912 MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
 913 MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
 914 MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
 915 MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
 916 MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
 917 MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
 918
 919 /*
 920  * MDMISC       mirroring       interleaved (row/bank/col)
 921  */
 922 /* TODO: check what the RALAT field does */
 923 MX6_MMDC_P0_MDMISC, 0x00081740,
 924
 925 /*
 926  * MDSCR        con_req
 927  */
 928 MX6_MMDC_P0_MDSCR, 0x00008000,
 929
 930
 931 /* 800mhz_2x64mx16.cfg */
 932
 933 MX6_MMDC_P0_MDPDC, 0x0002002D,
 934 MX6_MMDC_P0_MDCFG0, 0x2C305503,
 935 MX6_MMDC_P0_MDCFG1, 0xB66D8D63,
 936 MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
 937 MX6_MMDC_P0_MDRWD, 0x000026D2,
 938 MX6_MMDC_P0_MDOR, 0x00301023,
 939 MX6_MMDC_P0_MDOTC, 0x00333030,
 940 MX6_MMDC_P0_MDPDC, 0x0002556D,
 941 /* CS0 End: 7MSB of ((0x10000000, + 512M) -1) >> 25 */
 942 MX6_MMDC_P0_MDASP, 0x00000017,
 943 /* DDR3 DATA BUS SIZE: 64BIT */
 944 MX6_MMDC_P0_MDCTL, 0x821A0000,
 945 /* DDR3 DATA BUS SIZE: 32BIT */
 946 /* MX6_MMDC_P0_MDCTL, 0x82190000, */
 947
 948 /* Write commands to DDR */
 949 /* Load Mode Registers */
 950 /* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
 951 /* MX6_MMDC_P0_MDSCR, 0x04408032, */
 952 MX6_MMDC_P0_MDSCR, 0x04008032,
 953 MX6_MMDC_P0_MDSCR, 0x00008033,
 954 MX6_MMDC_P0_MDSCR, 0x00048031,
 955 MX6_MMDC_P0_MDSCR, 0x13208030,
 956 /* ZQ calibration */
 957 MX6_MMDC_P0_MDSCR, 0x04008040,
 958
 959 MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
 960 MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
 961 MX6_MMDC_P0_MDREF, 0x00005800,
 962
 963 MX6_MMDC_P0_MPODTCTRL, 0x00000000,
 964 MX6_MMDC_P1_MPODTCTRL, 0x00000000,
 965
 966 MX6_MMDC_P0_MPDGCTRL0, 0x42360232,
 967 MX6_MMDC_P0_MPDGCTRL1, 0x021F022A,
 968 MX6_MMDC_P1_MPDGCTRL0, 0x421E0224,
 969 MX6_MMDC_P1_MPDGCTRL1, 0x02110218,
 970
 971 MX6_MMDC_P0_MPRDDLCTL, 0x41434344,
 972 MX6_MMDC_P1_MPRDDLCTL, 0x4345423E,
 973 MX6_MMDC_P0_MPWRDLCTL, 0x39383339,
 974 MX6_MMDC_P1_MPWRDLCTL, 0x3E363930,
 975
 976 MX6_MMDC_P0_MPWLDECTRL0, 0x00340039,
 977 MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D,
 978 MX6_MMDC_P1_MPWLDECTRL0, 0x00120019,
 979 MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D,
 980
 981 MX6_MMDC_P0_MPMUR0, 0x00000800,
 982 MX6_MMDC_P1_MPMUR0, 0x00000800,
 983 MX6_MMDC_P0_MDSCR, 0x00000000,
 984 MX6_MMDC_P0_MAPSR, 0x00011006,
 985 };
 986
 987 static void ccgr_init(void)
 988 {
 989         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 990
 991         writel(0x00C03F3F, &ccm->CCGR0);
 992         writel(0x0030FC03, &ccm->CCGR1);
 993         writel(0x0FFFFFF3, &ccm->CCGR2);
 994         writel(0x3FF0300F, &ccm->CCGR3);
 995         writel(0x00FFF300, &ccm->CCGR4);
 996         writel(0x0F0000F3, &ccm->CCGR5);
 997         writel(0x000003FF, &ccm->CCGR6);
 998
 999 /*
1000  * Setup CCM_CCOSR register as follows:
1001  *
1002  * cko1_en  = 1    --> CKO1 enabled
1003  * cko1_div = 111  --> divide by 8
1004  * cko1_sel = 1011 --> ahb_clk_root
1005  *
1006  * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
1007  */
1008         writel(0x000000FB, &ccm->ccosr);
1009 }
1010
1011 static void ddr_init(int *table, int size)
1012 {
1013         int i;
1014
1015         for (i = 0; i < size / 2 ; i++)
1016                 writel(table[2 * i + 1], table[2 * i]);
1017 }
1018
1019 static void spl_dram_init(void)
1020 {
1021         int minc, maxc;
1022
1023         switch (get_cpu_temp_grade(&minc, &maxc)) {
1024         case TEMP_COMMERCIAL:
1025         case TEMP_EXTCOMMERCIAL:
1026                 if (is_cpu_type(MXC_CPU_MX6DL)) {
1027                         puts("Commercial temperature grade DDR3 timings, 64bit bus width.\n");
1028                         ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
1029                 } else {
1030                         puts("Commercial temperature grade DDR3 timings, 32bit bus width.\n");
1031                         ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
1032                 }
1033                 break;
1034         case TEMP_INDUSTRIAL:
1035         case TEMP_AUTOMOTIVE:
1036         default:
1037                 if (is_cpu_type(MXC_CPU_MX6DL)) {
1038                         ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
1039                 } else {
1040                         puts("Industrial temperature grade DDR3 timings, 32bit bus width.\n");
1041                         ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
1042                 }
1043                 break;
1044         };
1045         udelay(100);
1046 }
1047
1048 void board_init_f(ulong dummy)
1049 {
1050         /* setup AIPS and disable watchdog */
1051         arch_cpu_init();
1052
1053         ccgr_init();
1054         gpr_init();
1055
1056         /* iomux */
1057         board_early_init_f();
1058
1059         /* setup GP timer */
1060         timer_init();
1061
1062         /* UART clocks enabled and gd valid - init serial console */
1063         preloader_console_init();
1064
1065         /* Make sure we use dte mode */
1066         setup_dtemode_uart();
1067
1068         /* DDR initialization */
1069         spl_dram_init();
1070
1071         /* Clear the BSS. */
1072         memset(__bss_start, 0, __bss_end - __bss_start);
1073
1074         /* load/boot image from boot device */
1075         board_init_r(NULL, 0);
1076 }
1077
1078 void reset_cpu(ulong addr)
1079 {
1080 }
1081
1082 #endif /* CONFIG_SPL_BUILD */
1083
1084 static struct mxc_serial_platdata mxc_serial_plat = {
1085         .reg = (struct mxc_uart *)UART1_BASE,
1086         .use_dte = true,
1087 };
1088
1089 U_BOOT_DEVICE(mxc_serial) = {
1090         .name = "serial_mxc",
1091         .platdata = &mxc_serial_plat,
1092 };