board/toradex/colibri_imx6/colibri_imx6.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
   4  * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
   5  * Copyright (C) 2014-2019, Toradex AG
   6  * copied from nitrogen6x
   7  */
   8
   9 #include <common.h>
  10 #include <cpu_func.h>
  11 #include <dm.h>
  12 #include <env.h>
  13 #include <init.h>
  14 #include <net.h>
  15 #include <linux/bitops.h>
  16 #include <linux/delay.h>
  17
  18 #include <asm/arch/clock.h>
  19 #include <asm/arch/crm_regs.h>
  20 #include <asm/arch/imx-regs.h>
  21 #include <asm/arch/mx6-ddr.h>
  22 #include <asm/arch/mx6-pins.h>
  23 #include <asm/arch/mxc_hdmi.h>
  24 #include <asm/arch/sys_proto.h>
  25 #include <asm/bootm.h>
  26 #include <asm/gpio.h>
  27 #include <asm/mach-imx/boot_mode.h>
  28 #include <asm/mach-imx/iomux-v3.h>
  29 #include <asm/mach-imx/sata.h>
  30 #include <asm/mach-imx/video.h>
  31 #include <cpu.h>
  32 #include <dm/platform_data/serial_mxc.h>
  33 #include <fsl_esdhc_imx.h>
  34 #include <imx_thermal.h>
  35 #include <miiphy.h>
  36 #include <netdev.h>
  37 #include <cpu.h>
  38
  39 #include "../common/tdx-cfg-block.h"
  40 #ifdef CONFIG_TDX_CMD_IMX_MFGR
  41 #include "pf0100.h"
  42 #endif
  43
  44 DECLARE_GLOBAL_DATA_PTR;
  45
  46 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  47         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  48         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  49
  50 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  51         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm |                 \
  52         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  53
  54 #define USDHC_EMMC_PAD_CTRL (PAD_CTL_PUS_47K_UP |               \
  55         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  56         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  57
  58 #define WEAK_PULLUP     (PAD_CTL_PUS_100K_UP |                  \
  59         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  60         PAD_CTL_SRE_SLOW)
  61
  62 #define NO_PULLUP       (                                       \
  63         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  64         PAD_CTL_SRE_SLOW)
  65
  66 #define WEAK_PULLDOWN   (PAD_CTL_PUS_100K_DOWN |                \
  67         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  68         PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
  69
  70 #define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST)
  71
  72 int dram_init(void)
  73 {
  74         /* use the DDR controllers configured size */
  75         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  76                                     (ulong)imx_ddr_size());
  77
  78         return 0;
  79 }
  80
  81 /* Colibri UARTA */
  82 iomux_v3_cfg_t const uart1_pads[] = {
  83         MX6_PAD_CSI0_DAT10__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  84         MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  85 };
  86
  87 #if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
  88 /* Colibri MMC */
  89 iomux_v3_cfg_t const usdhc1_pads[] = {
  90         MX6_PAD_SD1_CLK__SD1_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  91         MX6_PAD_SD1_CMD__SD1_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  92         MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  93         MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  94         MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  95         MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  96         MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
  97 #       define GPIO_MMC_CD IMX_GPIO_NR(2, 5)
  98 };
  99
 100 /* eMMC */
 101 iomux_v3_cfg_t const usdhc3_pads[] = {
 102         MX6_PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 103         MX6_PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 104         MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 105         MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 106         MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 107         MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 108         MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 109         MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 110         MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 111         MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 112         MX6_PAD_SD3_RST__SD3_RESET  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 113 };
 114 #endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
 115
 116 /* mux auxiliary pins to GPIO, so they can be used from the U-Boot cmdline */
 117 iomux_v3_cfg_t const gpio_pads[] = {
 118         /* ADDRESS[17:18] [25] used as GPIO */
 119         MX6_PAD_KEY_ROW2__GPIO4_IO11    | MUX_PAD_CTRL(WEAK_PULLUP) |
 120                                           MUX_MODE_SION,
 121         MX6_PAD_KEY_COL2__GPIO4_IO10    | MUX_PAD_CTRL(WEAK_PULLUP) |
 122                                           MUX_MODE_SION,
 123         MX6_PAD_NANDF_D1__GPIO2_IO01    | MUX_PAD_CTRL(WEAK_PULLUP) |
 124                                           MUX_MODE_SION,
 125         /* ADDRESS[19:24] used as GPIO */
 126         MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(WEAK_PULLUP) |
 127                                           MUX_MODE_SION,
 128         MX6_PAD_DISP0_DAT22__GPIO5_IO16 | MUX_PAD_CTRL(WEAK_PULLUP) |
 129                                           MUX_MODE_SION,
 130         MX6_PAD_DISP0_DAT21__GPIO5_IO15 | MUX_PAD_CTRL(WEAK_PULLUP) |
 131                                           MUX_MODE_SION,
 132         MX6_PAD_DISP0_DAT20__GPIO5_IO14 | MUX_PAD_CTRL(WEAK_PULLUP) |
 133                                           MUX_MODE_SION,
 134         MX6_PAD_DISP0_DAT19__GPIO5_IO13 | MUX_PAD_CTRL(WEAK_PULLUP) |
 135                                           MUX_MODE_SION,
 136         MX6_PAD_DISP0_DAT18__GPIO5_IO12 | MUX_PAD_CTRL(WEAK_PULLUP) |
 137                                           MUX_MODE_SION,
 138         /* DATA[16:29] [31]      used as GPIO */
 139         MX6_PAD_EIM_LBA__GPIO2_IO27     | MUX_PAD_CTRL(WEAK_PULLUP) |
 140                                           MUX_MODE_SION,
 141         MX6_PAD_EIM_BCLK__GPIO6_IO31    | MUX_PAD_CTRL(WEAK_PULLUP) |
 142                                           MUX_MODE_SION,
 143         MX6_PAD_NANDF_CS3__GPIO6_IO16   | MUX_PAD_CTRL(WEAK_PULLUP) |
 144                                           MUX_MODE_SION,
 145         MX6_PAD_NANDF_CS1__GPIO6_IO14   | MUX_PAD_CTRL(WEAK_PULLUP) |
 146                                           MUX_MODE_SION,
 147         MX6_PAD_NANDF_RB0__GPIO6_IO10   | MUX_PAD_CTRL(WEAK_PULLUP) |
 148                                           MUX_MODE_SION,
 149         MX6_PAD_NANDF_ALE__GPIO6_IO08   | MUX_PAD_CTRL(WEAK_PULLUP) |
 150                                           MUX_MODE_SION,
 151         MX6_PAD_NANDF_WP_B__GPIO6_IO09  | MUX_PAD_CTRL(WEAK_PULLUP) |
 152                                           MUX_MODE_SION,
 153         MX6_PAD_NANDF_CS0__GPIO6_IO11   | MUX_PAD_CTRL(WEAK_PULLUP) |
 154                                           MUX_MODE_SION,
 155         MX6_PAD_NANDF_CLE__GPIO6_IO07   | MUX_PAD_CTRL(WEAK_PULLUP) |
 156                                           MUX_MODE_SION,
 157         MX6_PAD_GPIO_19__GPIO4_IO05     | MUX_PAD_CTRL(WEAK_PULLUP) |
 158                                           MUX_MODE_SION,
 159         MX6_PAD_CSI0_MCLK__GPIO5_IO19   | MUX_PAD_CTRL(WEAK_PULLUP) |
 160                                           MUX_MODE_SION,
 161         MX6_PAD_CSI0_PIXCLK__GPIO5_IO18 | MUX_PAD_CTRL(WEAK_PULLUP) |
 162                                           MUX_MODE_SION,
 163         MX6_PAD_GPIO_4__GPIO1_IO04      | MUX_PAD_CTRL(WEAK_PULLUP) |
 164                                           MUX_MODE_SION,
 165         MX6_PAD_GPIO_5__GPIO1_IO05      | MUX_PAD_CTRL(WEAK_PULLUP) |
 166                                           MUX_MODE_SION,
 167         MX6_PAD_GPIO_2__GPIO1_IO02      | MUX_PAD_CTRL(WEAK_PULLUP) |
 168                                           MUX_MODE_SION,
 169         /* DQM[0:3]      used as GPIO */
 170         MX6_PAD_EIM_EB0__GPIO2_IO28     | MUX_PAD_CTRL(WEAK_PULLUP) |
 171                                           MUX_MODE_SION,
 172         MX6_PAD_EIM_EB1__GPIO2_IO29     | MUX_PAD_CTRL(WEAK_PULLUP) |
 173                                           MUX_MODE_SION,
 174         MX6_PAD_SD2_DAT2__GPIO1_IO13    | MUX_PAD_CTRL(WEAK_PULLUP) |
 175                                           MUX_MODE_SION,
 176         MX6_PAD_NANDF_D0__GPIO2_IO00    | MUX_PAD_CTRL(WEAK_PULLUP) |
 177                                           MUX_MODE_SION,
 178         /* RDY  used as GPIO */
 179         MX6_PAD_EIM_WAIT__GPIO5_IO00    | MUX_PAD_CTRL(WEAK_PULLUP) |
 180                                           MUX_MODE_SION,
 181         /* ADDRESS[16] DATA[30]  used as GPIO */
 182         MX6_PAD_KEY_ROW4__GPIO4_IO15    | MUX_PAD_CTRL(WEAK_PULLDOWN) |
 183                                           MUX_MODE_SION,
 184         MX6_PAD_KEY_COL4__GPIO4_IO14    | MUX_PAD_CTRL(WEAK_PULLUP) |
 185                                           MUX_MODE_SION,
 186         /* CSI pins used as GPIO */
 187         MX6_PAD_EIM_A24__GPIO5_IO04     | MUX_PAD_CTRL(WEAK_PULLUP) |
 188                                           MUX_MODE_SION,
 189         MX6_PAD_SD2_CMD__GPIO1_IO11     | MUX_PAD_CTRL(WEAK_PULLUP) |
 190                                           MUX_MODE_SION,
 191         MX6_PAD_NANDF_CS2__GPIO6_IO15   | MUX_PAD_CTRL(WEAK_PULLUP) |
 192                                           MUX_MODE_SION,
 193         MX6_PAD_EIM_D18__GPIO3_IO18     | MUX_PAD_CTRL(WEAK_PULLUP) |
 194                                           MUX_MODE_SION,
 195         MX6_PAD_EIM_A19__GPIO2_IO19     | MUX_PAD_CTRL(WEAK_PULLUP) |
 196                                           MUX_MODE_SION,
 197         MX6_PAD_EIM_D29__GPIO3_IO29     | MUX_PAD_CTRL(WEAK_PULLDOWN) |
 198                                           MUX_MODE_SION,
 199         MX6_PAD_EIM_A23__GPIO6_IO06     | MUX_PAD_CTRL(WEAK_PULLUP) |
 200                                           MUX_MODE_SION,
 201         MX6_PAD_EIM_A20__GPIO2_IO18     | MUX_PAD_CTRL(WEAK_PULLUP) |
 202                                           MUX_MODE_SION,
 203         MX6_PAD_EIM_A17__GPIO2_IO21     | MUX_PAD_CTRL(WEAK_PULLUP) |
 204                                           MUX_MODE_SION,
 205         MX6_PAD_EIM_A18__GPIO2_IO20     | MUX_PAD_CTRL(WEAK_PULLUP) |
 206                                           MUX_MODE_SION,
 207         MX6_PAD_EIM_EB3__GPIO2_IO31     | MUX_PAD_CTRL(WEAK_PULLUP) |
 208                                           MUX_MODE_SION,
 209         MX6_PAD_EIM_D17__GPIO3_IO17     | MUX_PAD_CTRL(WEAK_PULLUP) |
 210                                           MUX_MODE_SION,
 211         MX6_PAD_SD2_DAT0__GPIO1_IO15    | MUX_PAD_CTRL(WEAK_PULLUP) |
 212                                           MUX_MODE_SION,
 213         /* GPIO */
 214         MX6_PAD_EIM_D26__GPIO3_IO26     | MUX_PAD_CTRL(WEAK_PULLUP) |
 215                                           MUX_MODE_SION,
 216         MX6_PAD_EIM_D27__GPIO3_IO27     | MUX_PAD_CTRL(WEAK_PULLUP) |
 217                                           MUX_MODE_SION,
 218         MX6_PAD_NANDF_D6__GPIO2_IO06    | MUX_PAD_CTRL(WEAK_PULLUP) |
 219                                           MUX_MODE_SION,
 220         MX6_PAD_NANDF_D3__GPIO2_IO03    | MUX_PAD_CTRL(WEAK_PULLUP) |
 221                                           MUX_MODE_SION,
 222         MX6_PAD_ENET_REF_CLK__GPIO1_IO23 | MUX_PAD_CTRL(WEAK_PULLUP) |
 223                                           MUX_MODE_SION,
 224         MX6_PAD_DI0_PIN4__GPIO4_IO20    | MUX_PAD_CTRL(WEAK_PULLUP) |
 225                                           MUX_MODE_SION,
 226         MX6_PAD_SD4_DAT3__GPIO2_IO11    | MUX_PAD_CTRL(WEAK_PULLUP) |
 227                                           MUX_MODE_SION,
 228         MX6_PAD_NANDF_D4__GPIO2_IO04    | MUX_PAD_CTRL(WEAK_PULLUP) |
 229                                           MUX_MODE_SION,
 230         MX6_PAD_SD4_DAT0__GPIO2_IO08    | MUX_PAD_CTRL(WEAK_PULLUP) |
 231                                           MUX_MODE_SION,
 232         MX6_PAD_GPIO_7__GPIO1_IO07      | MUX_PAD_CTRL(WEAK_PULLUP) |
 233                                           MUX_MODE_SION,
 234         MX6_PAD_GPIO_8__GPIO1_IO08      | MUX_PAD_CTRL(WEAK_PULLUP) |
 235                                           MUX_MODE_SION,
 236         /* USBH_OC */
 237         MX6_PAD_EIM_D30__GPIO3_IO30     | MUX_PAD_CTRL(WEAK_PULLUP),
 238         /* USBC_ID */
 239         MX6_PAD_NANDF_D2__GPIO2_IO02    | MUX_PAD_CTRL(WEAK_PULLUP),
 240         /* USBC_DET */
 241         MX6_PAD_GPIO_17__GPIO7_IO12     | MUX_PAD_CTRL(WEAK_PULLUP),
 242 };
 243
 244 static void setup_iomux_gpio(void)
 245 {
 246         imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
 247 }
 248
 249 iomux_v3_cfg_t const usb_pads[] = {
 250         /* USBH_PEN */
 251         MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
 252 #       define GPIO_USBH_EN IMX_GPIO_NR(3, 31)
 253 };
 254
 255 /*
 256  * UARTs are used in DTE mode, switch the mode on all UARTs before
 257  * any pinmuxing connects a (DCE) output to a transceiver output.
 258  */
 259 #define UCR3            0x88    /* FIFO Control Register */
 260 #define UCR3_RI         BIT(8)  /* RIDELT DTE mode */
 261 #define UCR3_DCD        BIT(9)  /* DCDDELT DTE mode */
 262 #define UFCR            0x90    /* FIFO Control Register */
 263 #define UFCR_DCEDTE     BIT(6)  /* DCE=0 */
 264
 265 static void setup_dtemode_uart(void)
 266 {
 267         setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
 268         setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
 269         setbits_le32((u32 *)(UART3_BASE + UFCR), UFCR_DCEDTE);
 270
 271         clrbits_le32((u32 *)(UART1_BASE + UCR3), UCR3_DCD | UCR3_RI);
 272         clrbits_le32((u32 *)(UART2_BASE + UCR3), UCR3_DCD | UCR3_RI);
 273         clrbits_le32((u32 *)(UART3_BASE + UCR3), UCR3_DCD | UCR3_RI);
 274 }
 275
 276 static void setup_iomux_uart(void)
 277 {
 278         setup_dtemode_uart();
 279         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 280 }
 281
 282 #ifdef CONFIG_USB_EHCI_MX6
 283 int board_ehci_hcd_init(int port)
 284 {
 285         imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
 286         return 0;
 287 }
 288 #endif
 289
 290 #if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
 291 /* use the following sequence: eMMC, MMC */
 292 struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
 293         {USDHC3_BASE_ADDR},
 294         {USDHC1_BASE_ADDR},
 295 };
 296
 297 int board_mmc_getcd(struct mmc *mmc)
 298 {
 299         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 300         int ret = true; /* default: assume inserted */
 301
 302         switch (cfg->esdhc_base) {
 303         case USDHC1_BASE_ADDR:
 304                 gpio_request(GPIO_MMC_CD, "MMC_CD");
 305                 gpio_direction_input(GPIO_MMC_CD);
 306                 ret = !gpio_get_value(GPIO_MMC_CD);
 307                 break;
 308         }
 309
 310         return ret;
 311 }
 312
 313 int board_mmc_init(bd_t *bis)
 314 {
 315         struct src *psrc = (struct src *)SRC_BASE_ADDR;
 316         unsigned reg = readl(&psrc->sbmr1) >> 11;
 317         /*
 318          * Upon reading BOOT_CFG register the following map is done:
 319          * Bit 11 and 12 of BOOT_CFG register can determine the current
 320          * mmc port
 321          * 0x1                  SD1
 322          * 0x2                  SD2
 323          * 0x3                  SD4
 324          */
 325
 326         switch (reg & 0x3) {
 327         case 0x0:
 328                 imx_iomux_v3_setup_multiple_pads(
 329                         usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
 330                 usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
 331                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 332                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 333                 break;
 334         case 0x2:
 335                 imx_iomux_v3_setup_multiple_pads(
 336                         usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 337                 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
 338                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 339                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 340                 break;
 341         default:
 342                 puts("MMC boot device not available");
 343         }
 344
 345         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 346 }
 347 #endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
 348
 349 int board_phy_config(struct phy_device *phydev)
 350 {
 351         if (phydev->drv->config)
 352                 phydev->drv->config(phydev);
 353
 354         return 0;
 355 }
 356
 357 int setup_fec(void)
 358 {
 359         int ret;
 360         struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 361
 362         /* provide the PHY clock from the i.MX 6 */
 363         ret = enable_fec_anatop_clock(0, ENET_50MHZ);
 364         if (ret)
 365                 return ret;
 366
 367         setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
 368
 369         return 0;
 370 }
 371
 372 static iomux_v3_cfg_t const pwr_intb_pads[] = {
 373         /*
 374          * the bootrom sets the iomux to vselect, potentially connecting
 375          * two outputs. Set this back to GPIO
 376          */
 377         MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)
 378 };
 379
 380 #if defined(CONFIG_VIDEO_IPUV3)
 381
 382 static iomux_v3_cfg_t const backlight_pads[] = {
 383         /* Backlight On */
 384         MX6_PAD_EIM_D26__GPIO3_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
 385 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 26)
 386         /* Backlight PWM, used as GPIO in U-Boot */
 387         MX6_PAD_EIM_A22__GPIO2_IO16  | MUX_PAD_CTRL(NO_PULLUP),
 388         MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL) |
 389                                        MUX_MODE_SION,
 390 #define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 9)
 391 };
 392
 393 static iomux_v3_cfg_t const rgb_pads[] = {
 394         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(OUTPUT_RGB),
 395         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(OUTPUT_RGB),
 396         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(OUTPUT_RGB),
 397         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(OUTPUT_RGB),
 398         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(OUTPUT_RGB),
 399         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(OUTPUT_RGB),
 400         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(OUTPUT_RGB),
 401         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(OUTPUT_RGB),
 402         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(OUTPUT_RGB),
 403         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(OUTPUT_RGB),
 404         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(OUTPUT_RGB),
 405         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(OUTPUT_RGB),
 406         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(OUTPUT_RGB),
 407         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(OUTPUT_RGB),
 408         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(OUTPUT_RGB),
 409         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(OUTPUT_RGB),
 410         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(OUTPUT_RGB),
 411         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(OUTPUT_RGB),
 412         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(OUTPUT_RGB),
 413         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(OUTPUT_RGB),
 414         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(OUTPUT_RGB),
 415         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(OUTPUT_RGB),
 416 };
 417
 418 static void do_enable_hdmi(struct display_info_t const *dev)
 419 {
 420         imx_enable_hdmi_phy();
 421 }
 422
 423 static void enable_rgb(struct display_info_t const *dev)
 424 {
 425         imx_iomux_v3_setup_multiple_pads(
 426                 rgb_pads,
 427                 ARRAY_SIZE(rgb_pads));
 428         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 429         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
 430 }
 431
 432 static int detect_default(struct display_info_t const *dev)
 433 {
 434         (void) dev;
 435         return 1;
 436 }
 437
 438 struct display_info_t const displays[] = {{
 439         .bus    = -1,
 440         .addr   = 0,
 441         .pixfmt = IPU_PIX_FMT_RGB24,
 442         .detect = detect_hdmi,
 443         .enable = do_enable_hdmi,
 444         .mode   = {
 445                 .name           = "HDMI",
 446                 .refresh        = 60,
 447                 .xres           = 1024,
 448                 .yres           = 768,
 449                 .pixclock       = 15385,
 450                 .left_margin    = 220,
 451                 .right_margin   = 40,
 452                 .upper_margin   = 21,
 453                 .lower_margin   = 7,
 454                 .hsync_len      = 60,
 455                 .vsync_len      = 10,
 456                 .sync           = FB_SYNC_EXT,
 457                 .vmode          = FB_VMODE_NONINTERLACED
 458 } }, {
 459         .bus    = -1,
 460         .addr   = 0,
 461         .pixfmt = IPU_PIX_FMT_RGB666,
 462         .detect = detect_default,
 463         .enable = enable_rgb,
 464         .mode   = {
 465                 .name           = "vga-rgb",
 466                 .refresh        = 60,
 467                 .xres           = 640,
 468                 .yres           = 480,
 469                 .pixclock       = 33000,
 470                 .left_margin    = 48,
 471                 .right_margin   = 16,
 472                 .upper_margin   = 31,
 473                 .lower_margin   = 11,
 474                 .hsync_len      = 96,
 475                 .vsync_len      = 2,
 476                 .sync           = 0,
 477                 .vmode          = FB_VMODE_NONINTERLACED
 478 } }, {
 479         .bus    = -1,
 480         .addr   = 0,
 481         .pixfmt = IPU_PIX_FMT_RGB666,
 482         .enable = enable_rgb,
 483         .mode   = {
 484                 .name           = "wvga-rgb",
 485                 .refresh        = 60,
 486                 .xres           = 800,
 487                 .yres           = 480,
 488                 .pixclock       = 25000,
 489                 .left_margin    = 40,
 490                 .right_margin   = 88,
 491                 .upper_margin   = 33,
 492                 .lower_margin   = 10,
 493                 .hsync_len      = 128,
 494                 .vsync_len      = 2,
 495                 .sync           = 0,
 496                 .vmode          = FB_VMODE_NONINTERLACED
 497 } } };
 498 size_t display_count = ARRAY_SIZE(displays);
 499
 500 static void setup_display(void)
 501 {
 502         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 503         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 504         int reg;
 505
 506         enable_ipu_clock();
 507         imx_setup_hdmi();
 508         /* Turn on LDB0,IPU,IPU DI0 clocks */
 509         reg = __raw_readl(&mxc_ccm->CCGR3);
 510         reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
 511         writel(reg, &mxc_ccm->CCGR3);
 512
 513         /* set LDB0, LDB1 clk select to 011/011 */
 514         reg = readl(&mxc_ccm->cs2cdr);
 515         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 516                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 517         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 518               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 519         writel(reg, &mxc_ccm->cs2cdr);
 520
 521         reg = readl(&mxc_ccm->cscmr2);
 522         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 523         writel(reg, &mxc_ccm->cscmr2);
 524
 525         reg = readl(&mxc_ccm->chsccdr);
 526         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 527                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 528         writel(reg, &mxc_ccm->chsccdr);
 529
 530         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 531              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 532              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 533              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 534              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 535              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 536              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 537              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 538              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 539         writel(reg, &iomux->gpr[2]);
 540
 541         reg = readl(&iomux->gpr[3]);
 542         reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
 543                         |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
 544             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 545                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 546         writel(reg, &iomux->gpr[3]);
 547
 548         /* backlight unconditionally on for now */
 549         imx_iomux_v3_setup_multiple_pads(backlight_pads,
 550                                          ARRAY_SIZE(backlight_pads));
 551         /* use 0 for EDT 7", use 1 for LG fullHD panel */
 552         gpio_request(RGB_BACKLIGHTPWM_GP, "PWM<A>");
 553         gpio_request(RGB_BACKLIGHT_GP, "BL_ON");
 554         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
 555         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 556 }
 557
 558 /*
 559  * Backlight off before OS handover
 560  */
 561 void board_preboot_os(void)
 562 {
 563         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 1);
 564         gpio_direction_output(RGB_BACKLIGHT_GP, 0);
 565 }
 566 #endif /* defined(CONFIG_VIDEO_IPUV3) */
 567
 568 int board_early_init_f(void)
 569 {
 570         imx_iomux_v3_setup_multiple_pads(pwr_intb_pads,
 571                                          ARRAY_SIZE(pwr_intb_pads));
 572         setup_iomux_uart();
 573
 574         return 0;
 575 }
 576
 577 /*
 578  * Do not overwrite the console
 579  * Use always serial for U-Boot console
 580  */
 581 int overwrite_console(void)
 582 {
 583         return 1;
 584 }
 585
 586 int board_init(void)
 587 {
 588         /* address of boot parameters */
 589         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 590 #if defined(CONFIG_FEC_MXC)
 591         setup_fec();
 592 #endif
 593 #if defined(CONFIG_VIDEO_IPUV3)
 594         setup_display();
 595 #endif
 596
 597 #ifdef CONFIG_TDX_CMD_IMX_MFGR
 598         (void) pmic_init();
 599 #endif
 600
 601 #ifdef CONFIG_SATA
 602         setup_sata();
 603 #endif
 604
 605         setup_iomux_gpio();
 606
 607         return 0;
 608 }
 609
 610 #ifdef CONFIG_BOARD_LATE_INIT
 611 int board_late_init(void)
 612 {
 613 #if defined(CONFIG_REVISION_TAG) && \
 614     defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
 615         char env_str[256];
 616         u32 rev;
 617
 618         rev = get_board_rev();
 619         snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev);
 620         env_set("board_rev", env_str);
 621 #endif
 622
 623 #ifdef CONFIG_CMD_USB_SDP
 624         if (is_boot_from_usb()) {
 625                 printf("Serial Downloader recovery mode, using sdp command\n");
 626                 env_set("bootdelay", "0");
 627                 env_set("bootcmd", "sdp 0");
 628         }
 629 #endif /* CONFIG_CMD_USB_SDP */
 630
 631         return 0;
 632 }
 633 #endif /* CONFIG_BOARD_LATE_INIT */
 634
 635 int checkboard(void)
 636 {
 637         char it[] = " IT";
 638         int minc, maxc;
 639
 640         switch (get_cpu_temp_grade(&minc, &maxc)) {
 641         case TEMP_AUTOMOTIVE:
 642         case TEMP_INDUSTRIAL:
 643                 break;
 644         case TEMP_EXTCOMMERCIAL:
 645         default:
 646                 it[0] = 0;
 647         };
 648         printf("Model: Toradex Colibri iMX6 %s %sMB%s\n",
 649                is_cpu_type(MXC_CPU_MX6DL) ? "DualLite" : "Solo",
 650                (gd->ram_size == 0x20000000) ? "512" : "256", it);
 651         return 0;
 652 }
 653
 654 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 655 int ft_board_setup(void *blob, bd_t *bd)
 656 {
 657         u32 cma_size;
 658
 659         ft_common_board_setup(blob, bd);
 660
 661         cma_size = env_get_ulong("cma-size", 10, 320 * 1024 * 1024);
 662         cma_size = min((u32)(gd->ram_size >> 1), cma_size);
 663
 664         fdt_setprop_u32(blob,
 665                         fdt_path_offset(blob, "/reserved-memory/linux,cma"),
 666                         "size",
 667                         cma_size);
 668         return 0;
 669 }
 670 #endif
 671
 672 #ifdef CONFIG_CMD_BMODE
 673 static const struct boot_mode board_boot_modes[] = {
 674         {"mmc", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
 675         {NULL,  0},
 676 };
 677 #endif
 678
 679 int misc_init_r(void)
 680 {
 681 #ifdef CONFIG_CMD_BMODE
 682         add_board_boot_modes(board_boot_modes);
 683 #endif
 684         return 0;
 685 }
 686
 687 #ifdef CONFIG_LDO_BYPASS_CHECK
 688 /* TODO, use external pmic, for now always ldo_enable */
 689 void ldo_mode_set(int ldo_bypass)
 690 {
 691         return;
 692 }
 693 #endif
 694
 695 #ifdef CONFIG_SPL_BUILD
 696 #include <spl.h>
 697 #include <linux/libfdt.h>
 698 #include "asm/arch/mx6dl-ddr.h"
 699 #include "asm/arch/iomux.h"
 700 #include "asm/arch/crm_regs.h"
 701
 702 static int mx6s_dcd_table[] = {
 703 /* ddr-setup.cfg */
 704
 705 MX6_IOM_DRAM_SDQS0, 0x00000030,
 706 MX6_IOM_DRAM_SDQS1, 0x00000030,
 707 MX6_IOM_DRAM_SDQS2, 0x00000030,
 708 MX6_IOM_DRAM_SDQS3, 0x00000030,
 709 MX6_IOM_DRAM_SDQS4, 0x00000030,
 710 MX6_IOM_DRAM_SDQS5, 0x00000030,
 711 MX6_IOM_DRAM_SDQS6, 0x00000030,
 712 MX6_IOM_DRAM_SDQS7, 0x00000030,
 713
 714 MX6_IOM_GRP_B0DS, 0x00000030,
 715 MX6_IOM_GRP_B1DS, 0x00000030,
 716 MX6_IOM_GRP_B2DS, 0x00000030,
 717 MX6_IOM_GRP_B3DS, 0x00000030,
 718 MX6_IOM_GRP_B4DS, 0x00000030,
 719 MX6_IOM_GRP_B5DS, 0x00000030,
 720 MX6_IOM_GRP_B6DS, 0x00000030,
 721 MX6_IOM_GRP_B7DS, 0x00000030,
 722 MX6_IOM_GRP_ADDDS, 0x00000030,
 723 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 724 MX6_IOM_GRP_CTLDS, 0x00000030,
 725
 726 MX6_IOM_DRAM_DQM0, 0x00020030,
 727 MX6_IOM_DRAM_DQM1, 0x00020030,
 728 MX6_IOM_DRAM_DQM2, 0x00020030,
 729 MX6_IOM_DRAM_DQM3, 0x00020030,
 730 MX6_IOM_DRAM_DQM4, 0x00020030,
 731 MX6_IOM_DRAM_DQM5, 0x00020030,
 732 MX6_IOM_DRAM_DQM6, 0x00020030,
 733 MX6_IOM_DRAM_DQM7, 0x00020030,
 734
 735 MX6_IOM_DRAM_CAS, 0x00020030,
 736 MX6_IOM_DRAM_RAS, 0x00020030,
 737 MX6_IOM_DRAM_SDCLK_0, 0x00020030,
 738 MX6_IOM_DRAM_SDCLK_1, 0x00020030,
 739
 740 MX6_IOM_DRAM_RESET, 0x00020030,
 741 MX6_IOM_DRAM_SDCKE0, 0x00003000,
 742 MX6_IOM_DRAM_SDCKE1, 0x00003000,
 743
 744 MX6_IOM_DRAM_SDODT0, 0x00003030,
 745 MX6_IOM_DRAM_SDODT1, 0x00003030,
 746
 747 /* (differential input) */
 748 MX6_IOM_DDRMODE_CTL, 0x00020000,
 749 /* (differential input) */
 750 MX6_IOM_GRP_DDRMODE, 0x00020000,
 751 /* disable ddr pullups */
 752 MX6_IOM_GRP_DDRPKE, 0x00000000,
 753 MX6_IOM_DRAM_SDBA2, 0x00000000,
 754 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 755 MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
 756
 757 /* Read data DQ Byte0-3 delay */
 758 MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
 759 MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
 760 MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
 761 MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
 762 MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
 763 MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
 764 MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
 765 MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
 766
 767 /*
 768  * MDMISC       mirroring       interleaved (row/bank/col)
 769  */
 770 /* TODO: check what the RALAT field does */
 771 MX6_MMDC_P0_MDMISC, 0x00081740,
 772
 773 /*
 774  * MDSCR        con_req
 775  */
 776 MX6_MMDC_P0_MDSCR, 0x00008000,
 777
 778
 779 /* 800mhz_2x64mx16.cfg */
 780
 781 MX6_MMDC_P0_MDPDC, 0x0002002D,
 782 MX6_MMDC_P0_MDCFG0, 0x2C305503,
 783 MX6_MMDC_P0_MDCFG1, 0xB66D8D63,
 784 MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
 785 MX6_MMDC_P0_MDRWD, 0x000026D2,
 786 MX6_MMDC_P0_MDOR, 0x00301023,
 787 MX6_MMDC_P0_MDOTC, 0x00333030,
 788 MX6_MMDC_P0_MDPDC, 0x0002556D,
 789 /* CS0 End: 7MSB of ((0x10000000, + 512M) -1) >> 25 */
 790 MX6_MMDC_P0_MDASP, 0x00000017,
 791 /* DDR3 DATA BUS SIZE: 64BIT */
 792 /* MX6_MMDC_P0_MDCTL, 0x821A0000, */
 793 /* DDR3 DATA BUS SIZE: 32BIT */
 794 MX6_MMDC_P0_MDCTL, 0x82190000,
 795
 796 /* Write commands to DDR */
 797 /* Load Mode Registers */
 798 /* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
 799 /* MX6_MMDC_P0_MDSCR, 0x04408032, */
 800 MX6_MMDC_P0_MDSCR, 0x04008032,
 801 MX6_MMDC_P0_MDSCR, 0x00008033,
 802 MX6_MMDC_P0_MDSCR, 0x00048031,
 803 MX6_MMDC_P0_MDSCR, 0x13208030,
 804 /* ZQ calibration */
 805 MX6_MMDC_P0_MDSCR, 0x04008040,
 806
 807 MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
 808 MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
 809 MX6_MMDC_P0_MDREF, 0x00005800,
 810
 811 MX6_MMDC_P0_MPODTCTRL, 0x00000000,
 812 MX6_MMDC_P1_MPODTCTRL, 0x00000000,
 813
 814 MX6_MMDC_P0_MPDGCTRL0, 0x42360232,
 815 MX6_MMDC_P0_MPDGCTRL1, 0x021F022A,
 816 MX6_MMDC_P1_MPDGCTRL0, 0x421E0224,
 817 MX6_MMDC_P1_MPDGCTRL1, 0x02110218,
 818
 819 MX6_MMDC_P0_MPRDDLCTL, 0x41434344,
 820 MX6_MMDC_P1_MPRDDLCTL, 0x4345423E,
 821 MX6_MMDC_P0_MPWRDLCTL, 0x39383339,
 822 MX6_MMDC_P1_MPWRDLCTL, 0x3E363930,
 823
 824 MX6_MMDC_P0_MPWLDECTRL0, 0x00340039,
 825 MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D,
 826 MX6_MMDC_P1_MPWLDECTRL0, 0x00120019,
 827 MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D,
 828
 829 MX6_MMDC_P0_MPMUR0, 0x00000800,
 830 MX6_MMDC_P1_MPMUR0, 0x00000800,
 831 MX6_MMDC_P0_MDSCR, 0x00000000,
 832 MX6_MMDC_P0_MAPSR, 0x00011006,
 833 };
 834
 835 static int mx6dl_dcd_table[] = {
 836 /* ddr-setup.cfg */
 837
 838 MX6_IOM_DRAM_SDQS0, 0x00000030,
 839 MX6_IOM_DRAM_SDQS1, 0x00000030,
 840 MX6_IOM_DRAM_SDQS2, 0x00000030,
 841 MX6_IOM_DRAM_SDQS3, 0x00000030,
 842 MX6_IOM_DRAM_SDQS4, 0x00000030,
 843 MX6_IOM_DRAM_SDQS5, 0x00000030,
 844 MX6_IOM_DRAM_SDQS6, 0x00000030,
 845 MX6_IOM_DRAM_SDQS7, 0x00000030,
 846
 847 MX6_IOM_GRP_B0DS, 0x00000030,
 848 MX6_IOM_GRP_B1DS, 0x00000030,
 849 MX6_IOM_GRP_B2DS, 0x00000030,
 850 MX6_IOM_GRP_B3DS, 0x00000030,
 851 MX6_IOM_GRP_B4DS, 0x00000030,
 852 MX6_IOM_GRP_B5DS, 0x00000030,
 853 MX6_IOM_GRP_B6DS, 0x00000030,
 854 MX6_IOM_GRP_B7DS, 0x00000030,
 855 MX6_IOM_GRP_ADDDS, 0x00000030,
 856 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 857 MX6_IOM_GRP_CTLDS, 0x00000030,
 858
 859 MX6_IOM_DRAM_DQM0, 0x00020030,
 860 MX6_IOM_DRAM_DQM1, 0x00020030,
 861 MX6_IOM_DRAM_DQM2, 0x00020030,
 862 MX6_IOM_DRAM_DQM3, 0x00020030,
 863 MX6_IOM_DRAM_DQM4, 0x00020030,
 864 MX6_IOM_DRAM_DQM5, 0x00020030,
 865 MX6_IOM_DRAM_DQM6, 0x00020030,
 866 MX6_IOM_DRAM_DQM7, 0x00020030,
 867
 868 MX6_IOM_DRAM_CAS, 0x00020030,
 869 MX6_IOM_DRAM_RAS, 0x00020030,
 870 MX6_IOM_DRAM_SDCLK_0, 0x00020030,
 871 MX6_IOM_DRAM_SDCLK_1, 0x00020030,
 872
 873 MX6_IOM_DRAM_RESET, 0x00020030,
 874 MX6_IOM_DRAM_SDCKE0, 0x00003000,
 875 MX6_IOM_DRAM_SDCKE1, 0x00003000,
 876
 877 MX6_IOM_DRAM_SDODT0, 0x00003030,
 878 MX6_IOM_DRAM_SDODT1, 0x00003030,
 879
 880 /* (differential input) */
 881 MX6_IOM_DDRMODE_CTL, 0x00020000,
 882 /* (differential input) */
 883 MX6_IOM_GRP_DDRMODE, 0x00020000,
 884 /* disable ddr pullups */
 885 MX6_IOM_GRP_DDRPKE, 0x00000000,
 886 MX6_IOM_DRAM_SDBA2, 0x00000000,
 887 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 888 MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
 889
 890 /* Read data DQ Byte0-3 delay */
 891 MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
 892 MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
 893 MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
 894 MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
 895 MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
 896 MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
 897 MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
 898 MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
 899
 900 /*
 901  * MDMISC       mirroring       interleaved (row/bank/col)
 902  */
 903 /* TODO: check what the RALAT field does */
 904 MX6_MMDC_P0_MDMISC, 0x00081740,
 905
 906 /*
 907  * MDSCR        con_req
 908  */
 909 MX6_MMDC_P0_MDSCR, 0x00008000,
 910
 911
 912 /* 800mhz_2x64mx16.cfg */
 913
 914 MX6_MMDC_P0_MDPDC, 0x0002002D,
 915 MX6_MMDC_P0_MDCFG0, 0x2C305503,
 916 MX6_MMDC_P0_MDCFG1, 0xB66D8D63,
 917 MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
 918 MX6_MMDC_P0_MDRWD, 0x000026D2,
 919 MX6_MMDC_P0_MDOR, 0x00301023,
 920 MX6_MMDC_P0_MDOTC, 0x00333030,
 921 MX6_MMDC_P0_MDPDC, 0x0002556D,
 922 /* CS0 End: 7MSB of ((0x10000000, + 512M) -1) >> 25 */
 923 MX6_MMDC_P0_MDASP, 0x00000017,
 924 /* DDR3 DATA BUS SIZE: 64BIT */
 925 MX6_MMDC_P0_MDCTL, 0x821A0000,
 926 /* DDR3 DATA BUS SIZE: 32BIT */
 927 /* MX6_MMDC_P0_MDCTL, 0x82190000, */
 928
 929 /* Write commands to DDR */
 930 /* Load Mode Registers */
 931 /* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
 932 /* MX6_MMDC_P0_MDSCR, 0x04408032, */
 933 MX6_MMDC_P0_MDSCR, 0x04008032,
 934 MX6_MMDC_P0_MDSCR, 0x00008033,
 935 MX6_MMDC_P0_MDSCR, 0x00048031,
 936 MX6_MMDC_P0_MDSCR, 0x13208030,
 937 /* ZQ calibration */
 938 MX6_MMDC_P0_MDSCR, 0x04008040,
 939
 940 MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
 941 MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
 942 MX6_MMDC_P0_MDREF, 0x00005800,
 943
 944 MX6_MMDC_P0_MPODTCTRL, 0x00000000,
 945 MX6_MMDC_P1_MPODTCTRL, 0x00000000,
 946
 947 MX6_MMDC_P0_MPDGCTRL0, 0x42360232,
 948 MX6_MMDC_P0_MPDGCTRL1, 0x021F022A,
 949 MX6_MMDC_P1_MPDGCTRL0, 0x421E0224,
 950 MX6_MMDC_P1_MPDGCTRL1, 0x02110218,
 951
 952 MX6_MMDC_P0_MPRDDLCTL, 0x41434344,
 953 MX6_MMDC_P1_MPRDDLCTL, 0x4345423E,
 954 MX6_MMDC_P0_MPWRDLCTL, 0x39383339,
 955 MX6_MMDC_P1_MPWRDLCTL, 0x3E363930,
 956
 957 MX6_MMDC_P0_MPWLDECTRL0, 0x00340039,
 958 MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D,
 959 MX6_MMDC_P1_MPWLDECTRL0, 0x00120019,
 960 MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D,
 961
 962 MX6_MMDC_P0_MPMUR0, 0x00000800,
 963 MX6_MMDC_P1_MPMUR0, 0x00000800,
 964 MX6_MMDC_P0_MDSCR, 0x00000000,
 965 MX6_MMDC_P0_MAPSR, 0x00011006,
 966 };
 967
 968 static void ccgr_init(void)
 969 {
 970         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 971
 972         writel(0x00C03F3F, &ccm->CCGR0);
 973         writel(0x0030FC03, &ccm->CCGR1);
 974         writel(0x0FFFFFF3, &ccm->CCGR2);
 975         writel(0x3FF0300F, &ccm->CCGR3);
 976         writel(0x00FFF300, &ccm->CCGR4);
 977         writel(0x0F0000F3, &ccm->CCGR5);
 978         writel(0x000003FF, &ccm->CCGR6);
 979
 980 /*
 981  * Setup CCM_CCOSR register as follows:
 982  *
 983  * cko1_en  = 1    --> CKO1 enabled
 984  * cko1_div = 111  --> divide by 8
 985  * cko1_sel = 1011 --> ahb_clk_root
 986  *
 987  * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
 988  */
 989         writel(0x000000FB, &ccm->ccosr);
 990 }
 991
 992 static void ddr_init(int *table, int size)
 993 {
 994         int i;
 995
 996         for (i = 0; i < size / 2 ; i++)
 997                 writel(table[2 * i + 1], table[2 * i]);
 998 }
 999
1000 static void spl_dram_init(void)
1001 {
1002         int minc, maxc;
1003
1004         switch (get_cpu_temp_grade(&minc, &maxc)) {
1005         case TEMP_COMMERCIAL:
1006         case TEMP_EXTCOMMERCIAL:
1007                 if (is_cpu_type(MXC_CPU_MX6DL)) {
1008                         puts("Commercial temperature grade DDR3 timings, 64bit bus width.\n");
1009                         ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
1010                 } else {
1011                         puts("Commercial temperature grade DDR3 timings, 32bit bus width.\n");
1012                         ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
1013                 }
1014                 break;
1015         case TEMP_INDUSTRIAL:
1016         case TEMP_AUTOMOTIVE:
1017         default:
1018                 if (is_cpu_type(MXC_CPU_MX6DL)) {
1019                         puts("Industrial temperature grade DDR3 timings, 64bit bus width.\n");
1020                         ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
1021                 } else {
1022                         puts("Industrial temperature grade DDR3 timings, 32bit bus width.\n");
1023                         ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
1024                 }
1025                 break;
1026         };
1027         udelay(100);
1028 }
1029
1030 static iomux_v3_cfg_t const gpio_reset_pad[] = {
1031         MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL) |
1032                                         MUX_MODE_SION
1033 #define GPIO_NRESET IMX_GPIO_NR(6, 27)
1034 };
1035
1036 #define IMX_RESET_CAUSE_POR 0x00011
1037 static void nreset_out(void)
1038 {
1039         int reset_cause = get_imx_reset_cause();
1040
1041         if (reset_cause != IMX_RESET_CAUSE_POR) {
1042                 imx_iomux_v3_setup_multiple_pads(gpio_reset_pad,
1043                                                  ARRAY_SIZE(gpio_reset_pad));
1044                 gpio_direction_output(GPIO_NRESET, 1);
1045                 udelay(100);
1046                 gpio_direction_output(GPIO_NRESET, 0);
1047         }
1048 }
1049
1050 void board_init_f(ulong dummy)
1051 {
1052         /* setup AIPS and disable watchdog */
1053         arch_cpu_init();
1054
1055         ccgr_init();
1056         gpr_init();
1057
1058         /* iomux */
1059         board_early_init_f();
1060
1061         /* setup GP timer */
1062         timer_init();
1063
1064         /* UART clocks enabled and gd valid - init serial console */
1065         preloader_console_init();
1066
1067         /* Make sure we use dte mode */
1068         setup_dtemode_uart();
1069
1070         /* DDR initialization */
1071         spl_dram_init();
1072
1073         /* Clear the BSS. */
1074         memset(__bss_start, 0, __bss_end - __bss_start);
1075
1076         /* Assert nReset_Out */
1077         nreset_out();
1078
1079         /* load/boot image from boot device */
1080         board_init_r(NULL, 0);
1081 }
1082
1083 void reset_cpu(ulong addr)
1084 {
1085 }
1086
1087 #endif /* CONFIG_SPL_BUILD */
1088
1089 static struct mxc_serial_platdata mxc_serial_plat = {
1090         .reg = (struct mxc_uart *)UART1_BASE,
1091         .use_dte = true,
1092 };
1093
1094 U_BOOT_DEVICE(mxc_serial) = {
1095         .name = "serial_mxc",
1096         .platdata = &mxc_serial_plat,
1097 };