board/toradex/colibri_imx6/colibri_imx6.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
   4  * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
   5  * Copyright (C) 2014-2019, Toradex AG
   6  * copied from nitrogen6x
   7  */
   8
   9 #include <common.h>
  10 #include <dm.h>
  11
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/crm_regs.h>
  14 #include <asm/arch/imx-regs.h>
  15 #include <asm/arch/mx6-ddr.h>
  16 #include <asm/arch/mx6-pins.h>
  17 #include <asm/arch/mxc_hdmi.h>
  18 #include <asm/arch/sys_proto.h>
  19 #include <asm/bootm.h>
  20 #include <asm/gpio.h>
  21 #include <asm/mach-imx/boot_mode.h>
  22 #include <asm/mach-imx/iomux-v3.h>
  23 #include <asm/mach-imx/sata.h>
  24 #include <asm/mach-imx/video.h>
  25 #include <dm/platform_data/serial_mxc.h>
  26 #include <environment.h>
  27 #include <fsl_esdhc.h>
  28 #include <imx_thermal.h>
  29 #include <micrel.h>
  30 #include <miiphy.h>
  31 #include <netdev.h>
  32
  33 #include "../common/tdx-cfg-block.h"
  34 #ifdef CONFIG_TDX_CMD_IMX_MFGR
  35 #include "pf0100.h"
  36 #endif
  37
  38 DECLARE_GLOBAL_DATA_PTR;
  39
  40 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  41         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  42         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  43
  44 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  45         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  46         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  47
  48 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  49         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  50
  51 #define WEAK_PULLUP     (PAD_CTL_PUS_100K_UP |                  \
  52         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  53         PAD_CTL_SRE_SLOW)
  54
  55 #define NO_PULLUP       (                                       \
  56         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  57         PAD_CTL_SRE_SLOW)
  58
  59 #define WEAK_PULLDOWN   (PAD_CTL_PUS_100K_DOWN |                \
  60         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  61         PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
  62
  63 #define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST)
  64
  65 int dram_init(void)
  66 {
  67         /* use the DDR controllers configured size */
  68         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  69                                     (ulong)imx_ddr_size());
  70
  71         return 0;
  72 }
  73
  74 /* Colibri UARTA */
  75 iomux_v3_cfg_t const uart1_pads[] = {
  76         MX6_PAD_CSI0_DAT10__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  77         MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  78 };
  79
  80 #if defined(CONFIG_FSL_ESDHC) && defined(CONFIG_SPL_BUILD)
  81 /* Colibri MMC */
  82 iomux_v3_cfg_t const usdhc1_pads[] = {
  83         MX6_PAD_SD1_CLK__SD1_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  84         MX6_PAD_SD1_CMD__SD1_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  85         MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  86         MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  87         MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  88         MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  89         MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
  90 #       define GPIO_MMC_CD IMX_GPIO_NR(2, 5)
  91 };
  92
  93 /* eMMC */
  94 iomux_v3_cfg_t const usdhc3_pads[] = {
  95         MX6_PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  96         MX6_PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  97         MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  98         MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  99         MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 100         MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 101         MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 102         MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 103         MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 104         MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 105         MX6_PAD_SD3_RST__SD3_RESET  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 106 };
 107 #endif /* CONFIG_FSL_ESDHC & CONFIG_SPL_BUILD */
 108
 109 iomux_v3_cfg_t const enet_pads[] = {
 110         MX6_PAD_ENET_MDC__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
 111         MX6_PAD_ENET_MDIO__ENET_MDIO            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 112         MX6_PAD_ENET_RXD0__ENET_RX_DATA0        | MUX_PAD_CTRL(ENET_PAD_CTRL),
 113         MX6_PAD_ENET_RXD1__ENET_RX_DATA1        | MUX_PAD_CTRL(ENET_PAD_CTRL),
 114         MX6_PAD_ENET_RX_ER__ENET_RX_ER          | MUX_PAD_CTRL(ENET_PAD_CTRL),
 115         MX6_PAD_ENET_TX_EN__ENET_TX_EN          | MUX_PAD_CTRL(ENET_PAD_CTRL),
 116         MX6_PAD_ENET_TXD0__ENET_TX_DATA0        | MUX_PAD_CTRL(ENET_PAD_CTRL),
 117         MX6_PAD_ENET_TXD1__ENET_TX_DATA1        | MUX_PAD_CTRL(ENET_PAD_CTRL),
 118         MX6_PAD_ENET_CRS_DV__ENET_RX_EN         | MUX_PAD_CTRL(ENET_PAD_CTRL),
 119         MX6_PAD_GPIO_16__ENET_REF_CLK           | MUX_PAD_CTRL(ENET_PAD_CTRL),
 120 };
 121
 122 static void setup_iomux_enet(void)
 123 {
 124         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
 125 }
 126
 127 /* mux auxiliary pins to GPIO, so they can be used from the U-Boot cmdline */
 128 iomux_v3_cfg_t const gpio_pads[] = {
 129         /* ADDRESS[17:18] [25] used as GPIO */
 130         MX6_PAD_KEY_ROW2__GPIO4_IO11    | MUX_PAD_CTRL(WEAK_PULLUP) |
 131                                           MUX_MODE_SION,
 132         MX6_PAD_KEY_COL2__GPIO4_IO10    | MUX_PAD_CTRL(WEAK_PULLUP) |
 133                                           MUX_MODE_SION,
 134         MX6_PAD_NANDF_D1__GPIO2_IO01    | MUX_PAD_CTRL(WEAK_PULLUP) |
 135                                           MUX_MODE_SION,
 136         /* ADDRESS[19:24] used as GPIO */
 137         MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(WEAK_PULLUP) |
 138                                           MUX_MODE_SION,
 139         MX6_PAD_DISP0_DAT22__GPIO5_IO16 | MUX_PAD_CTRL(WEAK_PULLUP) |
 140                                           MUX_MODE_SION,
 141         MX6_PAD_DISP0_DAT21__GPIO5_IO15 | MUX_PAD_CTRL(WEAK_PULLUP) |
 142                                           MUX_MODE_SION,
 143         MX6_PAD_DISP0_DAT20__GPIO5_IO14 | MUX_PAD_CTRL(WEAK_PULLUP) |
 144                                           MUX_MODE_SION,
 145         MX6_PAD_DISP0_DAT19__GPIO5_IO13 | MUX_PAD_CTRL(WEAK_PULLUP) |
 146                                           MUX_MODE_SION,
 147         MX6_PAD_DISP0_DAT18__GPIO5_IO12 | MUX_PAD_CTRL(WEAK_PULLUP) |
 148                                           MUX_MODE_SION,
 149         /* DATA[16:29] [31]      used as GPIO */
 150         MX6_PAD_EIM_LBA__GPIO2_IO27     | MUX_PAD_CTRL(WEAK_PULLUP) |
 151                                           MUX_MODE_SION,
 152         MX6_PAD_EIM_BCLK__GPIO6_IO31    | MUX_PAD_CTRL(WEAK_PULLUP) |
 153                                           MUX_MODE_SION,
 154         MX6_PAD_NANDF_CS3__GPIO6_IO16   | MUX_PAD_CTRL(WEAK_PULLUP) |
 155                                           MUX_MODE_SION,
 156         MX6_PAD_NANDF_CS1__GPIO6_IO14   | MUX_PAD_CTRL(WEAK_PULLUP) |
 157                                           MUX_MODE_SION,
 158         MX6_PAD_NANDF_RB0__GPIO6_IO10   | MUX_PAD_CTRL(WEAK_PULLUP) |
 159                                           MUX_MODE_SION,
 160         MX6_PAD_NANDF_ALE__GPIO6_IO08   | MUX_PAD_CTRL(WEAK_PULLUP) |
 161                                           MUX_MODE_SION,
 162         MX6_PAD_NANDF_WP_B__GPIO6_IO09  | MUX_PAD_CTRL(WEAK_PULLUP) |
 163                                           MUX_MODE_SION,
 164         MX6_PAD_NANDF_CS0__GPIO6_IO11   | MUX_PAD_CTRL(WEAK_PULLUP) |
 165                                           MUX_MODE_SION,
 166         MX6_PAD_NANDF_CLE__GPIO6_IO07   | MUX_PAD_CTRL(WEAK_PULLUP) |
 167                                           MUX_MODE_SION,
 168         MX6_PAD_GPIO_19__GPIO4_IO05     | MUX_PAD_CTRL(WEAK_PULLUP) |
 169                                           MUX_MODE_SION,
 170         MX6_PAD_CSI0_MCLK__GPIO5_IO19   | MUX_PAD_CTRL(WEAK_PULLUP) |
 171                                           MUX_MODE_SION,
 172         MX6_PAD_CSI0_PIXCLK__GPIO5_IO18 | MUX_PAD_CTRL(WEAK_PULLUP) |
 173                                           MUX_MODE_SION,
 174         MX6_PAD_GPIO_4__GPIO1_IO04      | MUX_PAD_CTRL(WEAK_PULLUP) |
 175                                           MUX_MODE_SION,
 176         MX6_PAD_GPIO_5__GPIO1_IO05      | MUX_PAD_CTRL(WEAK_PULLUP) |
 177                                           MUX_MODE_SION,
 178         MX6_PAD_GPIO_2__GPIO1_IO02      | MUX_PAD_CTRL(WEAK_PULLUP) |
 179                                           MUX_MODE_SION,
 180         /* DQM[0:3]      used as GPIO */
 181         MX6_PAD_EIM_EB0__GPIO2_IO28     | MUX_PAD_CTRL(WEAK_PULLUP) |
 182                                           MUX_MODE_SION,
 183         MX6_PAD_EIM_EB1__GPIO2_IO29     | MUX_PAD_CTRL(WEAK_PULLUP) |
 184                                           MUX_MODE_SION,
 185         MX6_PAD_SD2_DAT2__GPIO1_IO13    | MUX_PAD_CTRL(WEAK_PULLUP) |
 186                                           MUX_MODE_SION,
 187         MX6_PAD_NANDF_D0__GPIO2_IO00    | MUX_PAD_CTRL(WEAK_PULLUP) |
 188                                           MUX_MODE_SION,
 189         /* RDY  used as GPIO */
 190         MX6_PAD_EIM_WAIT__GPIO5_IO00    | MUX_PAD_CTRL(WEAK_PULLUP) |
 191                                           MUX_MODE_SION,
 192         /* ADDRESS[16] DATA[30]  used as GPIO */
 193         MX6_PAD_KEY_ROW4__GPIO4_IO15    | MUX_PAD_CTRL(WEAK_PULLDOWN) |
 194                                           MUX_MODE_SION,
 195         MX6_PAD_KEY_COL4__GPIO4_IO14    | MUX_PAD_CTRL(WEAK_PULLUP) |
 196                                           MUX_MODE_SION,
 197         /* CSI pins used as GPIO */
 198         MX6_PAD_EIM_A24__GPIO5_IO04     | MUX_PAD_CTRL(WEAK_PULLUP) |
 199                                           MUX_MODE_SION,
 200         MX6_PAD_SD2_CMD__GPIO1_IO11     | MUX_PAD_CTRL(WEAK_PULLUP) |
 201                                           MUX_MODE_SION,
 202         MX6_PAD_NANDF_CS2__GPIO6_IO15   | MUX_PAD_CTRL(WEAK_PULLUP) |
 203                                           MUX_MODE_SION,
 204         MX6_PAD_EIM_D18__GPIO3_IO18     | MUX_PAD_CTRL(WEAK_PULLUP) |
 205                                           MUX_MODE_SION,
 206         MX6_PAD_EIM_A19__GPIO2_IO19     | MUX_PAD_CTRL(WEAK_PULLUP) |
 207                                           MUX_MODE_SION,
 208         MX6_PAD_EIM_D29__GPIO3_IO29     | MUX_PAD_CTRL(WEAK_PULLDOWN) |
 209                                           MUX_MODE_SION,
 210         MX6_PAD_EIM_A23__GPIO6_IO06     | MUX_PAD_CTRL(WEAK_PULLUP) |
 211                                           MUX_MODE_SION,
 212         MX6_PAD_EIM_A20__GPIO2_IO18     | MUX_PAD_CTRL(WEAK_PULLUP) |
 213                                           MUX_MODE_SION,
 214         MX6_PAD_EIM_A17__GPIO2_IO21     | MUX_PAD_CTRL(WEAK_PULLUP) |
 215                                           MUX_MODE_SION,
 216         MX6_PAD_EIM_A18__GPIO2_IO20     | MUX_PAD_CTRL(WEAK_PULLUP) |
 217                                           MUX_MODE_SION,
 218         MX6_PAD_EIM_EB3__GPIO2_IO31     | MUX_PAD_CTRL(WEAK_PULLUP) |
 219                                           MUX_MODE_SION,
 220         MX6_PAD_EIM_D17__GPIO3_IO17     | MUX_PAD_CTRL(WEAK_PULLUP) |
 221                                           MUX_MODE_SION,
 222         MX6_PAD_SD2_DAT0__GPIO1_IO15    | MUX_PAD_CTRL(WEAK_PULLUP) |
 223                                           MUX_MODE_SION,
 224         /* GPIO */
 225         MX6_PAD_EIM_D26__GPIO3_IO26     | MUX_PAD_CTRL(WEAK_PULLUP) |
 226                                           MUX_MODE_SION,
 227         MX6_PAD_EIM_D27__GPIO3_IO27     | MUX_PAD_CTRL(WEAK_PULLUP) |
 228                                           MUX_MODE_SION,
 229         MX6_PAD_NANDF_D6__GPIO2_IO06    | MUX_PAD_CTRL(WEAK_PULLUP) |
 230                                           MUX_MODE_SION,
 231         MX6_PAD_NANDF_D3__GPIO2_IO03    | MUX_PAD_CTRL(WEAK_PULLUP) |
 232                                           MUX_MODE_SION,
 233         MX6_PAD_ENET_REF_CLK__GPIO1_IO23 | MUX_PAD_CTRL(WEAK_PULLUP) |
 234                                           MUX_MODE_SION,
 235         MX6_PAD_DI0_PIN4__GPIO4_IO20    | MUX_PAD_CTRL(WEAK_PULLUP) |
 236                                           MUX_MODE_SION,
 237         MX6_PAD_SD4_DAT3__GPIO2_IO11    | MUX_PAD_CTRL(WEAK_PULLUP) |
 238                                           MUX_MODE_SION,
 239         MX6_PAD_NANDF_D4__GPIO2_IO04    | MUX_PAD_CTRL(WEAK_PULLUP) |
 240                                           MUX_MODE_SION,
 241         MX6_PAD_SD4_DAT0__GPIO2_IO08    | MUX_PAD_CTRL(WEAK_PULLUP) |
 242                                           MUX_MODE_SION,
 243         MX6_PAD_GPIO_7__GPIO1_IO07      | MUX_PAD_CTRL(WEAK_PULLUP) |
 244                                           MUX_MODE_SION,
 245         MX6_PAD_GPIO_8__GPIO1_IO08      | MUX_PAD_CTRL(WEAK_PULLUP) |
 246                                           MUX_MODE_SION,
 247         /* USBH_OC */
 248         MX6_PAD_EIM_D30__GPIO3_IO30     | MUX_PAD_CTRL(WEAK_PULLUP),
 249         /* USBC_ID */
 250         MX6_PAD_NANDF_D2__GPIO2_IO02    | MUX_PAD_CTRL(WEAK_PULLUP),
 251         /* USBC_DET */
 252         MX6_PAD_GPIO_17__GPIO7_IO12     | MUX_PAD_CTRL(WEAK_PULLUP),
 253 };
 254
 255 static void setup_iomux_gpio(void)
 256 {
 257         imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
 258 }
 259
 260 iomux_v3_cfg_t const usb_pads[] = {
 261         /* USBH_PEN */
 262         MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
 263 #       define GPIO_USBH_EN IMX_GPIO_NR(3, 31)
 264 };
 265
 266 /*
 267  * UARTs are used in DTE mode, switch the mode on all UARTs before
 268  * any pinmuxing connects a (DCE) output to a transceiver output.
 269  */
 270 #define UFCR            0x90    /* FIFO Control Register */
 271 #define UFCR_DCEDTE     (1<<6)  /* DCE=0 */
 272
 273 static void setup_dtemode_uart(void)
 274 {
 275         setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
 276         setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
 277         setbits_le32((u32 *)(UART3_BASE + UFCR), UFCR_DCEDTE);
 278 }
 279
 280 static void setup_iomux_uart(void)
 281 {
 282         setup_dtemode_uart();
 283         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 284 }
 285
 286 #ifdef CONFIG_USB_EHCI_MX6
 287 int board_ehci_hcd_init(int port)
 288 {
 289         imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
 290         return 0;
 291 }
 292
 293 int board_ehci_power(int port, int on)
 294 {
 295         switch (port) {
 296         case 0:
 297                 /* control OTG power */
 298                 /* No special PE for USBC, always on when ID pin signals
 299                    host mode */
 300                 break;
 301         case 1:
 302                 /* Control MXM USBH */
 303                 /* Set MXM USBH power enable, '0' means on */
 304                 gpio_request(GPIO_USBH_EN, "USBH_EN");
 305                 gpio_direction_output(GPIO_USBH_EN, !on);
 306                 mdelay(100);
 307                 break;
 308         default:
 309                 break;
 310         }
 311         return 0;
 312 }
 313 #endif /* CONFIG_USB_EHCI_MX6 */
 314
 315 #if defined(CONFIG_FSL_ESDHC) && defined(CONFIG_SPL_BUILD)
 316 /* use the following sequence: eMMC, MMC */
 317 struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
 318         {USDHC3_BASE_ADDR},
 319         {USDHC1_BASE_ADDR},
 320 };
 321
 322 int board_mmc_getcd(struct mmc *mmc)
 323 {
 324         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 325         int ret = true; /* default: assume inserted */
 326
 327         switch (cfg->esdhc_base) {
 328         case USDHC1_BASE_ADDR:
 329                 gpio_request(GPIO_MMC_CD, "MMC_CD");
 330                 gpio_direction_input(GPIO_MMC_CD);
 331                 ret = !gpio_get_value(GPIO_MMC_CD);
 332                 break;
 333         }
 334
 335         return ret;
 336 }
 337
 338 int board_mmc_init(bd_t *bis)
 339 {
 340         struct src *psrc = (struct src *)SRC_BASE_ADDR;
 341         unsigned reg = readl(&psrc->sbmr1) >> 11;
 342         /*
 343          * Upon reading BOOT_CFG register the following map is done:
 344          * Bit 11 and 12 of BOOT_CFG register can determine the current
 345          * mmc port
 346          * 0x1                  SD1
 347          * 0x2                  SD2
 348          * 0x3                  SD4
 349          */
 350
 351         switch (reg & 0x3) {
 352         case 0x0:
 353                 imx_iomux_v3_setup_multiple_pads(
 354                         usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
 355                 usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
 356                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 357                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 358                 break;
 359         case 0x2:
 360                 imx_iomux_v3_setup_multiple_pads(
 361                         usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 362                 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
 363                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 364                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 365                 break;
 366         default:
 367                 puts("MMC boot device not available");
 368         }
 369
 370         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 371 }
 372 #endif /* CONFIG_FSL_ESDHC & CONFIG_SPL_BUILD */
 373
 374 int board_phy_config(struct phy_device *phydev)
 375 {
 376         if (phydev->drv->config)
 377                 phydev->drv->config(phydev);
 378
 379         return 0;
 380 }
 381
 382 int board_eth_init(bd_t *bis)
 383 {
 384         struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 385         uint32_t base = IMX_FEC_BASE;
 386         struct mii_dev *bus = NULL;
 387         struct phy_device *phydev = NULL;
 388         int ret;
 389
 390         /* provide the PHY clock from the i.MX 6 */
 391         ret = enable_fec_anatop_clock(0, ENET_50MHZ);
 392         if (ret)
 393                 return ret;
 394
 395         /* set gpr1[ENET_CLK_SEL] */
 396         setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
 397
 398         setup_iomux_enet();
 399
 400 #ifdef CONFIG_FEC_MXC
 401         bus = fec_get_miibus(base, -1);
 402         if (!bus)
 403                 return 0;
 404
 405         /* scan PHY 1..7 */
 406         phydev = phy_find_by_mask(bus, 0xff, PHY_INTERFACE_MODE_RMII);
 407         if (!phydev) {
 408                 free(bus);
 409                 puts("no PHY found\n");
 410                 return 0;
 411         }
 412
 413         phy_reset(phydev);
 414         printf("using PHY at %d\n", phydev->addr);
 415         ret = fec_probe(bis, -1, base, bus, phydev);
 416         if (ret) {
 417                 printf("FEC MXC: %s:failed\n", __func__);
 418                 free(phydev);
 419                 free(bus);
 420         }
 421 #endif /* CONFIG_FEC_MXC */
 422
 423         return 0;
 424 }
 425
 426 static iomux_v3_cfg_t const pwr_intb_pads[] = {
 427         /*
 428          * the bootrom sets the iomux to vselect, potentially connecting
 429          * two outputs. Set this back to GPIO
 430          */
 431         MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)
 432 };
 433
 434 #if defined(CONFIG_VIDEO_IPUV3)
 435
 436 static iomux_v3_cfg_t const backlight_pads[] = {
 437         /* Backlight On */
 438         MX6_PAD_EIM_D26__GPIO3_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
 439 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 26)
 440         /* Backlight PWM, used as GPIO in U-Boot */
 441         MX6_PAD_EIM_A22__GPIO2_IO16  | MUX_PAD_CTRL(NO_PULLUP),
 442         MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL) |
 443                                        MUX_MODE_SION,
 444 #define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 9)
 445 };
 446
 447 static iomux_v3_cfg_t const rgb_pads[] = {
 448         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(OUTPUT_RGB),
 449         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(OUTPUT_RGB),
 450         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(OUTPUT_RGB),
 451         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(OUTPUT_RGB),
 452         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(OUTPUT_RGB),
 453         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(OUTPUT_RGB),
 454         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(OUTPUT_RGB),
 455         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(OUTPUT_RGB),
 456         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(OUTPUT_RGB),
 457         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(OUTPUT_RGB),
 458         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(OUTPUT_RGB),
 459         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(OUTPUT_RGB),
 460         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(OUTPUT_RGB),
 461         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(OUTPUT_RGB),
 462         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(OUTPUT_RGB),
 463         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(OUTPUT_RGB),
 464         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(OUTPUT_RGB),
 465         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(OUTPUT_RGB),
 466         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(OUTPUT_RGB),
 467         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(OUTPUT_RGB),
 468         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(OUTPUT_RGB),
 469         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(OUTPUT_RGB),
 470 };
 471
 472 static void do_enable_hdmi(struct display_info_t const *dev)
 473 {
 474         imx_enable_hdmi_phy();
 475 }
 476
 477 static void enable_rgb(struct display_info_t const *dev)
 478 {
 479         imx_iomux_v3_setup_multiple_pads(
 480                 rgb_pads,
 481                 ARRAY_SIZE(rgb_pads));
 482         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 483         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
 484 }
 485
 486 static int detect_default(struct display_info_t const *dev)
 487 {
 488         (void) dev;
 489         return 1;
 490 }
 491
 492 struct display_info_t const displays[] = {{
 493         .bus    = -1,
 494         .addr   = 0,
 495         .pixfmt = IPU_PIX_FMT_RGB24,
 496         .detect = detect_hdmi,
 497         .enable = do_enable_hdmi,
 498         .mode   = {
 499                 .name           = "HDMI",
 500                 .refresh        = 60,
 501                 .xres           = 1024,
 502                 .yres           = 768,
 503                 .pixclock       = 15385,
 504                 .left_margin    = 220,
 505                 .right_margin   = 40,
 506                 .upper_margin   = 21,
 507                 .lower_margin   = 7,
 508                 .hsync_len      = 60,
 509                 .vsync_len      = 10,
 510                 .sync           = FB_SYNC_EXT,
 511                 .vmode          = FB_VMODE_NONINTERLACED
 512 } }, {
 513         .bus    = -1,
 514         .addr   = 0,
 515         .pixfmt = IPU_PIX_FMT_RGB666,
 516         .detect = detect_default,
 517         .enable = enable_rgb,
 518         .mode   = {
 519                 .name           = "vga-rgb",
 520                 .refresh        = 60,
 521                 .xres           = 640,
 522                 .yres           = 480,
 523                 .pixclock       = 33000,
 524                 .left_margin    = 48,
 525                 .right_margin   = 16,
 526                 .upper_margin   = 31,
 527                 .lower_margin   = 11,
 528                 .hsync_len      = 96,
 529                 .vsync_len      = 2,
 530                 .sync           = 0,
 531                 .vmode          = FB_VMODE_NONINTERLACED
 532 } }, {
 533         .bus    = -1,
 534         .addr   = 0,
 535         .pixfmt = IPU_PIX_FMT_RGB666,
 536         .enable = enable_rgb,
 537         .mode   = {
 538                 .name           = "wvga-rgb",
 539                 .refresh        = 60,
 540                 .xres           = 800,
 541                 .yres           = 480,
 542                 .pixclock       = 25000,
 543                 .left_margin    = 40,
 544                 .right_margin   = 88,
 545                 .upper_margin   = 33,
 546                 .lower_margin   = 10,
 547                 .hsync_len      = 128,
 548                 .vsync_len      = 2,
 549                 .sync           = 0,
 550                 .vmode          = FB_VMODE_NONINTERLACED
 551 } } };
 552 size_t display_count = ARRAY_SIZE(displays);
 553
 554 static void setup_display(void)
 555 {
 556         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 557         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 558         int reg;
 559
 560         enable_ipu_clock();
 561         imx_setup_hdmi();
 562         /* Turn on LDB0,IPU,IPU DI0 clocks */
 563         reg = __raw_readl(&mxc_ccm->CCGR3);
 564         reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
 565         writel(reg, &mxc_ccm->CCGR3);
 566
 567         /* set LDB0, LDB1 clk select to 011/011 */
 568         reg = readl(&mxc_ccm->cs2cdr);
 569         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 570                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 571         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 572               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 573         writel(reg, &mxc_ccm->cs2cdr);
 574
 575         reg = readl(&mxc_ccm->cscmr2);
 576         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 577         writel(reg, &mxc_ccm->cscmr2);
 578
 579         reg = readl(&mxc_ccm->chsccdr);
 580         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 581                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 582         writel(reg, &mxc_ccm->chsccdr);
 583
 584         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 585              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 586              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 587              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 588              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 589              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 590              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 591              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 592              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 593         writel(reg, &iomux->gpr[2]);
 594
 595         reg = readl(&iomux->gpr[3]);
 596         reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
 597                         |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
 598             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 599                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 600         writel(reg, &iomux->gpr[3]);
 601
 602         /* backlight unconditionally on for now */
 603         imx_iomux_v3_setup_multiple_pads(backlight_pads,
 604                                          ARRAY_SIZE(backlight_pads));
 605         /* use 0 for EDT 7", use 1 for LG fullHD panel */
 606         gpio_request(RGB_BACKLIGHTPWM_GP, "PWM<A>");
 607         gpio_request(RGB_BACKLIGHT_GP, "BL_ON");
 608         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
 609         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 610 }
 611
 612 /*
 613  * Backlight off before OS handover
 614  */
 615 void board_preboot_os(void)
 616 {
 617         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 1);
 618         gpio_direction_output(RGB_BACKLIGHT_GP, 0);
 619 }
 620 #endif /* defined(CONFIG_VIDEO_IPUV3) */
 621
 622 int board_early_init_f(void)
 623 {
 624         imx_iomux_v3_setup_multiple_pads(pwr_intb_pads,
 625                                          ARRAY_SIZE(pwr_intb_pads));
 626         setup_iomux_uart();
 627
 628         return 0;
 629 }
 630
 631 /*
 632  * Do not overwrite the console
 633  * Use always serial for U-Boot console
 634  */
 635 int overwrite_console(void)
 636 {
 637         return 1;
 638 }
 639
 640 int board_init(void)
 641 {
 642         /* address of boot parameters */
 643         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 644
 645 #if defined(CONFIG_VIDEO_IPUV3)
 646         setup_display();
 647 #endif
 648
 649 #ifdef CONFIG_TDX_CMD_IMX_MFGR
 650         (void) pmic_init();
 651 #endif
 652
 653 #ifdef CONFIG_SATA
 654         setup_sata();
 655 #endif
 656
 657         setup_iomux_gpio();
 658
 659         return 0;
 660 }
 661
 662 #ifdef CONFIG_BOARD_LATE_INIT
 663 int board_late_init(void)
 664 {
 665 #if defined(CONFIG_REVISION_TAG) && \
 666     defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
 667         char env_str[256];
 668         u32 rev;
 669
 670         rev = get_board_rev();
 671         snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev);
 672         env_set("board_rev", env_str);
 673 #endif
 674
 675         return 0;
 676 }
 677 #endif /* CONFIG_BOARD_LATE_INIT */
 678
 679 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_SYSTEM_SETUP)
 680 int ft_system_setup(void *blob, bd_t *bd)
 681 {
 682         return 0;
 683 }
 684 #endif
 685
 686 int checkboard(void)
 687 {
 688         char it[] = " IT";
 689         int minc, maxc;
 690
 691         switch (get_cpu_temp_grade(&minc, &maxc)) {
 692         case TEMP_AUTOMOTIVE:
 693         case TEMP_INDUSTRIAL:
 694                 break;
 695         case TEMP_EXTCOMMERCIAL:
 696         default:
 697                 it[0] = 0;
 698         };
 699         printf("Model: Toradex Colibri iMX6 %s %sMB%s\n",
 700                is_cpu_type(MXC_CPU_MX6DL) ? "DualLite" : "Solo",
 701                (gd->ram_size == 0x20000000) ? "512" : "256", it);
 702         return 0;
 703 }
 704
 705 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 706 int ft_board_setup(void *blob, bd_t *bd)
 707 {
 708         return ft_common_board_setup(blob, bd);
 709 }
 710 #endif
 711
 712 #ifdef CONFIG_CMD_BMODE
 713 static const struct boot_mode board_boot_modes[] = {
 714         {"mmc", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
 715         {NULL,  0},
 716 };
 717 #endif
 718
 719 int misc_init_r(void)
 720 {
 721 #ifdef CONFIG_CMD_BMODE
 722         add_board_boot_modes(board_boot_modes);
 723 #endif
 724         return 0;
 725 }
 726
 727 #ifdef CONFIG_LDO_BYPASS_CHECK
 728 /* TODO, use external pmic, for now always ldo_enable */
 729 void ldo_mode_set(int ldo_bypass)
 730 {
 731         return;
 732 }
 733 #endif
 734
 735 #ifdef CONFIG_SPL_BUILD
 736 #include <spl.h>
 737 #include <linux/libfdt.h>
 738 #include "asm/arch/mx6dl-ddr.h"
 739 #include "asm/arch/iomux.h"
 740 #include "asm/arch/crm_regs.h"
 741
 742 static int mx6s_dcd_table[] = {
 743 /* ddr-setup.cfg */
 744
 745 MX6_IOM_DRAM_SDQS0, 0x00000030,
 746 MX6_IOM_DRAM_SDQS1, 0x00000030,
 747 MX6_IOM_DRAM_SDQS2, 0x00000030,
 748 MX6_IOM_DRAM_SDQS3, 0x00000030,
 749 MX6_IOM_DRAM_SDQS4, 0x00000030,
 750 MX6_IOM_DRAM_SDQS5, 0x00000030,
 751 MX6_IOM_DRAM_SDQS6, 0x00000030,
 752 MX6_IOM_DRAM_SDQS7, 0x00000030,
 753
 754 MX6_IOM_GRP_B0DS, 0x00000030,
 755 MX6_IOM_GRP_B1DS, 0x00000030,
 756 MX6_IOM_GRP_B2DS, 0x00000030,
 757 MX6_IOM_GRP_B3DS, 0x00000030,
 758 MX6_IOM_GRP_B4DS, 0x00000030,
 759 MX6_IOM_GRP_B5DS, 0x00000030,
 760 MX6_IOM_GRP_B6DS, 0x00000030,
 761 MX6_IOM_GRP_B7DS, 0x00000030,
 762 MX6_IOM_GRP_ADDDS, 0x00000030,
 763 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 764 MX6_IOM_GRP_CTLDS, 0x00000030,
 765
 766 MX6_IOM_DRAM_DQM0, 0x00020030,
 767 MX6_IOM_DRAM_DQM1, 0x00020030,
 768 MX6_IOM_DRAM_DQM2, 0x00020030,
 769 MX6_IOM_DRAM_DQM3, 0x00020030,
 770 MX6_IOM_DRAM_DQM4, 0x00020030,
 771 MX6_IOM_DRAM_DQM5, 0x00020030,
 772 MX6_IOM_DRAM_DQM6, 0x00020030,
 773 MX6_IOM_DRAM_DQM7, 0x00020030,
 774
 775 MX6_IOM_DRAM_CAS, 0x00020030,
 776 MX6_IOM_DRAM_RAS, 0x00020030,
 777 MX6_IOM_DRAM_SDCLK_0, 0x00020030,
 778 MX6_IOM_DRAM_SDCLK_1, 0x00020030,
 779
 780 MX6_IOM_DRAM_RESET, 0x00020030,
 781 MX6_IOM_DRAM_SDCKE0, 0x00003000,
 782 MX6_IOM_DRAM_SDCKE1, 0x00003000,
 783
 784 MX6_IOM_DRAM_SDODT0, 0x00003030,
 785 MX6_IOM_DRAM_SDODT1, 0x00003030,
 786
 787 /* (differential input) */
 788 MX6_IOM_DDRMODE_CTL, 0x00020000,
 789 /* (differential input) */
 790 MX6_IOM_GRP_DDRMODE, 0x00020000,
 791 /* disable ddr pullups */
 792 MX6_IOM_GRP_DDRPKE, 0x00000000,
 793 MX6_IOM_DRAM_SDBA2, 0x00000000,
 794 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 795 MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
 796
 797 /* Read data DQ Byte0-3 delay */
 798 MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
 799 MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
 800 MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
 801 MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
 802 MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
 803 MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
 804 MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
 805 MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
 806
 807 /*
 808  * MDMISC       mirroring       interleaved (row/bank/col)
 809  */
 810 /* TODO: check what the RALAT field does */
 811 MX6_MMDC_P0_MDMISC, 0x00081740,
 812
 813 /*
 814  * MDSCR        con_req
 815  */
 816 MX6_MMDC_P0_MDSCR, 0x00008000,
 817
 818
 819 /* 800mhz_2x64mx16.cfg */
 820
 821 MX6_MMDC_P0_MDPDC, 0x0002002D,
 822 MX6_MMDC_P0_MDCFG0, 0x2C305503,
 823 MX6_MMDC_P0_MDCFG1, 0xB66D8D63,
 824 MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
 825 MX6_MMDC_P0_MDRWD, 0x000026D2,
 826 MX6_MMDC_P0_MDOR, 0x00301023,
 827 MX6_MMDC_P0_MDOTC, 0x00333030,
 828 MX6_MMDC_P0_MDPDC, 0x0002556D,
 829 /* CS0 End: 7MSB of ((0x10000000, + 512M) -1) >> 25 */
 830 MX6_MMDC_P0_MDASP, 0x00000017,
 831 /* DDR3 DATA BUS SIZE: 64BIT */
 832 /* MX6_MMDC_P0_MDCTL, 0x821A0000, */
 833 /* DDR3 DATA BUS SIZE: 32BIT */
 834 MX6_MMDC_P0_MDCTL, 0x82190000,
 835
 836 /* Write commands to DDR */
 837 /* Load Mode Registers */
 838 /* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
 839 /* MX6_MMDC_P0_MDSCR, 0x04408032, */
 840 MX6_MMDC_P0_MDSCR, 0x04008032,
 841 MX6_MMDC_P0_MDSCR, 0x00008033,
 842 MX6_MMDC_P0_MDSCR, 0x00048031,
 843 MX6_MMDC_P0_MDSCR, 0x13208030,
 844 /* ZQ calibration */
 845 MX6_MMDC_P0_MDSCR, 0x04008040,
 846
 847 MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
 848 MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
 849 MX6_MMDC_P0_MDREF, 0x00005800,
 850
 851 MX6_MMDC_P0_MPODTCTRL, 0x00000000,
 852 MX6_MMDC_P1_MPODTCTRL, 0x00000000,
 853
 854 MX6_MMDC_P0_MPDGCTRL0, 0x42360232,
 855 MX6_MMDC_P0_MPDGCTRL1, 0x021F022A,
 856 MX6_MMDC_P1_MPDGCTRL0, 0x421E0224,
 857 MX6_MMDC_P1_MPDGCTRL1, 0x02110218,
 858
 859 MX6_MMDC_P0_MPRDDLCTL, 0x41434344,
 860 MX6_MMDC_P1_MPRDDLCTL, 0x4345423E,
 861 MX6_MMDC_P0_MPWRDLCTL, 0x39383339,
 862 MX6_MMDC_P1_MPWRDLCTL, 0x3E363930,
 863
 864 MX6_MMDC_P0_MPWLDECTRL0, 0x00340039,
 865 MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D,
 866 MX6_MMDC_P1_MPWLDECTRL0, 0x00120019,
 867 MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D,
 868
 869 MX6_MMDC_P0_MPMUR0, 0x00000800,
 870 MX6_MMDC_P1_MPMUR0, 0x00000800,
 871 MX6_MMDC_P0_MDSCR, 0x00000000,
 872 MX6_MMDC_P0_MAPSR, 0x00011006,
 873 };
 874
 875 static int mx6dl_dcd_table[] = {
 876 /* ddr-setup.cfg */
 877
 878 MX6_IOM_DRAM_SDQS0, 0x00000030,
 879 MX6_IOM_DRAM_SDQS1, 0x00000030,
 880 MX6_IOM_DRAM_SDQS2, 0x00000030,
 881 MX6_IOM_DRAM_SDQS3, 0x00000030,
 882 MX6_IOM_DRAM_SDQS4, 0x00000030,
 883 MX6_IOM_DRAM_SDQS5, 0x00000030,
 884 MX6_IOM_DRAM_SDQS6, 0x00000030,
 885 MX6_IOM_DRAM_SDQS7, 0x00000030,
 886
 887 MX6_IOM_GRP_B0DS, 0x00000030,
 888 MX6_IOM_GRP_B1DS, 0x00000030,
 889 MX6_IOM_GRP_B2DS, 0x00000030,
 890 MX6_IOM_GRP_B3DS, 0x00000030,
 891 MX6_IOM_GRP_B4DS, 0x00000030,
 892 MX6_IOM_GRP_B5DS, 0x00000030,
 893 MX6_IOM_GRP_B6DS, 0x00000030,
 894 MX6_IOM_GRP_B7DS, 0x00000030,
 895 MX6_IOM_GRP_ADDDS, 0x00000030,
 896 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 897 MX6_IOM_GRP_CTLDS, 0x00000030,
 898
 899 MX6_IOM_DRAM_DQM0, 0x00020030,
 900 MX6_IOM_DRAM_DQM1, 0x00020030,
 901 MX6_IOM_DRAM_DQM2, 0x00020030,
 902 MX6_IOM_DRAM_DQM3, 0x00020030,
 903 MX6_IOM_DRAM_DQM4, 0x00020030,
 904 MX6_IOM_DRAM_DQM5, 0x00020030,
 905 MX6_IOM_DRAM_DQM6, 0x00020030,
 906 MX6_IOM_DRAM_DQM7, 0x00020030,
 907
 908 MX6_IOM_DRAM_CAS, 0x00020030,
 909 MX6_IOM_DRAM_RAS, 0x00020030,
 910 MX6_IOM_DRAM_SDCLK_0, 0x00020030,
 911 MX6_IOM_DRAM_SDCLK_1, 0x00020030,
 912
 913 MX6_IOM_DRAM_RESET, 0x00020030,
 914 MX6_IOM_DRAM_SDCKE0, 0x00003000,
 915 MX6_IOM_DRAM_SDCKE1, 0x00003000,
 916
 917 MX6_IOM_DRAM_SDODT0, 0x00003030,
 918 MX6_IOM_DRAM_SDODT1, 0x00003030,
 919
 920 /* (differential input) */
 921 MX6_IOM_DDRMODE_CTL, 0x00020000,
 922 /* (differential input) */
 923 MX6_IOM_GRP_DDRMODE, 0x00020000,
 924 /* disable ddr pullups */
 925 MX6_IOM_GRP_DDRPKE, 0x00000000,
 926 MX6_IOM_DRAM_SDBA2, 0x00000000,
 927 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 928 MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
 929
 930 /* Read data DQ Byte0-3 delay */
 931 MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
 932 MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
 933 MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
 934 MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
 935 MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
 936 MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
 937 MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
 938 MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
 939
 940 /*
 941  * MDMISC       mirroring       interleaved (row/bank/col)
 942  */
 943 /* TODO: check what the RALAT field does */
 944 MX6_MMDC_P0_MDMISC, 0x00081740,
 945
 946 /*
 947  * MDSCR        con_req
 948  */
 949 MX6_MMDC_P0_MDSCR, 0x00008000,
 950
 951
 952 /* 800mhz_2x64mx16.cfg */
 953
 954 MX6_MMDC_P0_MDPDC, 0x0002002D,
 955 MX6_MMDC_P0_MDCFG0, 0x2C305503,
 956 MX6_MMDC_P0_MDCFG1, 0xB66D8D63,
 957 MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
 958 MX6_MMDC_P0_MDRWD, 0x000026D2,
 959 MX6_MMDC_P0_MDOR, 0x00301023,
 960 MX6_MMDC_P0_MDOTC, 0x00333030,
 961 MX6_MMDC_P0_MDPDC, 0x0002556D,
 962 /* CS0 End: 7MSB of ((0x10000000, + 512M) -1) >> 25 */
 963 MX6_MMDC_P0_MDASP, 0x00000017,
 964 /* DDR3 DATA BUS SIZE: 64BIT */
 965 MX6_MMDC_P0_MDCTL, 0x821A0000,
 966 /* DDR3 DATA BUS SIZE: 32BIT */
 967 /* MX6_MMDC_P0_MDCTL, 0x82190000, */
 968
 969 /* Write commands to DDR */
 970 /* Load Mode Registers */
 971 /* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
 972 /* MX6_MMDC_P0_MDSCR, 0x04408032, */
 973 MX6_MMDC_P0_MDSCR, 0x04008032,
 974 MX6_MMDC_P0_MDSCR, 0x00008033,
 975 MX6_MMDC_P0_MDSCR, 0x00048031,
 976 MX6_MMDC_P0_MDSCR, 0x13208030,
 977 /* ZQ calibration */
 978 MX6_MMDC_P0_MDSCR, 0x04008040,
 979
 980 MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
 981 MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
 982 MX6_MMDC_P0_MDREF, 0x00005800,
 983
 984 MX6_MMDC_P0_MPODTCTRL, 0x00000000,
 985 MX6_MMDC_P1_MPODTCTRL, 0x00000000,
 986
 987 MX6_MMDC_P0_MPDGCTRL0, 0x42360232,
 988 MX6_MMDC_P0_MPDGCTRL1, 0x021F022A,
 989 MX6_MMDC_P1_MPDGCTRL0, 0x421E0224,
 990 MX6_MMDC_P1_MPDGCTRL1, 0x02110218,
 991
 992 MX6_MMDC_P0_MPRDDLCTL, 0x41434344,
 993 MX6_MMDC_P1_MPRDDLCTL, 0x4345423E,
 994 MX6_MMDC_P0_MPWRDLCTL, 0x39383339,
 995 MX6_MMDC_P1_MPWRDLCTL, 0x3E363930,
 996
 997 MX6_MMDC_P0_MPWLDECTRL0, 0x00340039,
 998 MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D,
 999 MX6_MMDC_P1_MPWLDECTRL0, 0x00120019,
1000 MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D,
1001
1002 MX6_MMDC_P0_MPMUR0, 0x00000800,
1003 MX6_MMDC_P1_MPMUR0, 0x00000800,
1004 MX6_MMDC_P0_MDSCR, 0x00000000,
1005 MX6_MMDC_P0_MAPSR, 0x00011006,
1006 };
1007
1008 static void ccgr_init(void)
1009 {
1010         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1011
1012         writel(0x00C03F3F, &ccm->CCGR0);
1013         writel(0x0030FC03, &ccm->CCGR1);
1014         writel(0x0FFFFFF3, &ccm->CCGR2);
1015         writel(0x3FF0300F, &ccm->CCGR3);
1016         writel(0x00FFF300, &ccm->CCGR4);
1017         writel(0x0F0000F3, &ccm->CCGR5);
1018         writel(0x000003FF, &ccm->CCGR6);
1019
1020 /*
1021  * Setup CCM_CCOSR register as follows:
1022  *
1023  * cko1_en  = 1    --> CKO1 enabled
1024  * cko1_div = 111  --> divide by 8
1025  * cko1_sel = 1011 --> ahb_clk_root
1026  *
1027  * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
1028  */
1029         writel(0x000000FB, &ccm->ccosr);
1030 }
1031
1032 static void ddr_init(int *table, int size)
1033 {
1034         int i;
1035
1036         for (i = 0; i < size / 2 ; i++)
1037                 writel(table[2 * i + 1], table[2 * i]);
1038 }
1039
1040 static void spl_dram_init(void)
1041 {
1042         int minc, maxc;
1043
1044         switch (get_cpu_temp_grade(&minc, &maxc)) {
1045         case TEMP_COMMERCIAL:
1046         case TEMP_EXTCOMMERCIAL:
1047                 if (is_cpu_type(MXC_CPU_MX6DL)) {
1048                         puts("Commercial temperature grade DDR3 timings, 64bit bus width.\n");
1049                         ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
1050                 } else {
1051                         puts("Commercial temperature grade DDR3 timings, 32bit bus width.\n");
1052                         ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
1053                 }
1054                 break;
1055         case TEMP_INDUSTRIAL:
1056         case TEMP_AUTOMOTIVE:
1057         default:
1058                 if (is_cpu_type(MXC_CPU_MX6DL)) {
1059                         ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
1060                 } else {
1061                         puts("Industrial temperature grade DDR3 timings, 32bit bus width.\n");
1062                         ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
1063                 }
1064                 break;
1065         };
1066         udelay(100);
1067 }
1068
1069 void board_init_f(ulong dummy)
1070 {
1071         /* setup AIPS and disable watchdog */
1072         arch_cpu_init();
1073
1074         ccgr_init();
1075         gpr_init();
1076
1077         /* iomux */
1078         board_early_init_f();
1079
1080         /* setup GP timer */
1081         timer_init();
1082
1083         /* UART clocks enabled and gd valid - init serial console */
1084         preloader_console_init();
1085
1086         /* Make sure we use dte mode */
1087         setup_dtemode_uart();
1088
1089         /* DDR initialization */
1090         spl_dram_init();
1091
1092         /* Clear the BSS. */
1093         memset(__bss_start, 0, __bss_end - __bss_start);
1094
1095         /* load/boot image from boot device */
1096         board_init_r(NULL, 0);
1097 }
1098
1099 void reset_cpu(ulong addr)
1100 {
1101 }
1102
1103 #endif /* CONFIG_SPL_BUILD */
1104
1105 static struct mxc_serial_platdata mxc_serial_plat = {
1106         .reg = (struct mxc_uart *)UART1_BASE,
1107         .use_dte = true,
1108 };
1109
1110 U_BOOT_DEVICE(mxc_serial) = {
1111         .name = "serial_mxc",
1112         .platdata = &mxc_serial_plat,
1113 };