board/toradex/colibri_imx6/colibri_imx6.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
   4  * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
   5  * Copyright (C) 2014-2019, Toradex AG
   6  * copied from nitrogen6x
   7  */
   8
   9 #include <common.h>
  10 #include <dm.h>
  11
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/crm_regs.h>
  14 #include <asm/arch/imx-regs.h>
  15 #include <asm/arch/mx6-ddr.h>
  16 #include <asm/arch/mx6-pins.h>
  17 #include <asm/arch/mxc_hdmi.h>
  18 #include <asm/arch/sys_proto.h>
  19 #include <asm/bootm.h>
  20 #include <asm/gpio.h>
  21 #include <asm/mach-imx/boot_mode.h>
  22 #include <asm/mach-imx/iomux-v3.h>
  23 #include <asm/mach-imx/sata.h>
  24 #include <asm/mach-imx/video.h>
  25 #include <dm/platform_data/serial_mxc.h>
  26 #include <environment.h>
  27 #include <fsl_esdhc.h>
  28 #include <imx_thermal.h>
  29 #include <micrel.h>
  30 #include <miiphy.h>
  31 #include <netdev.h>
  32
  33 #include "../common/tdx-cfg-block.h"
  34 #ifdef CONFIG_TDX_CMD_IMX_MFGR
  35 #include "pf0100.h"
  36 #endif
  37
  38 DECLARE_GLOBAL_DATA_PTR;
  39
  40 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  41         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  42         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  43
  44 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  45         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  46         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  47
  48 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  49         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  50
  51 #define WEAK_PULLUP     (PAD_CTL_PUS_100K_UP |                  \
  52         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  53         PAD_CTL_SRE_SLOW)
  54
  55 #define NO_PULLUP       (                                       \
  56         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  57         PAD_CTL_SRE_SLOW)
  58
  59 #define WEAK_PULLDOWN   (PAD_CTL_PUS_100K_DOWN |                \
  60         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  61         PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
  62
  63 #define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST)
  64
  65 int dram_init(void)
  66 {
  67         /* use the DDR controllers configured size */
  68         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  69                                     (ulong)imx_ddr_size());
  70
  71         return 0;
  72 }
  73
  74 /* Colibri UARTA */
  75 iomux_v3_cfg_t const uart1_pads[] = {
  76         MX6_PAD_CSI0_DAT10__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  77         MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  78 };
  79
  80 /* Colibri MMC */
  81 iomux_v3_cfg_t const usdhc1_pads[] = {
  82         MX6_PAD_SD1_CLK__SD1_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  83         MX6_PAD_SD1_CMD__SD1_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  84         MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  85         MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  86         MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  87         MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  88         MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
  89 #       define GPIO_MMC_CD IMX_GPIO_NR(2, 5)
  90 };
  91
  92 /* eMMC */
  93 iomux_v3_cfg_t const usdhc3_pads[] = {
  94         MX6_PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  95         MX6_PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  96         MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  97         MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  98         MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  99         MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 100         MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 101         MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 102         MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 103         MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 104         MX6_PAD_SD3_RST__SD3_RESET  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 105 };
 106
 107 iomux_v3_cfg_t const enet_pads[] = {
 108         MX6_PAD_ENET_MDC__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
 109         MX6_PAD_ENET_MDIO__ENET_MDIO            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 110         MX6_PAD_ENET_RXD0__ENET_RX_DATA0        | MUX_PAD_CTRL(ENET_PAD_CTRL),
 111         MX6_PAD_ENET_RXD1__ENET_RX_DATA1        | MUX_PAD_CTRL(ENET_PAD_CTRL),
 112         MX6_PAD_ENET_RX_ER__ENET_RX_ER          | MUX_PAD_CTRL(ENET_PAD_CTRL),
 113         MX6_PAD_ENET_TX_EN__ENET_TX_EN          | MUX_PAD_CTRL(ENET_PAD_CTRL),
 114         MX6_PAD_ENET_TXD0__ENET_TX_DATA0        | MUX_PAD_CTRL(ENET_PAD_CTRL),
 115         MX6_PAD_ENET_TXD1__ENET_TX_DATA1        | MUX_PAD_CTRL(ENET_PAD_CTRL),
 116         MX6_PAD_ENET_CRS_DV__ENET_RX_EN         | MUX_PAD_CTRL(ENET_PAD_CTRL),
 117         MX6_PAD_GPIO_16__ENET_REF_CLK           | MUX_PAD_CTRL(ENET_PAD_CTRL),
 118 };
 119
 120 static void setup_iomux_enet(void)
 121 {
 122         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
 123 }
 124
 125 /* mux auxiliary pins to GPIO, so they can be used from the U-Boot cmdline */
 126 iomux_v3_cfg_t const gpio_pads[] = {
 127         /* ADDRESS[17:18] [25] used as GPIO */
 128         MX6_PAD_KEY_ROW2__GPIO4_IO11    | MUX_PAD_CTRL(WEAK_PULLUP) |
 129                                           MUX_MODE_SION,
 130         MX6_PAD_KEY_COL2__GPIO4_IO10    | MUX_PAD_CTRL(WEAK_PULLUP) |
 131                                           MUX_MODE_SION,
 132         MX6_PAD_NANDF_D1__GPIO2_IO01    | MUX_PAD_CTRL(WEAK_PULLUP) |
 133                                           MUX_MODE_SION,
 134         /* ADDRESS[19:24] used as GPIO */
 135         MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(WEAK_PULLUP) |
 136                                           MUX_MODE_SION,
 137         MX6_PAD_DISP0_DAT22__GPIO5_IO16 | MUX_PAD_CTRL(WEAK_PULLUP) |
 138                                           MUX_MODE_SION,
 139         MX6_PAD_DISP0_DAT21__GPIO5_IO15 | MUX_PAD_CTRL(WEAK_PULLUP) |
 140                                           MUX_MODE_SION,
 141         MX6_PAD_DISP0_DAT20__GPIO5_IO14 | MUX_PAD_CTRL(WEAK_PULLUP) |
 142                                           MUX_MODE_SION,
 143         MX6_PAD_DISP0_DAT19__GPIO5_IO13 | MUX_PAD_CTRL(WEAK_PULLUP) |
 144                                           MUX_MODE_SION,
 145         MX6_PAD_DISP0_DAT18__GPIO5_IO12 | MUX_PAD_CTRL(WEAK_PULLUP) |
 146                                           MUX_MODE_SION,
 147         /* DATA[16:29] [31]      used as GPIO */
 148         MX6_PAD_EIM_LBA__GPIO2_IO27     | MUX_PAD_CTRL(WEAK_PULLUP) |
 149                                           MUX_MODE_SION,
 150         MX6_PAD_EIM_BCLK__GPIO6_IO31    | MUX_PAD_CTRL(WEAK_PULLUP) |
 151                                           MUX_MODE_SION,
 152         MX6_PAD_NANDF_CS3__GPIO6_IO16   | MUX_PAD_CTRL(WEAK_PULLUP) |
 153                                           MUX_MODE_SION,
 154         MX6_PAD_NANDF_CS1__GPIO6_IO14   | MUX_PAD_CTRL(WEAK_PULLUP) |
 155                                           MUX_MODE_SION,
 156         MX6_PAD_NANDF_RB0__GPIO6_IO10   | MUX_PAD_CTRL(WEAK_PULLUP) |
 157                                           MUX_MODE_SION,
 158         MX6_PAD_NANDF_ALE__GPIO6_IO08   | MUX_PAD_CTRL(WEAK_PULLUP) |
 159                                           MUX_MODE_SION,
 160         MX6_PAD_NANDF_WP_B__GPIO6_IO09  | MUX_PAD_CTRL(WEAK_PULLUP) |
 161                                           MUX_MODE_SION,
 162         MX6_PAD_NANDF_CS0__GPIO6_IO11   | MUX_PAD_CTRL(WEAK_PULLUP) |
 163                                           MUX_MODE_SION,
 164         MX6_PAD_NANDF_CLE__GPIO6_IO07   | MUX_PAD_CTRL(WEAK_PULLUP) |
 165                                           MUX_MODE_SION,
 166         MX6_PAD_GPIO_19__GPIO4_IO05     | MUX_PAD_CTRL(WEAK_PULLUP) |
 167                                           MUX_MODE_SION,
 168         MX6_PAD_CSI0_MCLK__GPIO5_IO19   | MUX_PAD_CTRL(WEAK_PULLUP) |
 169                                           MUX_MODE_SION,
 170         MX6_PAD_CSI0_PIXCLK__GPIO5_IO18 | MUX_PAD_CTRL(WEAK_PULLUP) |
 171                                           MUX_MODE_SION,
 172         MX6_PAD_GPIO_4__GPIO1_IO04      | MUX_PAD_CTRL(WEAK_PULLUP) |
 173                                           MUX_MODE_SION,
 174         MX6_PAD_GPIO_5__GPIO1_IO05      | MUX_PAD_CTRL(WEAK_PULLUP) |
 175                                           MUX_MODE_SION,
 176         MX6_PAD_GPIO_2__GPIO1_IO02      | MUX_PAD_CTRL(WEAK_PULLUP) |
 177                                           MUX_MODE_SION,
 178         /* DQM[0:3]      used as GPIO */
 179         MX6_PAD_EIM_EB0__GPIO2_IO28     | MUX_PAD_CTRL(WEAK_PULLUP) |
 180                                           MUX_MODE_SION,
 181         MX6_PAD_EIM_EB1__GPIO2_IO29     | MUX_PAD_CTRL(WEAK_PULLUP) |
 182                                           MUX_MODE_SION,
 183         MX6_PAD_SD2_DAT2__GPIO1_IO13    | MUX_PAD_CTRL(WEAK_PULLUP) |
 184                                           MUX_MODE_SION,
 185         MX6_PAD_NANDF_D0__GPIO2_IO00    | MUX_PAD_CTRL(WEAK_PULLUP) |
 186                                           MUX_MODE_SION,
 187         /* RDY  used as GPIO */
 188         MX6_PAD_EIM_WAIT__GPIO5_IO00    | MUX_PAD_CTRL(WEAK_PULLUP) |
 189                                           MUX_MODE_SION,
 190         /* ADDRESS[16] DATA[30]  used as GPIO */
 191         MX6_PAD_KEY_ROW4__GPIO4_IO15    | MUX_PAD_CTRL(WEAK_PULLDOWN) |
 192                                           MUX_MODE_SION,
 193         MX6_PAD_KEY_COL4__GPIO4_IO14    | MUX_PAD_CTRL(WEAK_PULLUP) |
 194                                           MUX_MODE_SION,
 195         /* CSI pins used as GPIO */
 196         MX6_PAD_EIM_A24__GPIO5_IO04     | MUX_PAD_CTRL(WEAK_PULLUP) |
 197                                           MUX_MODE_SION,
 198         MX6_PAD_SD2_CMD__GPIO1_IO11     | MUX_PAD_CTRL(WEAK_PULLUP) |
 199                                           MUX_MODE_SION,
 200         MX6_PAD_NANDF_CS2__GPIO6_IO15   | MUX_PAD_CTRL(WEAK_PULLUP) |
 201                                           MUX_MODE_SION,
 202         MX6_PAD_EIM_D18__GPIO3_IO18     | MUX_PAD_CTRL(WEAK_PULLUP) |
 203                                           MUX_MODE_SION,
 204         MX6_PAD_EIM_A19__GPIO2_IO19     | MUX_PAD_CTRL(WEAK_PULLUP) |
 205                                           MUX_MODE_SION,
 206         MX6_PAD_EIM_D29__GPIO3_IO29     | MUX_PAD_CTRL(WEAK_PULLDOWN) |
 207                                           MUX_MODE_SION,
 208         MX6_PAD_EIM_A23__GPIO6_IO06     | MUX_PAD_CTRL(WEAK_PULLUP) |
 209                                           MUX_MODE_SION,
 210         MX6_PAD_EIM_A20__GPIO2_IO18     | MUX_PAD_CTRL(WEAK_PULLUP) |
 211                                           MUX_MODE_SION,
 212         MX6_PAD_EIM_A17__GPIO2_IO21     | MUX_PAD_CTRL(WEAK_PULLUP) |
 213                                           MUX_MODE_SION,
 214         MX6_PAD_EIM_A18__GPIO2_IO20     | MUX_PAD_CTRL(WEAK_PULLUP) |
 215                                           MUX_MODE_SION,
 216         MX6_PAD_EIM_EB3__GPIO2_IO31     | MUX_PAD_CTRL(WEAK_PULLUP) |
 217                                           MUX_MODE_SION,
 218         MX6_PAD_EIM_D17__GPIO3_IO17     | MUX_PAD_CTRL(WEAK_PULLUP) |
 219                                           MUX_MODE_SION,
 220         MX6_PAD_SD2_DAT0__GPIO1_IO15    | MUX_PAD_CTRL(WEAK_PULLUP) |
 221                                           MUX_MODE_SION,
 222         /* GPIO */
 223         MX6_PAD_EIM_D26__GPIO3_IO26     | MUX_PAD_CTRL(WEAK_PULLUP) |
 224                                           MUX_MODE_SION,
 225         MX6_PAD_EIM_D27__GPIO3_IO27     | MUX_PAD_CTRL(WEAK_PULLUP) |
 226                                           MUX_MODE_SION,
 227         MX6_PAD_NANDF_D6__GPIO2_IO06    | MUX_PAD_CTRL(WEAK_PULLUP) |
 228                                           MUX_MODE_SION,
 229         MX6_PAD_NANDF_D3__GPIO2_IO03    | MUX_PAD_CTRL(WEAK_PULLUP) |
 230                                           MUX_MODE_SION,
 231         MX6_PAD_ENET_REF_CLK__GPIO1_IO23 | MUX_PAD_CTRL(WEAK_PULLUP) |
 232                                           MUX_MODE_SION,
 233         MX6_PAD_DI0_PIN4__GPIO4_IO20    | MUX_PAD_CTRL(WEAK_PULLUP) |
 234                                           MUX_MODE_SION,
 235         MX6_PAD_SD4_DAT3__GPIO2_IO11    | MUX_PAD_CTRL(WEAK_PULLUP) |
 236                                           MUX_MODE_SION,
 237         MX6_PAD_NANDF_D4__GPIO2_IO04    | MUX_PAD_CTRL(WEAK_PULLUP) |
 238                                           MUX_MODE_SION,
 239         MX6_PAD_SD4_DAT0__GPIO2_IO08    | MUX_PAD_CTRL(WEAK_PULLUP) |
 240                                           MUX_MODE_SION,
 241         MX6_PAD_GPIO_7__GPIO1_IO07      | MUX_PAD_CTRL(WEAK_PULLUP) |
 242                                           MUX_MODE_SION,
 243         MX6_PAD_GPIO_8__GPIO1_IO08      | MUX_PAD_CTRL(WEAK_PULLUP) |
 244                                           MUX_MODE_SION,
 245         /* USBH_OC */
 246         MX6_PAD_EIM_D30__GPIO3_IO30     | MUX_PAD_CTRL(WEAK_PULLUP),
 247         /* USBC_ID */
 248         MX6_PAD_NANDF_D2__GPIO2_IO02    | MUX_PAD_CTRL(WEAK_PULLUP),
 249         /* USBC_DET */
 250         MX6_PAD_GPIO_17__GPIO7_IO12     | MUX_PAD_CTRL(WEAK_PULLUP),
 251 };
 252
 253 static void setup_iomux_gpio(void)
 254 {
 255         imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
 256 }
 257
 258 iomux_v3_cfg_t const usb_pads[] = {
 259         /* USBH_PEN */
 260         MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
 261 #       define GPIO_USBH_EN IMX_GPIO_NR(3, 31)
 262 };
 263
 264 /*
 265  * UARTs are used in DTE mode, switch the mode on all UARTs before
 266  * any pinmuxing connects a (DCE) output to a transceiver output.
 267  */
 268 #define UFCR            0x90    /* FIFO Control Register */
 269 #define UFCR_DCEDTE     (1<<6)  /* DCE=0 */
 270
 271 static void setup_dtemode_uart(void)
 272 {
 273         setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
 274         setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
 275         setbits_le32((u32 *)(UART3_BASE + UFCR), UFCR_DCEDTE);
 276 }
 277
 278 static void setup_iomux_uart(void)
 279 {
 280         setup_dtemode_uart();
 281         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 282 }
 283
 284 #ifdef CONFIG_USB_EHCI_MX6
 285 int board_ehci_hcd_init(int port)
 286 {
 287         imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
 288         return 0;
 289 }
 290
 291 int board_ehci_power(int port, int on)
 292 {
 293         switch (port) {
 294         case 0:
 295                 /* control OTG power */
 296                 /* No special PE for USBC, always on when ID pin signals
 297                    host mode */
 298                 break;
 299         case 1:
 300                 /* Control MXM USBH */
 301                 /* Set MXM USBH power enable, '0' means on */
 302                 gpio_request(GPIO_USBH_EN, "USBH_EN");
 303                 gpio_direction_output(GPIO_USBH_EN, !on);
 304                 mdelay(100);
 305                 break;
 306         default:
 307                 break;
 308         }
 309         return 0;
 310 }
 311 #endif /* CONFIG_USB_EHCI_MX6 */
 312
 313 #ifdef CONFIG_FSL_ESDHC
 314 /* use the following sequence: eMMC, MMC */
 315 struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
 316         {USDHC3_BASE_ADDR},
 317         {USDHC1_BASE_ADDR},
 318 };
 319
 320 int board_mmc_getcd(struct mmc *mmc)
 321 {
 322         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 323         int ret = true; /* default: assume inserted */
 324
 325         switch (cfg->esdhc_base) {
 326         case USDHC1_BASE_ADDR:
 327                 gpio_request(GPIO_MMC_CD, "MMC_CD");
 328                 gpio_direction_input(GPIO_MMC_CD);
 329                 ret = !gpio_get_value(GPIO_MMC_CD);
 330                 break;
 331         }
 332
 333         return ret;
 334 }
 335
 336 int board_mmc_init(bd_t *bis)
 337 {
 338 #ifndef CONFIG_SPL_BUILD
 339         s32 status = 0;
 340         u32 index = 0;
 341
 342         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 343         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 344
 345         usdhc_cfg[0].max_bus_width = 8;
 346         usdhc_cfg[1].max_bus_width = 4;
 347
 348         for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
 349                 switch (index) {
 350                 case 0:
 351                         imx_iomux_v3_setup_multiple_pads(
 352                                 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 353                         break;
 354                 case 1:
 355                         imx_iomux_v3_setup_multiple_pads(
 356                                 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
 357                         break;
 358                 default:
 359                         printf("Warning: you configured more USDHC controllers (%d) then supported by the board (%d)\n",
 360                                index + 1, CONFIG_SYS_FSL_USDHC_NUM);
 361                         return status;
 362                 }
 363
 364                 status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
 365         }
 366
 367         return status;
 368 #else /* !CONFIG_SPL_BUILD */
 369         struct src *psrc = (struct src *)SRC_BASE_ADDR;
 370         unsigned reg = readl(&psrc->sbmr1) >> 11;
 371         /*
 372          * Upon reading BOOT_CFG register the following map is done:
 373          * Bit 11 and 12 of BOOT_CFG register can determine the current
 374          * mmc port
 375          * 0x1                  SD1
 376          * 0x2                  SD2
 377          * 0x3                  SD4
 378          */
 379
 380         switch (reg & 0x3) {
 381         case 0x0:
 382                 imx_iomux_v3_setup_multiple_pads(
 383                         usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
 384                 usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
 385                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 386                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 387                 break;
 388         case 0x2:
 389                 imx_iomux_v3_setup_multiple_pads(
 390                         usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 391                 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
 392                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 393                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 394                 break;
 395         default:
 396                 puts("MMC boot device not available");
 397         }
 398
 399         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 400 #endif /* !CONFIG_SPL_BUILD */
 401 }
 402 #endif /* CONFIG_FSL_ESDHC */
 403
 404 int board_phy_config(struct phy_device *phydev)
 405 {
 406         if (phydev->drv->config)
 407                 phydev->drv->config(phydev);
 408
 409         return 0;
 410 }
 411
 412 int board_eth_init(bd_t *bis)
 413 {
 414         struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 415         uint32_t base = IMX_FEC_BASE;
 416         struct mii_dev *bus = NULL;
 417         struct phy_device *phydev = NULL;
 418         int ret;
 419
 420         /* provide the PHY clock from the i.MX 6 */
 421         ret = enable_fec_anatop_clock(0, ENET_50MHZ);
 422         if (ret)
 423                 return ret;
 424
 425         /* set gpr1[ENET_CLK_SEL] */
 426         setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
 427
 428         setup_iomux_enet();
 429
 430 #ifdef CONFIG_FEC_MXC
 431         bus = fec_get_miibus(base, -1);
 432         if (!bus)
 433                 return 0;
 434
 435         /* scan PHY 1..7 */
 436         phydev = phy_find_by_mask(bus, 0xff, PHY_INTERFACE_MODE_RMII);
 437         if (!phydev) {
 438                 free(bus);
 439                 puts("no PHY found\n");
 440                 return 0;
 441         }
 442
 443         phy_reset(phydev);
 444         printf("using PHY at %d\n", phydev->addr);
 445         ret = fec_probe(bis, -1, base, bus, phydev);
 446         if (ret) {
 447                 printf("FEC MXC: %s:failed\n", __func__);
 448                 free(phydev);
 449                 free(bus);
 450         }
 451 #endif /* CONFIG_FEC_MXC */
 452
 453         return 0;
 454 }
 455
 456 static iomux_v3_cfg_t const pwr_intb_pads[] = {
 457         /*
 458          * the bootrom sets the iomux to vselect, potentially connecting
 459          * two outputs. Set this back to GPIO
 460          */
 461         MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)
 462 };
 463
 464 #if defined(CONFIG_VIDEO_IPUV3)
 465
 466 static iomux_v3_cfg_t const backlight_pads[] = {
 467         /* Backlight On */
 468         MX6_PAD_EIM_D26__GPIO3_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
 469 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 26)
 470         /* Backlight PWM, used as GPIO in U-Boot */
 471         MX6_PAD_EIM_A22__GPIO2_IO16  | MUX_PAD_CTRL(NO_PULLUP),
 472         MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL) |
 473                                        MUX_MODE_SION,
 474 #define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 9)
 475 };
 476
 477 static iomux_v3_cfg_t const rgb_pads[] = {
 478         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(OUTPUT_RGB),
 479         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(OUTPUT_RGB),
 480         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(OUTPUT_RGB),
 481         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(OUTPUT_RGB),
 482         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(OUTPUT_RGB),
 483         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(OUTPUT_RGB),
 484         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(OUTPUT_RGB),
 485         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(OUTPUT_RGB),
 486         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(OUTPUT_RGB),
 487         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(OUTPUT_RGB),
 488         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(OUTPUT_RGB),
 489         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(OUTPUT_RGB),
 490         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(OUTPUT_RGB),
 491         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(OUTPUT_RGB),
 492         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(OUTPUT_RGB),
 493         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(OUTPUT_RGB),
 494         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(OUTPUT_RGB),
 495         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(OUTPUT_RGB),
 496         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(OUTPUT_RGB),
 497         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(OUTPUT_RGB),
 498         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(OUTPUT_RGB),
 499         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(OUTPUT_RGB),
 500 };
 501
 502 static void do_enable_hdmi(struct display_info_t const *dev)
 503 {
 504         imx_enable_hdmi_phy();
 505 }
 506
 507 static void enable_rgb(struct display_info_t const *dev)
 508 {
 509         imx_iomux_v3_setup_multiple_pads(
 510                 rgb_pads,
 511                 ARRAY_SIZE(rgb_pads));
 512         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 513         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
 514 }
 515
 516 static int detect_default(struct display_info_t const *dev)
 517 {
 518         (void) dev;
 519         return 1;
 520 }
 521
 522 struct display_info_t const displays[] = {{
 523         .bus    = -1,
 524         .addr   = 0,
 525         .pixfmt = IPU_PIX_FMT_RGB24,
 526         .detect = detect_hdmi,
 527         .enable = do_enable_hdmi,
 528         .mode   = {
 529                 .name           = "HDMI",
 530                 .refresh        = 60,
 531                 .xres           = 1024,
 532                 .yres           = 768,
 533                 .pixclock       = 15385,
 534                 .left_margin    = 220,
 535                 .right_margin   = 40,
 536                 .upper_margin   = 21,
 537                 .lower_margin   = 7,
 538                 .hsync_len      = 60,
 539                 .vsync_len      = 10,
 540                 .sync           = FB_SYNC_EXT,
 541                 .vmode          = FB_VMODE_NONINTERLACED
 542 } }, {
 543         .bus    = -1,
 544         .addr   = 0,
 545         .pixfmt = IPU_PIX_FMT_RGB666,
 546         .detect = detect_default,
 547         .enable = enable_rgb,
 548         .mode   = {
 549                 .name           = "vga-rgb",
 550                 .refresh        = 60,
 551                 .xres           = 640,
 552                 .yres           = 480,
 553                 .pixclock       = 33000,
 554                 .left_margin    = 48,
 555                 .right_margin   = 16,
 556                 .upper_margin   = 31,
 557                 .lower_margin   = 11,
 558                 .hsync_len      = 96,
 559                 .vsync_len      = 2,
 560                 .sync           = 0,
 561                 .vmode          = FB_VMODE_NONINTERLACED
 562 } }, {
 563         .bus    = -1,
 564         .addr   = 0,
 565         .pixfmt = IPU_PIX_FMT_RGB666,
 566         .enable = enable_rgb,
 567         .mode   = {
 568                 .name           = "wvga-rgb",
 569                 .refresh        = 60,
 570                 .xres           = 800,
 571                 .yres           = 480,
 572                 .pixclock       = 25000,
 573                 .left_margin    = 40,
 574                 .right_margin   = 88,
 575                 .upper_margin   = 33,
 576                 .lower_margin   = 10,
 577                 .hsync_len      = 128,
 578                 .vsync_len      = 2,
 579                 .sync           = 0,
 580                 .vmode          = FB_VMODE_NONINTERLACED
 581 } } };
 582 size_t display_count = ARRAY_SIZE(displays);
 583
 584 static void setup_display(void)
 585 {
 586         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 587         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 588         int reg;
 589
 590         enable_ipu_clock();
 591         imx_setup_hdmi();
 592         /* Turn on LDB0,IPU,IPU DI0 clocks */
 593         reg = __raw_readl(&mxc_ccm->CCGR3);
 594         reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
 595         writel(reg, &mxc_ccm->CCGR3);
 596
 597         /* set LDB0, LDB1 clk select to 011/011 */
 598         reg = readl(&mxc_ccm->cs2cdr);
 599         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 600                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 601         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 602               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 603         writel(reg, &mxc_ccm->cs2cdr);
 604
 605         reg = readl(&mxc_ccm->cscmr2);
 606         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 607         writel(reg, &mxc_ccm->cscmr2);
 608
 609         reg = readl(&mxc_ccm->chsccdr);
 610         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 611                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 612         writel(reg, &mxc_ccm->chsccdr);
 613
 614         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 615              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 616              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 617              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 618              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 619              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 620              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 621              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 622              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 623         writel(reg, &iomux->gpr[2]);
 624
 625         reg = readl(&iomux->gpr[3]);
 626         reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
 627                         |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
 628             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 629                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 630         writel(reg, &iomux->gpr[3]);
 631
 632         /* backlight unconditionally on for now */
 633         imx_iomux_v3_setup_multiple_pads(backlight_pads,
 634                                          ARRAY_SIZE(backlight_pads));
 635         /* use 0 for EDT 7", use 1 for LG fullHD panel */
 636         gpio_request(RGB_BACKLIGHTPWM_GP, "PWM<A>");
 637         gpio_request(RGB_BACKLIGHT_GP, "BL_ON");
 638         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
 639         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 640 }
 641
 642 /*
 643  * Backlight off before OS handover
 644  */
 645 void board_preboot_os(void)
 646 {
 647         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 1);
 648         gpio_direction_output(RGB_BACKLIGHT_GP, 0);
 649 }
 650 #endif /* defined(CONFIG_VIDEO_IPUV3) */
 651
 652 int board_early_init_f(void)
 653 {
 654         imx_iomux_v3_setup_multiple_pads(pwr_intb_pads,
 655                                          ARRAY_SIZE(pwr_intb_pads));
 656         setup_iomux_uart();
 657
 658         return 0;
 659 }
 660
 661 /*
 662  * Do not overwrite the console
 663  * Use always serial for U-Boot console
 664  */
 665 int overwrite_console(void)
 666 {
 667         return 1;
 668 }
 669
 670 int board_init(void)
 671 {
 672         /* address of boot parameters */
 673         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 674
 675 #if defined(CONFIG_VIDEO_IPUV3)
 676         setup_display();
 677 #endif
 678
 679 #ifdef CONFIG_TDX_CMD_IMX_MFGR
 680         (void) pmic_init();
 681 #endif
 682
 683 #ifdef CONFIG_SATA
 684         setup_sata();
 685 #endif
 686
 687         setup_iomux_gpio();
 688
 689         return 0;
 690 }
 691
 692 #ifdef CONFIG_BOARD_LATE_INIT
 693 int board_late_init(void)
 694 {
 695 #if defined(CONFIG_REVISION_TAG) && \
 696     defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
 697         char env_str[256];
 698         u32 rev;
 699
 700         rev = get_board_rev();
 701         snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev);
 702         env_set("board_rev", env_str);
 703 #endif
 704
 705         return 0;
 706 }
 707 #endif /* CONFIG_BOARD_LATE_INIT */
 708
 709 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_SYSTEM_SETUP)
 710 int ft_system_setup(void *blob, bd_t *bd)
 711 {
 712         return 0;
 713 }
 714 #endif
 715
 716 int checkboard(void)
 717 {
 718         char it[] = " IT";
 719         int minc, maxc;
 720
 721         switch (get_cpu_temp_grade(&minc, &maxc)) {
 722         case TEMP_AUTOMOTIVE:
 723         case TEMP_INDUSTRIAL:
 724                 break;
 725         case TEMP_EXTCOMMERCIAL:
 726         default:
 727                 it[0] = 0;
 728         };
 729         printf("Model: Toradex Colibri iMX6 %s %sMB%s\n",
 730                is_cpu_type(MXC_CPU_MX6DL) ? "DualLite" : "Solo",
 731                (gd->ram_size == 0x20000000) ? "512" : "256", it);
 732         return 0;
 733 }
 734
 735 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 736 int ft_board_setup(void *blob, bd_t *bd)
 737 {
 738         return ft_common_board_setup(blob, bd);
 739 }
 740 #endif
 741
 742 #ifdef CONFIG_CMD_BMODE
 743 static const struct boot_mode board_boot_modes[] = {
 744         {"mmc", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
 745         {NULL,  0},
 746 };
 747 #endif
 748
 749 int misc_init_r(void)
 750 {
 751 #ifdef CONFIG_CMD_BMODE
 752         add_board_boot_modes(board_boot_modes);
 753 #endif
 754         return 0;
 755 }
 756
 757 #ifdef CONFIG_LDO_BYPASS_CHECK
 758 /* TODO, use external pmic, for now always ldo_enable */
 759 void ldo_mode_set(int ldo_bypass)
 760 {
 761         return;
 762 }
 763 #endif
 764
 765 #ifdef CONFIG_SPL_BUILD
 766 #include <spl.h>
 767 #include <linux/libfdt.h>
 768 #include "asm/arch/mx6dl-ddr.h"
 769 #include "asm/arch/iomux.h"
 770 #include "asm/arch/crm_regs.h"
 771
 772 static int mx6s_dcd_table[] = {
 773 /* ddr-setup.cfg */
 774
 775 MX6_IOM_DRAM_SDQS0, 0x00000030,
 776 MX6_IOM_DRAM_SDQS1, 0x00000030,
 777 MX6_IOM_DRAM_SDQS2, 0x00000030,
 778 MX6_IOM_DRAM_SDQS3, 0x00000030,
 779 MX6_IOM_DRAM_SDQS4, 0x00000030,
 780 MX6_IOM_DRAM_SDQS5, 0x00000030,
 781 MX6_IOM_DRAM_SDQS6, 0x00000030,
 782 MX6_IOM_DRAM_SDQS7, 0x00000030,
 783
 784 MX6_IOM_GRP_B0DS, 0x00000030,
 785 MX6_IOM_GRP_B1DS, 0x00000030,
 786 MX6_IOM_GRP_B2DS, 0x00000030,
 787 MX6_IOM_GRP_B3DS, 0x00000030,
 788 MX6_IOM_GRP_B4DS, 0x00000030,
 789 MX6_IOM_GRP_B5DS, 0x00000030,
 790 MX6_IOM_GRP_B6DS, 0x00000030,
 791 MX6_IOM_GRP_B7DS, 0x00000030,
 792 MX6_IOM_GRP_ADDDS, 0x00000030,
 793 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 794 MX6_IOM_GRP_CTLDS, 0x00000030,
 795
 796 MX6_IOM_DRAM_DQM0, 0x00020030,
 797 MX6_IOM_DRAM_DQM1, 0x00020030,
 798 MX6_IOM_DRAM_DQM2, 0x00020030,
 799 MX6_IOM_DRAM_DQM3, 0x00020030,
 800 MX6_IOM_DRAM_DQM4, 0x00020030,
 801 MX6_IOM_DRAM_DQM5, 0x00020030,
 802 MX6_IOM_DRAM_DQM6, 0x00020030,
 803 MX6_IOM_DRAM_DQM7, 0x00020030,
 804
 805 MX6_IOM_DRAM_CAS, 0x00020030,
 806 MX6_IOM_DRAM_RAS, 0x00020030,
 807 MX6_IOM_DRAM_SDCLK_0, 0x00020030,
 808 MX6_IOM_DRAM_SDCLK_1, 0x00020030,
 809
 810 MX6_IOM_DRAM_RESET, 0x00020030,
 811 MX6_IOM_DRAM_SDCKE0, 0x00003000,
 812 MX6_IOM_DRAM_SDCKE1, 0x00003000,
 813
 814 MX6_IOM_DRAM_SDODT0, 0x00003030,
 815 MX6_IOM_DRAM_SDODT1, 0x00003030,
 816
 817 /* (differential input) */
 818 MX6_IOM_DDRMODE_CTL, 0x00020000,
 819 /* (differential input) */
 820 MX6_IOM_GRP_DDRMODE, 0x00020000,
 821 /* disable ddr pullups */
 822 MX6_IOM_GRP_DDRPKE, 0x00000000,
 823 MX6_IOM_DRAM_SDBA2, 0x00000000,
 824 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 825 MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
 826
 827 /* Read data DQ Byte0-3 delay */
 828 MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
 829 MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
 830 MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
 831 MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
 832 MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
 833 MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
 834 MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
 835 MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
 836
 837 /*
 838  * MDMISC       mirroring       interleaved (row/bank/col)
 839  */
 840 /* TODO: check what the RALAT field does */
 841 MX6_MMDC_P0_MDMISC, 0x00081740,
 842
 843 /*
 844  * MDSCR        con_req
 845  */
 846 MX6_MMDC_P0_MDSCR, 0x00008000,
 847
 848
 849 /* 800mhz_2x64mx16.cfg */
 850
 851 MX6_MMDC_P0_MDPDC, 0x0002002D,
 852 MX6_MMDC_P0_MDCFG0, 0x2C305503,
 853 MX6_MMDC_P0_MDCFG1, 0xB66D8D63,
 854 MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
 855 MX6_MMDC_P0_MDRWD, 0x000026D2,
 856 MX6_MMDC_P0_MDOR, 0x00301023,
 857 MX6_MMDC_P0_MDOTC, 0x00333030,
 858 MX6_MMDC_P0_MDPDC, 0x0002556D,
 859 /* CS0 End: 7MSB of ((0x10000000, + 512M) -1) >> 25 */
 860 MX6_MMDC_P0_MDASP, 0x00000017,
 861 /* DDR3 DATA BUS SIZE: 64BIT */
 862 /* MX6_MMDC_P0_MDCTL, 0x821A0000, */
 863 /* DDR3 DATA BUS SIZE: 32BIT */
 864 MX6_MMDC_P0_MDCTL, 0x82190000,
 865
 866 /* Write commands to DDR */
 867 /* Load Mode Registers */
 868 /* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
 869 /* MX6_MMDC_P0_MDSCR, 0x04408032, */
 870 MX6_MMDC_P0_MDSCR, 0x04008032,
 871 MX6_MMDC_P0_MDSCR, 0x00008033,
 872 MX6_MMDC_P0_MDSCR, 0x00048031,
 873 MX6_MMDC_P0_MDSCR, 0x13208030,
 874 /* ZQ calibration */
 875 MX6_MMDC_P0_MDSCR, 0x04008040,
 876
 877 MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
 878 MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
 879 MX6_MMDC_P0_MDREF, 0x00005800,
 880
 881 MX6_MMDC_P0_MPODTCTRL, 0x00000000,
 882 MX6_MMDC_P1_MPODTCTRL, 0x00000000,
 883
 884 MX6_MMDC_P0_MPDGCTRL0, 0x42360232,
 885 MX6_MMDC_P0_MPDGCTRL1, 0x021F022A,
 886 MX6_MMDC_P1_MPDGCTRL0, 0x421E0224,
 887 MX6_MMDC_P1_MPDGCTRL1, 0x02110218,
 888
 889 MX6_MMDC_P0_MPRDDLCTL, 0x41434344,
 890 MX6_MMDC_P1_MPRDDLCTL, 0x4345423E,
 891 MX6_MMDC_P0_MPWRDLCTL, 0x39383339,
 892 MX6_MMDC_P1_MPWRDLCTL, 0x3E363930,
 893
 894 MX6_MMDC_P0_MPWLDECTRL0, 0x00340039,
 895 MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D,
 896 MX6_MMDC_P1_MPWLDECTRL0, 0x00120019,
 897 MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D,
 898
 899 MX6_MMDC_P0_MPMUR0, 0x00000800,
 900 MX6_MMDC_P1_MPMUR0, 0x00000800,
 901 MX6_MMDC_P0_MDSCR, 0x00000000,
 902 MX6_MMDC_P0_MAPSR, 0x00011006,
 903 };
 904
 905 static int mx6dl_dcd_table[] = {
 906 /* ddr-setup.cfg */
 907
 908 MX6_IOM_DRAM_SDQS0, 0x00000030,
 909 MX6_IOM_DRAM_SDQS1, 0x00000030,
 910 MX6_IOM_DRAM_SDQS2, 0x00000030,
 911 MX6_IOM_DRAM_SDQS3, 0x00000030,
 912 MX6_IOM_DRAM_SDQS4, 0x00000030,
 913 MX6_IOM_DRAM_SDQS5, 0x00000030,
 914 MX6_IOM_DRAM_SDQS6, 0x00000030,
 915 MX6_IOM_DRAM_SDQS7, 0x00000030,
 916
 917 MX6_IOM_GRP_B0DS, 0x00000030,
 918 MX6_IOM_GRP_B1DS, 0x00000030,
 919 MX6_IOM_GRP_B2DS, 0x00000030,
 920 MX6_IOM_GRP_B3DS, 0x00000030,
 921 MX6_IOM_GRP_B4DS, 0x00000030,
 922 MX6_IOM_GRP_B5DS, 0x00000030,
 923 MX6_IOM_GRP_B6DS, 0x00000030,
 924 MX6_IOM_GRP_B7DS, 0x00000030,
 925 MX6_IOM_GRP_ADDDS, 0x00000030,
 926 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 927 MX6_IOM_GRP_CTLDS, 0x00000030,
 928
 929 MX6_IOM_DRAM_DQM0, 0x00020030,
 930 MX6_IOM_DRAM_DQM1, 0x00020030,
 931 MX6_IOM_DRAM_DQM2, 0x00020030,
 932 MX6_IOM_DRAM_DQM3, 0x00020030,
 933 MX6_IOM_DRAM_DQM4, 0x00020030,
 934 MX6_IOM_DRAM_DQM5, 0x00020030,
 935 MX6_IOM_DRAM_DQM6, 0x00020030,
 936 MX6_IOM_DRAM_DQM7, 0x00020030,
 937
 938 MX6_IOM_DRAM_CAS, 0x00020030,
 939 MX6_IOM_DRAM_RAS, 0x00020030,
 940 MX6_IOM_DRAM_SDCLK_0, 0x00020030,
 941 MX6_IOM_DRAM_SDCLK_1, 0x00020030,
 942
 943 MX6_IOM_DRAM_RESET, 0x00020030,
 944 MX6_IOM_DRAM_SDCKE0, 0x00003000,
 945 MX6_IOM_DRAM_SDCKE1, 0x00003000,
 946
 947 MX6_IOM_DRAM_SDODT0, 0x00003030,
 948 MX6_IOM_DRAM_SDODT1, 0x00003030,
 949
 950 /* (differential input) */
 951 MX6_IOM_DDRMODE_CTL, 0x00020000,
 952 /* (differential input) */
 953 MX6_IOM_GRP_DDRMODE, 0x00020000,
 954 /* disable ddr pullups */
 955 MX6_IOM_GRP_DDRPKE, 0x00000000,
 956 MX6_IOM_DRAM_SDBA2, 0x00000000,
 957 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 958 MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
 959
 960 /* Read data DQ Byte0-3 delay */
 961 MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
 962 MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
 963 MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
 964 MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
 965 MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
 966 MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
 967 MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
 968 MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
 969
 970 /*
 971  * MDMISC       mirroring       interleaved (row/bank/col)
 972  */
 973 /* TODO: check what the RALAT field does */
 974 MX6_MMDC_P0_MDMISC, 0x00081740,
 975
 976 /*
 977  * MDSCR        con_req
 978  */
 979 MX6_MMDC_P0_MDSCR, 0x00008000,
 980
 981
 982 /* 800mhz_2x64mx16.cfg */
 983
 984 MX6_MMDC_P0_MDPDC, 0x0002002D,
 985 MX6_MMDC_P0_MDCFG0, 0x2C305503,
 986 MX6_MMDC_P0_MDCFG1, 0xB66D8D63,
 987 MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
 988 MX6_MMDC_P0_MDRWD, 0x000026D2,
 989 MX6_MMDC_P0_MDOR, 0x00301023,
 990 MX6_MMDC_P0_MDOTC, 0x00333030,
 991 MX6_MMDC_P0_MDPDC, 0x0002556D,
 992 /* CS0 End: 7MSB of ((0x10000000, + 512M) -1) >> 25 */
 993 MX6_MMDC_P0_MDASP, 0x00000017,
 994 /* DDR3 DATA BUS SIZE: 64BIT */
 995 MX6_MMDC_P0_MDCTL, 0x821A0000,
 996 /* DDR3 DATA BUS SIZE: 32BIT */
 997 /* MX6_MMDC_P0_MDCTL, 0x82190000, */
 998
 999 /* Write commands to DDR */
1000 /* Load Mode Registers */
1001 /* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
1002 /* MX6_MMDC_P0_MDSCR, 0x04408032, */
1003 MX6_MMDC_P0_MDSCR, 0x04008032,
1004 MX6_MMDC_P0_MDSCR, 0x00008033,
1005 MX6_MMDC_P0_MDSCR, 0x00048031,
1006 MX6_MMDC_P0_MDSCR, 0x13208030,
1007 /* ZQ calibration */
1008 MX6_MMDC_P0_MDSCR, 0x04008040,
1009
1010 MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
1011 MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
1012 MX6_MMDC_P0_MDREF, 0x00005800,
1013
1014 MX6_MMDC_P0_MPODTCTRL, 0x00000000,
1015 MX6_MMDC_P1_MPODTCTRL, 0x00000000,
1016
1017 MX6_MMDC_P0_MPDGCTRL0, 0x42360232,
1018 MX6_MMDC_P0_MPDGCTRL1, 0x021F022A,
1019 MX6_MMDC_P1_MPDGCTRL0, 0x421E0224,
1020 MX6_MMDC_P1_MPDGCTRL1, 0x02110218,
1021
1022 MX6_MMDC_P0_MPRDDLCTL, 0x41434344,
1023 MX6_MMDC_P1_MPRDDLCTL, 0x4345423E,
1024 MX6_MMDC_P0_MPWRDLCTL, 0x39383339,
1025 MX6_MMDC_P1_MPWRDLCTL, 0x3E363930,
1026
1027 MX6_MMDC_P0_MPWLDECTRL0, 0x00340039,
1028 MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D,
1029 MX6_MMDC_P1_MPWLDECTRL0, 0x00120019,
1030 MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D,
1031
1032 MX6_MMDC_P0_MPMUR0, 0x00000800,
1033 MX6_MMDC_P1_MPMUR0, 0x00000800,
1034 MX6_MMDC_P0_MDSCR, 0x00000000,
1035 MX6_MMDC_P0_MAPSR, 0x00011006,
1036 };
1037
1038 static void ccgr_init(void)
1039 {
1040         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1041
1042         writel(0x00C03F3F, &ccm->CCGR0);
1043         writel(0x0030FC03, &ccm->CCGR1);
1044         writel(0x0FFFFFF3, &ccm->CCGR2);
1045         writel(0x3FF0300F, &ccm->CCGR3);
1046         writel(0x00FFF300, &ccm->CCGR4);
1047         writel(0x0F0000F3, &ccm->CCGR5);
1048         writel(0x000003FF, &ccm->CCGR6);
1049
1050 /*
1051  * Setup CCM_CCOSR register as follows:
1052  *
1053  * cko1_en  = 1    --> CKO1 enabled
1054  * cko1_div = 111  --> divide by 8
1055  * cko1_sel = 1011 --> ahb_clk_root
1056  *
1057  * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
1058  */
1059         writel(0x000000FB, &ccm->ccosr);
1060 }
1061
1062 static void ddr_init(int *table, int size)
1063 {
1064         int i;
1065
1066         for (i = 0; i < size / 2 ; i++)
1067                 writel(table[2 * i + 1], table[2 * i]);
1068 }
1069
1070 static void spl_dram_init(void)
1071 {
1072         int minc, maxc;
1073
1074         switch (get_cpu_temp_grade(&minc, &maxc)) {
1075         case TEMP_COMMERCIAL:
1076         case TEMP_EXTCOMMERCIAL:
1077                 if (is_cpu_type(MXC_CPU_MX6DL)) {
1078                         puts("Commercial temperature grade DDR3 timings, 64bit bus width.\n");
1079                         ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
1080                 } else {
1081                         puts("Commercial temperature grade DDR3 timings, 32bit bus width.\n");
1082                         ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
1083                 }
1084                 break;
1085         case TEMP_INDUSTRIAL:
1086         case TEMP_AUTOMOTIVE:
1087         default:
1088                 if (is_cpu_type(MXC_CPU_MX6DL)) {
1089                         ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
1090                 } else {
1091                         puts("Industrial temperature grade DDR3 timings, 32bit bus width.\n");
1092                         ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
1093                 }
1094                 break;
1095         };
1096         udelay(100);
1097 }
1098
1099 void board_init_f(ulong dummy)
1100 {
1101         /* setup AIPS and disable watchdog */
1102         arch_cpu_init();
1103
1104         ccgr_init();
1105         gpr_init();
1106
1107         /* iomux */
1108         board_early_init_f();
1109
1110         /* setup GP timer */
1111         timer_init();
1112
1113         /* UART clocks enabled and gd valid - init serial console */
1114         preloader_console_init();
1115
1116         /* Make sure we use dte mode */
1117         setup_dtemode_uart();
1118
1119         /* DDR initialization */
1120         spl_dram_init();
1121
1122         /* Clear the BSS. */
1123         memset(__bss_start, 0, __bss_end - __bss_start);
1124
1125         /* load/boot image from boot device */
1126         board_init_r(NULL, 0);
1127 }
1128
1129 void reset_cpu(ulong addr)
1130 {
1131 }
1132
1133 #endif /* CONFIG_SPL_BUILD */
1134
1135 static struct mxc_serial_platdata mxc_serial_plat = {
1136         .reg = (struct mxc_uart *)UART1_BASE,
1137         .use_dte = true,
1138 };
1139
1140 U_BOOT_DEVICE(mxc_serial) = {
1141         .name = "serial_mxc",
1142         .platdata = &mxc_serial_plat,
1143 };