board/toradex/apalis_imx6/apalis_imx6.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
   4  * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
   5  * Copyright (C) 2014-2019, Toradex AG
   6  * copied from nitrogen6x
   7  */
   8
   9 #include <common.h>
  10 #include <cpu_func.h>
  11 #include <dm.h>
  12 #include <init.h>
  13
  14 #include <ahci.h>
  15 #include <asm/arch/clock.h>
  16 #include <asm/arch/crm_regs.h>
  17 #include <asm/arch/imx-regs.h>
  18 #include <asm/arch/mx6-ddr.h>
  19 #include <asm/arch/mx6-pins.h>
  20 #include <asm/arch/mxc_hdmi.h>
  21 #include <asm/arch/sys_proto.h>
  22 #include <asm/bootm.h>
  23 #include <asm/gpio.h>
  24 #include <asm/mach-imx/boot_mode.h>
  25 #include <asm/mach-imx/iomux-v3.h>
  26 #include <asm/mach-imx/sata.h>
  27 #include <asm/mach-imx/video.h>
  28 #include <dm/device-internal.h>
  29 #include <dm/platform_data/serial_mxc.h>
  30 #include <dwc_ahsata.h>
  31 #include <env.h>
  32 #include <fsl_esdhc_imx.h>
  33 #include <imx_thermal.h>
  34 #include <micrel.h>
  35 #include <miiphy.h>
  36 #include <netdev.h>
  37
  38 #include "../common/tdx-cfg-block.h"
  39 #ifdef CONFIG_TDX_CMD_IMX_MFGR
  40 #include "pf0100.h"
  41 #endif
  42
  43 DECLARE_GLOBAL_DATA_PTR;
  44
  45 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  46         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  47         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  48
  49 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  50         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm |                 \
  51         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  52
  53 #define USDHC_EMMC_PAD_CTRL (PAD_CTL_PUS_47K_UP |               \
  54         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  55         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  56
  57 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  58         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  59
  60 #define WEAK_PULLUP     (PAD_CTL_PUS_100K_UP |                  \
  61         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  62         PAD_CTL_SRE_SLOW)
  63
  64 #define WEAK_PULLDOWN   (PAD_CTL_PUS_100K_DOWN |                \
  65         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  66         PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
  67
  68 #define TRISTATE        (PAD_CTL_HYS | PAD_CTL_SPEED_MED)
  69
  70 #define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST)
  71
  72 #define APALIS_IMX6_SATA_INIT_RETRIES   10
  73
  74 int dram_init(void)
  75 {
  76         /* use the DDR controllers configured size */
  77         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  78                                     (ulong)imx_ddr_size());
  79
  80         return 0;
  81 }
  82
  83 /* Apalis UART1 */
  84 iomux_v3_cfg_t const uart1_pads_dce[] = {
  85         MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  86         MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  87 };
  88 iomux_v3_cfg_t const uart1_pads_dte[] = {
  89         MX6_PAD_CSI0_DAT10__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  90         MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  91 };
  92
  93 #if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
  94 /* Apalis MMC1 */
  95 iomux_v3_cfg_t const usdhc1_pads[] = {
  96         MX6_PAD_SD1_CLK__SD1_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  97         MX6_PAD_SD1_CMD__SD1_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  98         MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  99         MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 100         MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 101         MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 102         MX6_PAD_NANDF_D0__SD1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 103         MX6_PAD_NANDF_D1__SD1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 104         MX6_PAD_NANDF_D2__SD1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 105         MX6_PAD_NANDF_D3__SD1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 106         MX6_PAD_DI0_PIN4__GPIO4_IO20   | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 107 #       define GPIO_MMC_CD IMX_GPIO_NR(4, 20)
 108 };
 109
 110 /* Apalis SD1 */
 111 iomux_v3_cfg_t const usdhc2_pads[] = {
 112         MX6_PAD_SD2_CLK__SD2_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 113         MX6_PAD_SD2_CMD__SD2_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 114         MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 115         MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 116         MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 117         MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 118         MX6_PAD_NANDF_CS1__GPIO6_IO14  | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 119 #       define GPIO_SD_CD IMX_GPIO_NR(6, 14)
 120 };
 121
 122 /* eMMC */
 123 iomux_v3_cfg_t const usdhc3_pads[] = {
 124         MX6_PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 125         MX6_PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 126         MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 127         MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 128         MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 129         MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 130         MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 131         MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 132         MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 133         MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 134         MX6_PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) | MUX_MODE_SION,
 135 };
 136 #endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
 137
 138 int mx6_rgmii_rework(struct phy_device *phydev)
 139 {
 140         /* control data pad skew - devaddr = 0x02, register = 0x04 */
 141         ksz9031_phy_extended_write(phydev, 0x02,
 142                                    MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
 143                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
 144         /* rx data pad skew - devaddr = 0x02, register = 0x05 */
 145         ksz9031_phy_extended_write(phydev, 0x02,
 146                                    MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
 147                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
 148         /* tx data pad skew - devaddr = 0x02, register = 0x05 */
 149         ksz9031_phy_extended_write(phydev, 0x02,
 150                                    MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
 151                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
 152         /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
 153         ksz9031_phy_extended_write(phydev, 0x02,
 154                                    MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
 155                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
 156         return 0;
 157 }
 158
 159 iomux_v3_cfg_t const enet_pads[] = {
 160         MX6_PAD_ENET_MDIO__ENET_MDIO            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 161         MX6_PAD_ENET_MDC__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
 162         MX6_PAD_RGMII_TXC__RGMII_TXC            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 163         MX6_PAD_RGMII_TD0__RGMII_TD0            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 164         MX6_PAD_RGMII_TD1__RGMII_TD1            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 165         MX6_PAD_RGMII_TD2__RGMII_TD2            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 166         MX6_PAD_RGMII_TD3__RGMII_TD3            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 167         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 168         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 169         MX6_PAD_RGMII_RXC__RGMII_RXC            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 170         MX6_PAD_RGMII_RD0__RGMII_RD0            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 171         MX6_PAD_RGMII_RD1__RGMII_RD1            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 172         MX6_PAD_RGMII_RD2__RGMII_RD2            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 173         MX6_PAD_RGMII_RD3__RGMII_RD3            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 174         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 175         /* KSZ9031 PHY Reset */
 176         MX6_PAD_ENET_CRS_DV__GPIO1_IO25         | MUX_PAD_CTRL(NO_PAD_CTRL) |
 177                                                   MUX_MODE_SION,
 178 #       define GPIO_ENET_PHY_RESET IMX_GPIO_NR(1, 25)
 179 };
 180
 181 /* mux the Apalis GPIO pins, so they can be used from the U-Boot cmdline */
 182 iomux_v3_cfg_t const gpio_pads[] = {
 183         /* Apalis GPIO1 - GPIO8 */
 184         MX6_PAD_NANDF_D4__GPIO2_IO04    | MUX_PAD_CTRL(WEAK_PULLUP) |
 185                                           MUX_MODE_SION,
 186         MX6_PAD_NANDF_D5__GPIO2_IO05    | MUX_PAD_CTRL(WEAK_PULLUP) |
 187                                           MUX_MODE_SION,
 188         MX6_PAD_NANDF_D6__GPIO2_IO06    | MUX_PAD_CTRL(WEAK_PULLUP) |
 189                                           MUX_MODE_SION,
 190         MX6_PAD_NANDF_D7__GPIO2_IO07    | MUX_PAD_CTRL(WEAK_PULLUP) |
 191                                           MUX_MODE_SION,
 192         MX6_PAD_NANDF_RB0__GPIO6_IO10   | MUX_PAD_CTRL(WEAK_PULLUP) |
 193                                           MUX_MODE_SION,
 194         MX6_PAD_NANDF_WP_B__GPIO6_IO09  | MUX_PAD_CTRL(WEAK_PULLUP) |
 195                                           MUX_MODE_SION,
 196         MX6_PAD_GPIO_2__GPIO1_IO02      | MUX_PAD_CTRL(WEAK_PULLDOWN) |
 197                                           MUX_MODE_SION,
 198         MX6_PAD_GPIO_6__GPIO1_IO06      | MUX_PAD_CTRL(WEAK_PULLUP) |
 199                                           MUX_MODE_SION,
 200         MX6_PAD_GPIO_4__GPIO1_IO04      | MUX_PAD_CTRL(WEAK_PULLUP) |
 201                                           MUX_MODE_SION,
 202 };
 203
 204 static void setup_iomux_gpio(void)
 205 {
 206         imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
 207 }
 208
 209 iomux_v3_cfg_t const usb_pads[] = {
 210         /* USBH_EN */
 211         MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
 212 #       define GPIO_USBH_EN IMX_GPIO_NR(1, 0)
 213         /* USB_VBUS_DET */
 214         MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
 215 #       define GPIO_USB_VBUS_DET IMX_GPIO_NR(3, 28)
 216         /* USBO1_ID */
 217         MX6_PAD_ENET_RX_ER__USB_OTG_ID  | MUX_PAD_CTRL(WEAK_PULLUP),
 218         /* USBO1_EN */
 219         MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
 220 #       define GPIO_USBO_EN IMX_GPIO_NR(3, 22)
 221 };
 222
 223 /*
 224  * UARTs are used in DTE mode, switch the mode on all UARTs before
 225  * any pinmuxing connects a (DCE) output to a transceiver output.
 226  */
 227 #define UCR3            0x88    /* FIFO Control Register */
 228 #define UCR3_RI         BIT(8)  /* RIDELT DTE mode */
 229 #define UCR3_DCD        BIT(9)  /* DCDDELT DTE mode */
 230 #define UFCR            0x90    /* FIFO Control Register */
 231 #define UFCR_DCEDTE     BIT(6)  /* DCE=0 */
 232
 233 static void setup_dtemode_uart(void)
 234 {
 235         setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
 236         setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
 237         setbits_le32((u32 *)(UART4_BASE + UFCR), UFCR_DCEDTE);
 238         setbits_le32((u32 *)(UART5_BASE + UFCR), UFCR_DCEDTE);
 239
 240         clrbits_le32((u32 *)(UART1_BASE + UCR3), UCR3_DCD | UCR3_RI);
 241         clrbits_le32((u32 *)(UART2_BASE + UCR3), UCR3_DCD | UCR3_RI);
 242         clrbits_le32((u32 *)(UART4_BASE + UCR3), UCR3_DCD | UCR3_RI);
 243         clrbits_le32((u32 *)(UART5_BASE + UCR3), UCR3_DCD | UCR3_RI);
 244 }
 245 static void setup_dcemode_uart(void)
 246 {
 247         clrbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
 248         clrbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
 249         clrbits_le32((u32 *)(UART4_BASE + UFCR), UFCR_DCEDTE);
 250         clrbits_le32((u32 *)(UART5_BASE + UFCR), UFCR_DCEDTE);
 251 }
 252
 253 static void setup_iomux_dte_uart(void)
 254 {
 255         setup_dtemode_uart();
 256         imx_iomux_v3_setup_multiple_pads(uart1_pads_dte,
 257                                          ARRAY_SIZE(uart1_pads_dte));
 258 }
 259 static void setup_iomux_dce_uart(void)
 260 {
 261         setup_dcemode_uart();
 262         imx_iomux_v3_setup_multiple_pads(uart1_pads_dce,
 263                                          ARRAY_SIZE(uart1_pads_dce));
 264 }
 265
 266 #ifdef CONFIG_USB_EHCI_MX6
 267 int board_ehci_hcd_init(int port)
 268 {
 269         imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
 270         return 0;
 271 }
 272 #endif
 273
 274 #if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
 275 /* use the following sequence: eMMC, MMC1, SD1 */
 276 struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
 277         {USDHC3_BASE_ADDR},
 278         {USDHC1_BASE_ADDR},
 279         {USDHC2_BASE_ADDR},
 280 };
 281
 282 int board_mmc_getcd(struct mmc *mmc)
 283 {
 284         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 285         int ret = true; /* default: assume inserted */
 286
 287         switch (cfg->esdhc_base) {
 288         case USDHC1_BASE_ADDR:
 289                 gpio_request(GPIO_MMC_CD, "MMC_CD");
 290                 gpio_direction_input(GPIO_MMC_CD);
 291                 ret = !gpio_get_value(GPIO_MMC_CD);
 292                 break;
 293         case USDHC2_BASE_ADDR:
 294                 gpio_request(GPIO_MMC_CD, "SD_CD");
 295                 gpio_direction_input(GPIO_SD_CD);
 296                 ret = !gpio_get_value(GPIO_SD_CD);
 297                 break;
 298         }
 299
 300         return ret;
 301 }
 302
 303 int board_mmc_init(bd_t *bis)
 304 {
 305         struct src *psrc = (struct src *)SRC_BASE_ADDR;
 306         unsigned reg = readl(&psrc->sbmr1) >> 11;
 307         /*
 308          * Upon reading BOOT_CFG register the following map is done:
 309          * Bit 11 and 12 of BOOT_CFG register can determine the current
 310          * mmc port
 311          * 0x1                  SD1
 312          * 0x2                  SD2
 313          * 0x3                  SD4
 314          */
 315
 316         switch (reg & 0x3) {
 317         case 0x0:
 318                 imx_iomux_v3_setup_multiple_pads(
 319                         usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
 320                 usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
 321                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 322                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 323                 break;
 324         case 0x1:
 325                 imx_iomux_v3_setup_multiple_pads(
 326                         usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 327                 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
 328                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 329                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 330                 break;
 331         case 0x2:
 332                 imx_iomux_v3_setup_multiple_pads(
 333                         usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 334                 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
 335                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 336                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 337                 break;
 338         default:
 339                 puts("MMC boot device not available");
 340         }
 341
 342         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 343 }
 344 #endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
 345
 346 int board_phy_config(struct phy_device *phydev)
 347 {
 348         mx6_rgmii_rework(phydev);
 349         if (phydev->drv->config)
 350                 phydev->drv->config(phydev);
 351
 352         return 0;
 353 }
 354
 355 static iomux_v3_cfg_t const pwr_intb_pads[] = {
 356         /*
 357          * the bootrom sets the iomux to vselect, potentially connecting
 358          * two outputs. Set this back to GPIO
 359          */
 360         MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)
 361 };
 362
 363 #if defined(CONFIG_VIDEO_IPUV3)
 364
 365 static iomux_v3_cfg_t const backlight_pads[] = {
 366         /* Backlight on RGB connector: J15 */
 367         MX6_PAD_EIM_DA13__GPIO3_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL) |
 368                                        MUX_MODE_SION,
 369 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 13)
 370         /* additional CPU pin on BKL_PWM, keep in tristate */
 371         MX6_PAD_EIM_DA14__GPIO3_IO14 | MUX_PAD_CTRL(TRISTATE),
 372         /* Backlight PWM, used as GPIO in U-Boot */
 373         MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL) |
 374                                        MUX_MODE_SION,
 375 #define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 10)
 376         /* buffer output enable 0: buffer enabled */
 377         MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(WEAK_PULLUP) | MUX_MODE_SION,
 378 #define RGB_BACKLIGHTPWM_OE IMX_GPIO_NR(5, 2)
 379         /* PSAVE# integrated VDAC */
 380         MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL) |
 381                                        MUX_MODE_SION,
 382 #define VGA_PSAVE_NOT_GP IMX_GPIO_NR(6, 31)
 383 };
 384
 385 static iomux_v3_cfg_t const rgb_pads[] = {
 386         MX6_PAD_EIM_A16__IPU1_DI1_DISP_CLK | MUX_PAD_CTRL(OUTPUT_RGB),
 387         MX6_PAD_EIM_DA10__IPU1_DI1_PIN15 | MUX_PAD_CTRL(OUTPUT_RGB),
 388         MX6_PAD_EIM_DA11__IPU1_DI1_PIN02 | MUX_PAD_CTRL(OUTPUT_RGB),
 389         MX6_PAD_EIM_DA12__IPU1_DI1_PIN03 | MUX_PAD_CTRL(OUTPUT_RGB),
 390         MX6_PAD_EIM_DA9__IPU1_DISP1_DATA00 | MUX_PAD_CTRL(OUTPUT_RGB),
 391         MX6_PAD_EIM_DA8__IPU1_DISP1_DATA01 | MUX_PAD_CTRL(OUTPUT_RGB),
 392         MX6_PAD_EIM_DA7__IPU1_DISP1_DATA02 | MUX_PAD_CTRL(OUTPUT_RGB),
 393         MX6_PAD_EIM_DA6__IPU1_DISP1_DATA03 | MUX_PAD_CTRL(OUTPUT_RGB),
 394         MX6_PAD_EIM_DA5__IPU1_DISP1_DATA04 | MUX_PAD_CTRL(OUTPUT_RGB),
 395         MX6_PAD_EIM_DA4__IPU1_DISP1_DATA05 | MUX_PAD_CTRL(OUTPUT_RGB),
 396         MX6_PAD_EIM_DA3__IPU1_DISP1_DATA06 | MUX_PAD_CTRL(OUTPUT_RGB),
 397         MX6_PAD_EIM_DA2__IPU1_DISP1_DATA07 | MUX_PAD_CTRL(OUTPUT_RGB),
 398         MX6_PAD_EIM_DA1__IPU1_DISP1_DATA08 | MUX_PAD_CTRL(OUTPUT_RGB),
 399         MX6_PAD_EIM_DA0__IPU1_DISP1_DATA09 | MUX_PAD_CTRL(OUTPUT_RGB),
 400         MX6_PAD_EIM_EB1__IPU1_DISP1_DATA10 | MUX_PAD_CTRL(OUTPUT_RGB),
 401         MX6_PAD_EIM_EB0__IPU1_DISP1_DATA11 | MUX_PAD_CTRL(OUTPUT_RGB),
 402         MX6_PAD_EIM_A17__IPU1_DISP1_DATA12 | MUX_PAD_CTRL(OUTPUT_RGB),
 403         MX6_PAD_EIM_A18__IPU1_DISP1_DATA13 | MUX_PAD_CTRL(OUTPUT_RGB),
 404         MX6_PAD_EIM_A19__IPU1_DISP1_DATA14 | MUX_PAD_CTRL(OUTPUT_RGB),
 405         MX6_PAD_EIM_A20__IPU1_DISP1_DATA15 | MUX_PAD_CTRL(OUTPUT_RGB),
 406         MX6_PAD_EIM_A21__IPU1_DISP1_DATA16 | MUX_PAD_CTRL(OUTPUT_RGB),
 407         MX6_PAD_EIM_A22__IPU1_DISP1_DATA17 | MUX_PAD_CTRL(OUTPUT_RGB),
 408         MX6_PAD_EIM_A23__IPU1_DISP1_DATA18 | MUX_PAD_CTRL(OUTPUT_RGB),
 409         MX6_PAD_EIM_A24__IPU1_DISP1_DATA19 | MUX_PAD_CTRL(OUTPUT_RGB),
 410         MX6_PAD_EIM_D26__IPU1_DISP1_DATA22 | MUX_PAD_CTRL(OUTPUT_RGB),
 411         MX6_PAD_EIM_D27__IPU1_DISP1_DATA23 | MUX_PAD_CTRL(OUTPUT_RGB),
 412         MX6_PAD_EIM_D30__IPU1_DISP1_DATA21 | MUX_PAD_CTRL(OUTPUT_RGB),
 413         MX6_PAD_EIM_D31__IPU1_DISP1_DATA20 | MUX_PAD_CTRL(OUTPUT_RGB),
 414 };
 415
 416 static void do_enable_hdmi(struct display_info_t const *dev)
 417 {
 418         imx_enable_hdmi_phy();
 419 }
 420
 421 static void enable_lvds(struct display_info_t const *dev)
 422 {
 423         struct iomuxc *iomux = (struct iomuxc *)
 424                                 IOMUXC_BASE_ADDR;
 425         u32 reg = readl(&iomux->gpr[2]);
 426         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
 427         writel(reg, &iomux->gpr[2]);
 428         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 429         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
 430         gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
 431 }
 432
 433 static void enable_rgb(struct display_info_t const *dev)
 434 {
 435         imx_iomux_v3_setup_multiple_pads(
 436                 rgb_pads,
 437                 ARRAY_SIZE(rgb_pads));
 438         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 439         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
 440         gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
 441 }
 442
 443 static int detect_default(struct display_info_t const *dev)
 444 {
 445         (void) dev;
 446         return 1;
 447 }
 448
 449 struct display_info_t const displays[] = {{
 450         .bus    = -1,
 451         .addr   = 0,
 452         .pixfmt = IPU_PIX_FMT_RGB24,
 453         .detect = detect_hdmi,
 454         .enable = do_enable_hdmi,
 455         .mode   = {
 456                 .name           = "HDMI",
 457                 .refresh        = 60,
 458                 .xres           = 1024,
 459                 .yres           = 768,
 460                 .pixclock       = 15385,
 461                 .left_margin    = 220,
 462                 .right_margin   = 40,
 463                 .upper_margin   = 21,
 464                 .lower_margin   = 7,
 465                 .hsync_len      = 60,
 466                 .vsync_len      = 10,
 467                 .sync           = FB_SYNC_EXT,
 468                 .vmode          = FB_VMODE_NONINTERLACED
 469 } }, {
 470         .bus    = -1,
 471         .addr   = 0,
 472         .di     = 1,
 473         .pixfmt = IPU_PIX_FMT_RGB24,
 474         .detect = detect_default,
 475         .enable = enable_rgb,
 476         .mode   = {
 477                 .name           = "vga-rgb",
 478                 .refresh        = 60,
 479                 .xres           = 640,
 480                 .yres           = 480,
 481                 .pixclock       = 33000,
 482                 .left_margin    = 48,
 483                 .right_margin   = 16,
 484                 .upper_margin   = 31,
 485                 .lower_margin   = 11,
 486                 .hsync_len      = 96,
 487                 .vsync_len      = 2,
 488                 .sync           = 0,
 489                 .vmode          = FB_VMODE_NONINTERLACED
 490 } }, {
 491         .bus    = -1,
 492         .addr   = 0,
 493         .di     = 1,
 494         .pixfmt = IPU_PIX_FMT_RGB24,
 495         .enable = enable_rgb,
 496         .mode   = {
 497                 .name           = "wvga-rgb",
 498                 .refresh        = 60,
 499                 .xres           = 800,
 500                 .yres           = 480,
 501                 .pixclock       = 25000,
 502                 .left_margin    = 40,
 503                 .right_margin   = 88,
 504                 .upper_margin   = 33,
 505                 .lower_margin   = 10,
 506                 .hsync_len      = 128,
 507                 .vsync_len      = 2,
 508                 .sync           = 0,
 509                 .vmode          = FB_VMODE_NONINTERLACED
 510 } }, {
 511         .bus    = -1,
 512         .addr   = 0,
 513         .pixfmt = IPU_PIX_FMT_LVDS666,
 514         .enable = enable_lvds,
 515         .mode   = {
 516                 .name           = "wsvga-lvds",
 517                 .refresh        = 60,
 518                 .xres           = 1024,
 519                 .yres           = 600,
 520                 .pixclock       = 15385,
 521                 .left_margin    = 220,
 522                 .right_margin   = 40,
 523                 .upper_margin   = 21,
 524                 .lower_margin   = 7,
 525                 .hsync_len      = 60,
 526                 .vsync_len      = 10,
 527                 .sync           = FB_SYNC_EXT,
 528                 .vmode          = FB_VMODE_NONINTERLACED
 529 } } };
 530 size_t display_count = ARRAY_SIZE(displays);
 531
 532 static void setup_display(void)
 533 {
 534         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 535         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 536         int reg;
 537
 538         enable_ipu_clock();
 539         imx_setup_hdmi();
 540         /* Turn on LDB0,IPU,IPU DI0 clocks */
 541         reg = __raw_readl(&mxc_ccm->CCGR3);
 542         reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
 543         writel(reg, &mxc_ccm->CCGR3);
 544
 545         /* set LDB0, LDB1 clk select to 011/011 */
 546         reg = readl(&mxc_ccm->cs2cdr);
 547         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 548                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 549         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 550               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 551         writel(reg, &mxc_ccm->cs2cdr);
 552
 553         reg = readl(&mxc_ccm->cscmr2);
 554         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 555         writel(reg, &mxc_ccm->cscmr2);
 556
 557         reg = readl(&mxc_ccm->chsccdr);
 558         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 559                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 560         writel(reg, &mxc_ccm->chsccdr);
 561
 562         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 563              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 564              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 565              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 566              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 567              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 568              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 569              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 570              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 571         writel(reg, &iomux->gpr[2]);
 572
 573         reg = readl(&iomux->gpr[3]);
 574         reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
 575                         |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
 576             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 577                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 578         writel(reg, &iomux->gpr[3]);
 579
 580         /* backlight unconditionally on for now */
 581         imx_iomux_v3_setup_multiple_pads(backlight_pads,
 582                                          ARRAY_SIZE(backlight_pads));
 583         /* use 0 for EDT 7", use 1 for LG fullHD panel */
 584         gpio_request(RGB_BACKLIGHTPWM_GP, "BKL1_PWM");
 585         gpio_request(RGB_BACKLIGHTPWM_OE, "BKL1_PWM_EN");
 586         gpio_request(RGB_BACKLIGHT_GP, "BKL1_ON");
 587         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
 588         gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
 589         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 590 }
 591
 592 /*
 593  * Backlight off before OS handover
 594  */
 595 void board_preboot_os(void)
 596 {
 597         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 1);
 598         gpio_direction_output(RGB_BACKLIGHT_GP, 0);
 599 }
 600 #endif /* defined(CONFIG_VIDEO_IPUV3) */
 601
 602 int board_early_init_f(void)
 603 {
 604         imx_iomux_v3_setup_multiple_pads(pwr_intb_pads,
 605                                          ARRAY_SIZE(pwr_intb_pads));
 606 #ifndef CONFIG_TDX_APALIS_IMX6_V1_0
 607         setup_iomux_dte_uart();
 608 #else
 609         setup_iomux_dce_uart();
 610 #endif
 611         return 0;
 612 }
 613
 614 /*
 615  * Do not overwrite the console
 616  * Use always serial for U-Boot console
 617  */
 618 int overwrite_console(void)
 619 {
 620         return 1;
 621 }
 622
 623 int board_init(void)
 624 {
 625         /* address of boot parameters */
 626         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 627
 628 #if defined(CONFIG_VIDEO_IPUV3)
 629         setup_display();
 630 #endif
 631
 632 #ifdef CONFIG_TDX_CMD_IMX_MFGR
 633         (void) pmic_init();
 634 #endif
 635
 636 #ifdef CONFIG_SATA
 637         setup_sata();
 638 #endif
 639
 640         setup_iomux_gpio();
 641
 642         return 0;
 643 }
 644
 645 #ifdef CONFIG_BOARD_LATE_INIT
 646 int board_late_init(void)
 647 {
 648 #if defined(CONFIG_REVISION_TAG) && \
 649     defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
 650         char env_str[256];
 651         u32 rev;
 652
 653         rev = get_board_rev();
 654         snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev);
 655         env_set("board_rev", env_str);
 656
 657 #ifndef CONFIG_TDX_APALIS_IMX6_V1_0
 658         if ((rev & 0xfff0) == 0x0100) {
 659                 char *fdt_env;
 660
 661                 /* reconfigure the UART to DCE mode dynamically if on V1.0 HW */
 662                 setup_iomux_dce_uart();
 663
 664                 /* if using the default device tree, use version for V1.0 HW */
 665                 fdt_env = env_get("fdt_file");
 666                 if ((fdt_env != NULL) && (strcmp(FDT_FILE, fdt_env) == 0)) {
 667                         env_set("fdt_file", FDT_FILE_V1_0);
 668                         printf("patching fdt_file to " FDT_FILE_V1_0 "\n");
 669 #ifndef CONFIG_ENV_IS_NOWHERE
 670                         env_save();
 671 #endif
 672                 }
 673         }
 674 #endif /* CONFIG_TDX_APALIS_IMX6_V1_0 */
 675 #endif /* CONFIG_REVISION_TAG */
 676
 677 #ifdef CONFIG_CMD_USB_SDP
 678         if (is_boot_from_usb()) {
 679                 printf("Serial Downloader recovery mode, using sdp command\n");
 680                 env_set("bootdelay", "0");
 681                 env_set("bootcmd", "sdp 0");
 682         }
 683 #endif /* CONFIG_CMD_USB_SDP */
 684
 685         return 0;
 686 }
 687 #endif /* CONFIG_BOARD_LATE_INIT */
 688
 689 int checkboard(void)
 690 {
 691         char it[] = " IT";
 692         int minc, maxc;
 693
 694         switch (get_cpu_temp_grade(&minc, &maxc)) {
 695         case TEMP_AUTOMOTIVE:
 696         case TEMP_INDUSTRIAL:
 697                 break;
 698         case TEMP_EXTCOMMERCIAL:
 699         default:
 700                 it[0] = 0;
 701         };
 702         printf("Model: Toradex Apalis iMX6 %s %s%s\n",
 703                is_cpu_type(MXC_CPU_MX6D) ? "Dual" : "Quad",
 704                (gd->ram_size == 0x80000000) ? "2GB" :
 705                (gd->ram_size == 0x40000000) ? "1GB" : "512MB", it);
 706         return 0;
 707 }
 708
 709 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 710 int ft_board_setup(void *blob, bd_t *bd)
 711 {
 712         return ft_common_board_setup(blob, bd);
 713 }
 714 #endif
 715
 716 #ifdef CONFIG_CMD_BMODE
 717 static const struct boot_mode board_boot_modes[] = {
 718         /* 4-bit bus width */
 719         {"mmc", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
 720         {"sd",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 721         {NULL,  0},
 722 };
 723 #endif
 724
 725 int misc_init_r(void)
 726 {
 727 #ifdef CONFIG_CMD_BMODE
 728         add_board_boot_modes(board_boot_modes);
 729 #endif
 730         return 0;
 731 }
 732
 733 #ifdef CONFIG_LDO_BYPASS_CHECK
 734 /* TODO, use external pmic, for now always ldo_enable */
 735 void ldo_mode_set(int ldo_bypass)
 736 {
 737         return;
 738 }
 739 #endif
 740
 741 #ifdef CONFIG_SPL_BUILD
 742 #include <spl.h>
 743 #include <linux/libfdt.h>
 744 #include "asm/arch/mx6q-ddr.h"
 745 #include "asm/arch/iomux.h"
 746 #include "asm/arch/crm_regs.h"
 747
 748 static int mx6_com_dcd_table[] = {
 749 /* ddr-setup.cfg */
 750 MX6_IOM_DRAM_SDQS0, 0x00000030,
 751 MX6_IOM_DRAM_SDQS1, 0x00000030,
 752 MX6_IOM_DRAM_SDQS2, 0x00000030,
 753 MX6_IOM_DRAM_SDQS3, 0x00000030,
 754 MX6_IOM_DRAM_SDQS4, 0x00000030,
 755 MX6_IOM_DRAM_SDQS5, 0x00000030,
 756 MX6_IOM_DRAM_SDQS6, 0x00000030,
 757 MX6_IOM_DRAM_SDQS7, 0x00000030,
 758
 759 MX6_IOM_GRP_B0DS, 0x00000030,
 760 MX6_IOM_GRP_B1DS, 0x00000030,
 761 MX6_IOM_GRP_B2DS, 0x00000030,
 762 MX6_IOM_GRP_B3DS, 0x00000030,
 763 MX6_IOM_GRP_B4DS, 0x00000030,
 764 MX6_IOM_GRP_B5DS, 0x00000030,
 765 MX6_IOM_GRP_B6DS, 0x00000030,
 766 MX6_IOM_GRP_B7DS, 0x00000030,
 767 MX6_IOM_GRP_ADDDS, 0x00000030,
 768 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 769 MX6_IOM_GRP_CTLDS, 0x00000030,
 770
 771 MX6_IOM_DRAM_DQM0, 0x00020030,
 772 MX6_IOM_DRAM_DQM1, 0x00020030,
 773 MX6_IOM_DRAM_DQM2, 0x00020030,
 774 MX6_IOM_DRAM_DQM3, 0x00020030,
 775 MX6_IOM_DRAM_DQM4, 0x00020030,
 776 MX6_IOM_DRAM_DQM5, 0x00020030,
 777 MX6_IOM_DRAM_DQM6, 0x00020030,
 778 MX6_IOM_DRAM_DQM7, 0x00020030,
 779
 780 MX6_IOM_DRAM_CAS, 0x00020030,
 781 MX6_IOM_DRAM_RAS, 0x00020030,
 782 MX6_IOM_DRAM_SDCLK_0, 0x00020030,
 783 MX6_IOM_DRAM_SDCLK_1, 0x00020030,
 784
 785 MX6_IOM_DRAM_RESET, 0x00020030,
 786 MX6_IOM_DRAM_SDCKE0, 0x00003000,
 787 MX6_IOM_DRAM_SDCKE1, 0x00003000,
 788
 789 MX6_IOM_DRAM_SDODT0, 0x00003030,
 790 MX6_IOM_DRAM_SDODT1, 0x00003030,
 791
 792 /* (differential input) */
 793 MX6_IOM_DDRMODE_CTL, 0x00020000,
 794 /* (differential input) */
 795 MX6_IOM_GRP_DDRMODE, 0x00020000,
 796 /* disable ddr pullups */
 797 MX6_IOM_GRP_DDRPKE, 0x00000000,
 798 MX6_IOM_DRAM_SDBA2, 0x00000000,
 799 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 800 MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
 801
 802 /* Read data DQ Byte0-3 delay */
 803 MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
 804 MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
 805 MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
 806 MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
 807 MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
 808 MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
 809 MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
 810 MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
 811
 812 /*
 813  * MDMISC       mirroring       interleaved (row/bank/col)
 814  */
 815 MX6_MMDC_P0_MDMISC, 0x00081740,
 816
 817 /*
 818  * MDSCR        con_req
 819  */
 820 MX6_MMDC_P0_MDSCR, 0x00008000,
 821
 822 /* 1066mhz_4x128mx16.cfg */
 823
 824 MX6_MMDC_P0_MDPDC, 0x00020036,
 825 MX6_MMDC_P0_MDCFG0, 0x555A7954,
 826 MX6_MMDC_P0_MDCFG1, 0xDB328F64,
 827 MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
 828 MX6_MMDC_P0_MDRWD, 0x000026D2,
 829 MX6_MMDC_P0_MDOR, 0x005A1023,
 830 MX6_MMDC_P0_MDOTC, 0x09555050,
 831 MX6_MMDC_P0_MDPDC, 0x00025576,
 832 MX6_MMDC_P0_MDASP, 0x00000027,
 833 MX6_MMDC_P0_MDCTL, 0x831A0000,
 834 MX6_MMDC_P0_MDSCR, 0x04088032,
 835 MX6_MMDC_P0_MDSCR, 0x00008033,
 836 MX6_MMDC_P0_MDSCR, 0x00428031,
 837 MX6_MMDC_P0_MDSCR, 0x19308030,
 838 MX6_MMDC_P0_MDSCR, 0x04008040,
 839 MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
 840 MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
 841 MX6_MMDC_P0_MDREF, 0x00005800,
 842 MX6_MMDC_P0_MPODTCTRL, 0x00000000,
 843 MX6_MMDC_P1_MPODTCTRL, 0x00000000,
 844
 845 MX6_MMDC_P0_MPDGCTRL0, 0x432A0338,
 846 MX6_MMDC_P0_MPDGCTRL1, 0x03260324,
 847 MX6_MMDC_P1_MPDGCTRL0, 0x43340344,
 848 MX6_MMDC_P1_MPDGCTRL1, 0x031E027C,
 849
 850 MX6_MMDC_P0_MPRDDLCTL, 0x33272D2E,
 851 MX6_MMDC_P1_MPRDDLCTL, 0x2F312B37,
 852
 853 MX6_MMDC_P0_MPWRDLCTL, 0x3A35433C,
 854 MX6_MMDC_P1_MPWRDLCTL, 0x4336453F,
 855
 856 MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E,
 857 MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B,
 858 MX6_MMDC_P1_MPWLDECTRL0, 0x00060015,
 859 MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E,
 860
 861 MX6_MMDC_P0_MPMUR0, 0x00000800,
 862 MX6_MMDC_P1_MPMUR0, 0x00000800,
 863 MX6_MMDC_P0_MDSCR, 0x00000000,
 864 MX6_MMDC_P0_MAPSR, 0x00011006,
 865 };
 866
 867 static int mx6_it_dcd_table[] = {
 868 /* ddr-setup.cfg */
 869 MX6_IOM_DRAM_SDQS0, 0x00000030,
 870 MX6_IOM_DRAM_SDQS1, 0x00000030,
 871 MX6_IOM_DRAM_SDQS2, 0x00000030,
 872 MX6_IOM_DRAM_SDQS3, 0x00000030,
 873 MX6_IOM_DRAM_SDQS4, 0x00000030,
 874 MX6_IOM_DRAM_SDQS5, 0x00000030,
 875 MX6_IOM_DRAM_SDQS6, 0x00000030,
 876 MX6_IOM_DRAM_SDQS7, 0x00000030,
 877
 878 MX6_IOM_GRP_B0DS, 0x00000030,
 879 MX6_IOM_GRP_B1DS, 0x00000030,
 880 MX6_IOM_GRP_B2DS, 0x00000030,
 881 MX6_IOM_GRP_B3DS, 0x00000030,
 882 MX6_IOM_GRP_B4DS, 0x00000030,
 883 MX6_IOM_GRP_B5DS, 0x00000030,
 884 MX6_IOM_GRP_B6DS, 0x00000030,
 885 MX6_IOM_GRP_B7DS, 0x00000030,
 886 MX6_IOM_GRP_ADDDS, 0x00000030,
 887 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 888 MX6_IOM_GRP_CTLDS, 0x00000030,
 889
 890 MX6_IOM_DRAM_DQM0, 0x00020030,
 891 MX6_IOM_DRAM_DQM1, 0x00020030,
 892 MX6_IOM_DRAM_DQM2, 0x00020030,
 893 MX6_IOM_DRAM_DQM3, 0x00020030,
 894 MX6_IOM_DRAM_DQM4, 0x00020030,
 895 MX6_IOM_DRAM_DQM5, 0x00020030,
 896 MX6_IOM_DRAM_DQM6, 0x00020030,
 897 MX6_IOM_DRAM_DQM7, 0x00020030,
 898
 899 MX6_IOM_DRAM_CAS, 0x00020030,
 900 MX6_IOM_DRAM_RAS, 0x00020030,
 901 MX6_IOM_DRAM_SDCLK_0, 0x00020030,
 902 MX6_IOM_DRAM_SDCLK_1, 0x00020030,
 903
 904 MX6_IOM_DRAM_RESET, 0x00020030,
 905 MX6_IOM_DRAM_SDCKE0, 0x00003000,
 906 MX6_IOM_DRAM_SDCKE1, 0x00003000,
 907
 908 MX6_IOM_DRAM_SDODT0, 0x00003030,
 909 MX6_IOM_DRAM_SDODT1, 0x00003030,
 910
 911 /* (differential input) */
 912 MX6_IOM_DDRMODE_CTL, 0x00020000,
 913 /* (differential input) */
 914 MX6_IOM_GRP_DDRMODE, 0x00020000,
 915 /* disable ddr pullups */
 916 MX6_IOM_GRP_DDRPKE, 0x00000000,
 917 MX6_IOM_DRAM_SDBA2, 0x00000000,
 918 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 919 MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
 920
 921 /* Read data DQ Byte0-3 delay */
 922 MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
 923 MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
 924 MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
 925 MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
 926 MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
 927 MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
 928 MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
 929 MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
 930
 931 /*
 932  * MDMISC       mirroring       interleaved (row/bank/col)
 933  */
 934 MX6_MMDC_P0_MDMISC, 0x00081740,
 935
 936 /*
 937  * MDSCR        con_req
 938  */
 939 MX6_MMDC_P0_MDSCR, 0x00008000,
 940
 941 /* 1066mhz_4x256mx16.cfg */
 942
 943 MX6_MMDC_P0_MDPDC, 0x00020036,
 944 MX6_MMDC_P0_MDCFG0, 0x898E78f5,
 945 MX6_MMDC_P0_MDCFG1, 0xff328f64,
 946 MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
 947 MX6_MMDC_P0_MDRWD, 0x000026D2,
 948 MX6_MMDC_P0_MDOR, 0x008E1023,
 949 MX6_MMDC_P0_MDOTC, 0x09444040,
 950 MX6_MMDC_P0_MDPDC, 0x00025576,
 951 MX6_MMDC_P0_MDASP, 0x00000047,
 952 MX6_MMDC_P0_MDCTL, 0x841A0000,
 953 MX6_MMDC_P0_MDSCR, 0x02888032,
 954 MX6_MMDC_P0_MDSCR, 0x00008033,
 955 MX6_MMDC_P0_MDSCR, 0x00048031,
 956 MX6_MMDC_P0_MDSCR, 0x19408030,
 957 MX6_MMDC_P0_MDSCR, 0x04008040,
 958 MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
 959 MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
 960 MX6_MMDC_P0_MDREF, 0x00007800,
 961 MX6_MMDC_P0_MPODTCTRL, 0x00022227,
 962 MX6_MMDC_P1_MPODTCTRL, 0x00022227,
 963
 964 MX6_MMDC_P0_MPDGCTRL0, 0x03300338,
 965 MX6_MMDC_P0_MPDGCTRL1, 0x03240324,
 966 MX6_MMDC_P1_MPDGCTRL0, 0x03440350,
 967 MX6_MMDC_P1_MPDGCTRL1, 0x032C0308,
 968
 969 MX6_MMDC_P0_MPRDDLCTL, 0x40363C3E,
 970 MX6_MMDC_P1_MPRDDLCTL, 0x3C3E3C46,
 971
 972 MX6_MMDC_P0_MPWRDLCTL, 0x403E463E,
 973 MX6_MMDC_P1_MPWRDLCTL, 0x4A384C46,
 974
 975 MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E,
 976 MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B,
 977 MX6_MMDC_P1_MPWLDECTRL0, 0x00060015,
 978 MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E,
 979
 980 MX6_MMDC_P0_MPMUR0, 0x00000800,
 981 MX6_MMDC_P1_MPMUR0, 0x00000800,
 982 MX6_MMDC_P0_MDSCR, 0x00000000,
 983 MX6_MMDC_P0_MAPSR, 0x00011006,
 984 };
 985
 986 static void ccgr_init(void)
 987 {
 988         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 989
 990         writel(0x00C03F3F, &ccm->CCGR0);
 991         writel(0x0030FC03, &ccm->CCGR1);
 992         writel(0x0FFFFFF3, &ccm->CCGR2);
 993         writel(0x3FF0300F, &ccm->CCGR3);
 994         writel(0x00FFF300, &ccm->CCGR4);
 995         writel(0x0F0000F3, &ccm->CCGR5);
 996         writel(0x000003FF, &ccm->CCGR6);
 997
 998 /*
 999  * Setup CCM_CCOSR register as follows:
1000  *
1001  * cko1_en  = 1    --> CKO1 enabled
1002  * cko1_div = 111  --> divide by 8
1003  * cko1_sel = 1011 --> ahb_clk_root
1004  *
1005  * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
1006  */
1007         writel(0x000000FB, &ccm->ccosr);
1008 }
1009
1010 static void ddr_init(int *table, int size)
1011 {
1012         int i;
1013
1014         for (i = 0; i < size / 2 ; i++)
1015                 writel(table[2 * i + 1], table[2 * i]);
1016 }
1017
1018 static void spl_dram_init(void)
1019 {
1020         int minc, maxc;
1021
1022         switch (get_cpu_temp_grade(&minc, &maxc)) {
1023         case TEMP_COMMERCIAL:
1024         case TEMP_EXTCOMMERCIAL:
1025                 puts("Commercial temperature grade DDR3 timings.\n");
1026                 ddr_init(mx6_com_dcd_table, ARRAY_SIZE(mx6_com_dcd_table));
1027                 break;
1028         case TEMP_INDUSTRIAL:
1029         case TEMP_AUTOMOTIVE:
1030         default:
1031                 puts("Industrial temperature grade DDR3 timings.\n");
1032                 ddr_init(mx6_it_dcd_table, ARRAY_SIZE(mx6_it_dcd_table));
1033                 break;
1034         };
1035         udelay(100);
1036 }
1037
1038 void board_init_f(ulong dummy)
1039 {
1040         /* setup AIPS and disable watchdog */
1041         arch_cpu_init();
1042
1043         ccgr_init();
1044         gpr_init();
1045
1046         /* iomux */
1047         board_early_init_f();
1048
1049         /* setup GP timer */
1050         timer_init();
1051
1052         /* UART clocks enabled and gd valid - init serial console */
1053         preloader_console_init();
1054
1055 #ifndef CONFIG_TDX_APALIS_IMX6_V1_0
1056         /* Make sure we use dte mode */
1057         setup_dtemode_uart();
1058 #endif
1059
1060         /* DDR initialization */
1061         spl_dram_init();
1062
1063         /* Clear the BSS. */
1064         memset(__bss_start, 0, __bss_end - __bss_start);
1065
1066         /* load/boot image from boot device */
1067         board_init_r(NULL, 0);
1068 }
1069
1070 #ifdef CONFIG_SPL_LOAD_FIT
1071 int board_fit_config_name_match(const char *name)
1072 {
1073         if (!strcmp(name, "imx6-apalis"))
1074                 return 0;
1075
1076         return -1;
1077 }
1078 #endif
1079
1080 void reset_cpu(ulong addr)
1081 {
1082 }
1083
1084 #endif /* CONFIG_SPL_BUILD */
1085
1086 static struct mxc_serial_platdata mxc_serial_plat = {
1087         .reg = (struct mxc_uart *)UART1_BASE,
1088         .use_dte = true,
1089 };
1090
1091 U_BOOT_DEVICE(mxc_serial) = {
1092         .name = "serial_mxc",
1093         .platdata = &mxc_serial_plat,
1094 };