board/toradex/apalis_imx6/apalis_imx6.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
   4  * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
   5  * Copyright (C) 2014-2019, Toradex AG
   6  * copied from nitrogen6x
   7  */
   8
   9 #include <common.h>
  10 #include <dm.h>
  11 #include <init.h>
  12
  13 #include <ahci.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/crm_regs.h>
  16 #include <asm/arch/imx-regs.h>
  17 #include <asm/arch/mx6-ddr.h>
  18 #include <asm/arch/mx6-pins.h>
  19 #include <asm/arch/mxc_hdmi.h>
  20 #include <asm/arch/sys_proto.h>
  21 #include <asm/bootm.h>
  22 #include <asm/gpio.h>
  23 #include <asm/mach-imx/boot_mode.h>
  24 #include <asm/mach-imx/iomux-v3.h>
  25 #include <asm/mach-imx/sata.h>
  26 #include <asm/mach-imx/video.h>
  27 #include <dm/device-internal.h>
  28 #include <dm/platform_data/serial_mxc.h>
  29 #include <dwc_ahsata.h>
  30 #include <env.h>
  31 #include <fsl_esdhc_imx.h>
  32 #include <imx_thermal.h>
  33 #include <micrel.h>
  34 #include <miiphy.h>
  35 #include <netdev.h>
  36
  37 #include "../common/tdx-cfg-block.h"
  38 #ifdef CONFIG_TDX_CMD_IMX_MFGR
  39 #include "pf0100.h"
  40 #endif
  41
  42 DECLARE_GLOBAL_DATA_PTR;
  43
  44 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  45         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  46         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  47
  48 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  49         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm |                 \
  50         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  51
  52 #define USDHC_EMMC_PAD_CTRL (PAD_CTL_PUS_47K_UP |               \
  53         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  54         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  55
  56 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  57         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  58
  59 #define WEAK_PULLUP     (PAD_CTL_PUS_100K_UP |                  \
  60         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  61         PAD_CTL_SRE_SLOW)
  62
  63 #define WEAK_PULLDOWN   (PAD_CTL_PUS_100K_DOWN |                \
  64         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  65         PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
  66
  67 #define TRISTATE        (PAD_CTL_HYS | PAD_CTL_SPEED_MED)
  68
  69 #define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST)
  70
  71 #define APALIS_IMX6_SATA_INIT_RETRIES   10
  72
  73 int dram_init(void)
  74 {
  75         /* use the DDR controllers configured size */
  76         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  77                                     (ulong)imx_ddr_size());
  78
  79         return 0;
  80 }
  81
  82 /* Apalis UART1 */
  83 iomux_v3_cfg_t const uart1_pads_dce[] = {
  84         MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  85         MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  86 };
  87 iomux_v3_cfg_t const uart1_pads_dte[] = {
  88         MX6_PAD_CSI0_DAT10__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  89         MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  90 };
  91
  92 #if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
  93 /* Apalis MMC1 */
  94 iomux_v3_cfg_t const usdhc1_pads[] = {
  95         MX6_PAD_SD1_CLK__SD1_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  96         MX6_PAD_SD1_CMD__SD1_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  97         MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  98         MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  99         MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 100         MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 101         MX6_PAD_NANDF_D0__SD1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 102         MX6_PAD_NANDF_D1__SD1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 103         MX6_PAD_NANDF_D2__SD1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 104         MX6_PAD_NANDF_D3__SD1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 105         MX6_PAD_DI0_PIN4__GPIO4_IO20   | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 106 #       define GPIO_MMC_CD IMX_GPIO_NR(4, 20)
 107 };
 108
 109 /* Apalis SD1 */
 110 iomux_v3_cfg_t const usdhc2_pads[] = {
 111         MX6_PAD_SD2_CLK__SD2_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 112         MX6_PAD_SD2_CMD__SD2_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 113         MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 114         MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 115         MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 116         MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 117         MX6_PAD_NANDF_CS1__GPIO6_IO14  | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 118 #       define GPIO_SD_CD IMX_GPIO_NR(6, 14)
 119 };
 120
 121 /* eMMC */
 122 iomux_v3_cfg_t const usdhc3_pads[] = {
 123         MX6_PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 124         MX6_PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 125         MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 126         MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 127         MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 128         MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 129         MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 130         MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 131         MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 132         MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 133         MX6_PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) | MUX_MODE_SION,
 134 };
 135 #endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
 136
 137 int mx6_rgmii_rework(struct phy_device *phydev)
 138 {
 139         /* control data pad skew - devaddr = 0x02, register = 0x04 */
 140         ksz9031_phy_extended_write(phydev, 0x02,
 141                                    MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
 142                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
 143         /* rx data pad skew - devaddr = 0x02, register = 0x05 */
 144         ksz9031_phy_extended_write(phydev, 0x02,
 145                                    MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
 146                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
 147         /* tx data pad skew - devaddr = 0x02, register = 0x05 */
 148         ksz9031_phy_extended_write(phydev, 0x02,
 149                                    MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
 150                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
 151         /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
 152         ksz9031_phy_extended_write(phydev, 0x02,
 153                                    MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
 154                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
 155         return 0;
 156 }
 157
 158 iomux_v3_cfg_t const enet_pads[] = {
 159         MX6_PAD_ENET_MDIO__ENET_MDIO            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 160         MX6_PAD_ENET_MDC__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
 161         MX6_PAD_RGMII_TXC__RGMII_TXC            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 162         MX6_PAD_RGMII_TD0__RGMII_TD0            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 163         MX6_PAD_RGMII_TD1__RGMII_TD1            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 164         MX6_PAD_RGMII_TD2__RGMII_TD2            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 165         MX6_PAD_RGMII_TD3__RGMII_TD3            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 166         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 167         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 168         MX6_PAD_RGMII_RXC__RGMII_RXC            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 169         MX6_PAD_RGMII_RD0__RGMII_RD0            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 170         MX6_PAD_RGMII_RD1__RGMII_RD1            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 171         MX6_PAD_RGMII_RD2__RGMII_RD2            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 172         MX6_PAD_RGMII_RD3__RGMII_RD3            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 173         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 174         /* KSZ9031 PHY Reset */
 175         MX6_PAD_ENET_CRS_DV__GPIO1_IO25         | MUX_PAD_CTRL(NO_PAD_CTRL) |
 176                                                   MUX_MODE_SION,
 177 #       define GPIO_ENET_PHY_RESET IMX_GPIO_NR(1, 25)
 178 };
 179
 180 /* mux the Apalis GPIO pins, so they can be used from the U-Boot cmdline */
 181 iomux_v3_cfg_t const gpio_pads[] = {
 182         /* Apalis GPIO1 - GPIO8 */
 183         MX6_PAD_NANDF_D4__GPIO2_IO04    | MUX_PAD_CTRL(WEAK_PULLUP) |
 184                                           MUX_MODE_SION,
 185         MX6_PAD_NANDF_D5__GPIO2_IO05    | MUX_PAD_CTRL(WEAK_PULLUP) |
 186                                           MUX_MODE_SION,
 187         MX6_PAD_NANDF_D6__GPIO2_IO06    | MUX_PAD_CTRL(WEAK_PULLUP) |
 188                                           MUX_MODE_SION,
 189         MX6_PAD_NANDF_D7__GPIO2_IO07    | MUX_PAD_CTRL(WEAK_PULLUP) |
 190                                           MUX_MODE_SION,
 191         MX6_PAD_NANDF_RB0__GPIO6_IO10   | MUX_PAD_CTRL(WEAK_PULLUP) |
 192                                           MUX_MODE_SION,
 193         MX6_PAD_NANDF_WP_B__GPIO6_IO09  | MUX_PAD_CTRL(WEAK_PULLUP) |
 194                                           MUX_MODE_SION,
 195         MX6_PAD_GPIO_2__GPIO1_IO02      | MUX_PAD_CTRL(WEAK_PULLDOWN) |
 196                                           MUX_MODE_SION,
 197         MX6_PAD_GPIO_6__GPIO1_IO06      | MUX_PAD_CTRL(WEAK_PULLUP) |
 198                                           MUX_MODE_SION,
 199         MX6_PAD_GPIO_4__GPIO1_IO04      | MUX_PAD_CTRL(WEAK_PULLUP) |
 200                                           MUX_MODE_SION,
 201 };
 202
 203 static void setup_iomux_gpio(void)
 204 {
 205         imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
 206 }
 207
 208 iomux_v3_cfg_t const usb_pads[] = {
 209         /* USBH_EN */
 210         MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
 211 #       define GPIO_USBH_EN IMX_GPIO_NR(1, 0)
 212         /* USB_VBUS_DET */
 213         MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
 214 #       define GPIO_USB_VBUS_DET IMX_GPIO_NR(3, 28)
 215         /* USBO1_ID */
 216         MX6_PAD_ENET_RX_ER__USB_OTG_ID  | MUX_PAD_CTRL(WEAK_PULLUP),
 217         /* USBO1_EN */
 218         MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
 219 #       define GPIO_USBO_EN IMX_GPIO_NR(3, 22)
 220 };
 221
 222 /*
 223  * UARTs are used in DTE mode, switch the mode on all UARTs before
 224  * any pinmuxing connects a (DCE) output to a transceiver output.
 225  */
 226 #define UCR3            0x88    /* FIFO Control Register */
 227 #define UCR3_RI         BIT(8)  /* RIDELT DTE mode */
 228 #define UCR3_DCD        BIT(9)  /* DCDDELT DTE mode */
 229 #define UFCR            0x90    /* FIFO Control Register */
 230 #define UFCR_DCEDTE     BIT(6)  /* DCE=0 */
 231
 232 static void setup_dtemode_uart(void)
 233 {
 234         setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
 235         setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
 236         setbits_le32((u32 *)(UART4_BASE + UFCR), UFCR_DCEDTE);
 237         setbits_le32((u32 *)(UART5_BASE + UFCR), UFCR_DCEDTE);
 238
 239         clrbits_le32((u32 *)(UART1_BASE + UCR3), UCR3_DCD | UCR3_RI);
 240         clrbits_le32((u32 *)(UART2_BASE + UCR3), UCR3_DCD | UCR3_RI);
 241         clrbits_le32((u32 *)(UART4_BASE + UCR3), UCR3_DCD | UCR3_RI);
 242         clrbits_le32((u32 *)(UART5_BASE + UCR3), UCR3_DCD | UCR3_RI);
 243 }
 244 static void setup_dcemode_uart(void)
 245 {
 246         clrbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
 247         clrbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
 248         clrbits_le32((u32 *)(UART4_BASE + UFCR), UFCR_DCEDTE);
 249         clrbits_le32((u32 *)(UART5_BASE + UFCR), UFCR_DCEDTE);
 250 }
 251
 252 static void setup_iomux_dte_uart(void)
 253 {
 254         setup_dtemode_uart();
 255         imx_iomux_v3_setup_multiple_pads(uart1_pads_dte,
 256                                          ARRAY_SIZE(uart1_pads_dte));
 257 }
 258 static void setup_iomux_dce_uart(void)
 259 {
 260         setup_dcemode_uart();
 261         imx_iomux_v3_setup_multiple_pads(uart1_pads_dce,
 262                                          ARRAY_SIZE(uart1_pads_dce));
 263 }
 264
 265 #ifdef CONFIG_USB_EHCI_MX6
 266 int board_ehci_hcd_init(int port)
 267 {
 268         imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
 269         return 0;
 270 }
 271 #endif
 272
 273 #if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
 274 /* use the following sequence: eMMC, MMC1, SD1 */
 275 struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
 276         {USDHC3_BASE_ADDR},
 277         {USDHC1_BASE_ADDR},
 278         {USDHC2_BASE_ADDR},
 279 };
 280
 281 int board_mmc_getcd(struct mmc *mmc)
 282 {
 283         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 284         int ret = true; /* default: assume inserted */
 285
 286         switch (cfg->esdhc_base) {
 287         case USDHC1_BASE_ADDR:
 288                 gpio_request(GPIO_MMC_CD, "MMC_CD");
 289                 gpio_direction_input(GPIO_MMC_CD);
 290                 ret = !gpio_get_value(GPIO_MMC_CD);
 291                 break;
 292         case USDHC2_BASE_ADDR:
 293                 gpio_request(GPIO_MMC_CD, "SD_CD");
 294                 gpio_direction_input(GPIO_SD_CD);
 295                 ret = !gpio_get_value(GPIO_SD_CD);
 296                 break;
 297         }
 298
 299         return ret;
 300 }
 301
 302 int board_mmc_init(bd_t *bis)
 303 {
 304         struct src *psrc = (struct src *)SRC_BASE_ADDR;
 305         unsigned reg = readl(&psrc->sbmr1) >> 11;
 306         /*
 307          * Upon reading BOOT_CFG register the following map is done:
 308          * Bit 11 and 12 of BOOT_CFG register can determine the current
 309          * mmc port
 310          * 0x1                  SD1
 311          * 0x2                  SD2
 312          * 0x3                  SD4
 313          */
 314
 315         switch (reg & 0x3) {
 316         case 0x0:
 317                 imx_iomux_v3_setup_multiple_pads(
 318                         usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
 319                 usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
 320                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 321                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 322                 break;
 323         case 0x1:
 324                 imx_iomux_v3_setup_multiple_pads(
 325                         usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 326                 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
 327                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 328                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 329                 break;
 330         case 0x2:
 331                 imx_iomux_v3_setup_multiple_pads(
 332                         usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 333                 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
 334                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 335                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 336                 break;
 337         default:
 338                 puts("MMC boot device not available");
 339         }
 340
 341         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 342 }
 343 #endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
 344
 345 int board_phy_config(struct phy_device *phydev)
 346 {
 347         mx6_rgmii_rework(phydev);
 348         if (phydev->drv->config)
 349                 phydev->drv->config(phydev);
 350
 351         return 0;
 352 }
 353
 354 static iomux_v3_cfg_t const pwr_intb_pads[] = {
 355         /*
 356          * the bootrom sets the iomux to vselect, potentially connecting
 357          * two outputs. Set this back to GPIO
 358          */
 359         MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)
 360 };
 361
 362 #if defined(CONFIG_VIDEO_IPUV3)
 363
 364 static iomux_v3_cfg_t const backlight_pads[] = {
 365         /* Backlight on RGB connector: J15 */
 366         MX6_PAD_EIM_DA13__GPIO3_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL) |
 367                                        MUX_MODE_SION,
 368 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 13)
 369         /* additional CPU pin on BKL_PWM, keep in tristate */
 370         MX6_PAD_EIM_DA14__GPIO3_IO14 | MUX_PAD_CTRL(TRISTATE),
 371         /* Backlight PWM, used as GPIO in U-Boot */
 372         MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL) |
 373                                        MUX_MODE_SION,
 374 #define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 10)
 375         /* buffer output enable 0: buffer enabled */
 376         MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(WEAK_PULLUP) | MUX_MODE_SION,
 377 #define RGB_BACKLIGHTPWM_OE IMX_GPIO_NR(5, 2)
 378         /* PSAVE# integrated VDAC */
 379         MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL) |
 380                                        MUX_MODE_SION,
 381 #define VGA_PSAVE_NOT_GP IMX_GPIO_NR(6, 31)
 382 };
 383
 384 static iomux_v3_cfg_t const rgb_pads[] = {
 385         MX6_PAD_EIM_A16__IPU1_DI1_DISP_CLK | MUX_PAD_CTRL(OUTPUT_RGB),
 386         MX6_PAD_EIM_DA10__IPU1_DI1_PIN15 | MUX_PAD_CTRL(OUTPUT_RGB),
 387         MX6_PAD_EIM_DA11__IPU1_DI1_PIN02 | MUX_PAD_CTRL(OUTPUT_RGB),
 388         MX6_PAD_EIM_DA12__IPU1_DI1_PIN03 | MUX_PAD_CTRL(OUTPUT_RGB),
 389         MX6_PAD_EIM_DA9__IPU1_DISP1_DATA00 | MUX_PAD_CTRL(OUTPUT_RGB),
 390         MX6_PAD_EIM_DA8__IPU1_DISP1_DATA01 | MUX_PAD_CTRL(OUTPUT_RGB),
 391         MX6_PAD_EIM_DA7__IPU1_DISP1_DATA02 | MUX_PAD_CTRL(OUTPUT_RGB),
 392         MX6_PAD_EIM_DA6__IPU1_DISP1_DATA03 | MUX_PAD_CTRL(OUTPUT_RGB),
 393         MX6_PAD_EIM_DA5__IPU1_DISP1_DATA04 | MUX_PAD_CTRL(OUTPUT_RGB),
 394         MX6_PAD_EIM_DA4__IPU1_DISP1_DATA05 | MUX_PAD_CTRL(OUTPUT_RGB),
 395         MX6_PAD_EIM_DA3__IPU1_DISP1_DATA06 | MUX_PAD_CTRL(OUTPUT_RGB),
 396         MX6_PAD_EIM_DA2__IPU1_DISP1_DATA07 | MUX_PAD_CTRL(OUTPUT_RGB),
 397         MX6_PAD_EIM_DA1__IPU1_DISP1_DATA08 | MUX_PAD_CTRL(OUTPUT_RGB),
 398         MX6_PAD_EIM_DA0__IPU1_DISP1_DATA09 | MUX_PAD_CTRL(OUTPUT_RGB),
 399         MX6_PAD_EIM_EB1__IPU1_DISP1_DATA10 | MUX_PAD_CTRL(OUTPUT_RGB),
 400         MX6_PAD_EIM_EB0__IPU1_DISP1_DATA11 | MUX_PAD_CTRL(OUTPUT_RGB),
 401         MX6_PAD_EIM_A17__IPU1_DISP1_DATA12 | MUX_PAD_CTRL(OUTPUT_RGB),
 402         MX6_PAD_EIM_A18__IPU1_DISP1_DATA13 | MUX_PAD_CTRL(OUTPUT_RGB),
 403         MX6_PAD_EIM_A19__IPU1_DISP1_DATA14 | MUX_PAD_CTRL(OUTPUT_RGB),
 404         MX6_PAD_EIM_A20__IPU1_DISP1_DATA15 | MUX_PAD_CTRL(OUTPUT_RGB),
 405         MX6_PAD_EIM_A21__IPU1_DISP1_DATA16 | MUX_PAD_CTRL(OUTPUT_RGB),
 406         MX6_PAD_EIM_A22__IPU1_DISP1_DATA17 | MUX_PAD_CTRL(OUTPUT_RGB),
 407         MX6_PAD_EIM_A23__IPU1_DISP1_DATA18 | MUX_PAD_CTRL(OUTPUT_RGB),
 408         MX6_PAD_EIM_A24__IPU1_DISP1_DATA19 | MUX_PAD_CTRL(OUTPUT_RGB),
 409         MX6_PAD_EIM_D26__IPU1_DISP1_DATA22 | MUX_PAD_CTRL(OUTPUT_RGB),
 410         MX6_PAD_EIM_D27__IPU1_DISP1_DATA23 | MUX_PAD_CTRL(OUTPUT_RGB),
 411         MX6_PAD_EIM_D30__IPU1_DISP1_DATA21 | MUX_PAD_CTRL(OUTPUT_RGB),
 412         MX6_PAD_EIM_D31__IPU1_DISP1_DATA20 | MUX_PAD_CTRL(OUTPUT_RGB),
 413 };
 414
 415 static void do_enable_hdmi(struct display_info_t const *dev)
 416 {
 417         imx_enable_hdmi_phy();
 418 }
 419
 420 static void enable_lvds(struct display_info_t const *dev)
 421 {
 422         struct iomuxc *iomux = (struct iomuxc *)
 423                                 IOMUXC_BASE_ADDR;
 424         u32 reg = readl(&iomux->gpr[2]);
 425         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
 426         writel(reg, &iomux->gpr[2]);
 427         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 428         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
 429         gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
 430 }
 431
 432 static void enable_rgb(struct display_info_t const *dev)
 433 {
 434         imx_iomux_v3_setup_multiple_pads(
 435                 rgb_pads,
 436                 ARRAY_SIZE(rgb_pads));
 437         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 438         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
 439         gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
 440 }
 441
 442 static int detect_default(struct display_info_t const *dev)
 443 {
 444         (void) dev;
 445         return 1;
 446 }
 447
 448 struct display_info_t const displays[] = {{
 449         .bus    = -1,
 450         .addr   = 0,
 451         .pixfmt = IPU_PIX_FMT_RGB24,
 452         .detect = detect_hdmi,
 453         .enable = do_enable_hdmi,
 454         .mode   = {
 455                 .name           = "HDMI",
 456                 .refresh        = 60,
 457                 .xres           = 1024,
 458                 .yres           = 768,
 459                 .pixclock       = 15385,
 460                 .left_margin    = 220,
 461                 .right_margin   = 40,
 462                 .upper_margin   = 21,
 463                 .lower_margin   = 7,
 464                 .hsync_len      = 60,
 465                 .vsync_len      = 10,
 466                 .sync           = FB_SYNC_EXT,
 467                 .vmode          = FB_VMODE_NONINTERLACED
 468 } }, {
 469         .bus    = -1,
 470         .addr   = 0,
 471         .di     = 1,
 472         .pixfmt = IPU_PIX_FMT_RGB24,
 473         .detect = detect_default,
 474         .enable = enable_rgb,
 475         .mode   = {
 476                 .name           = "vga-rgb",
 477                 .refresh        = 60,
 478                 .xres           = 640,
 479                 .yres           = 480,
 480                 .pixclock       = 33000,
 481                 .left_margin    = 48,
 482                 .right_margin   = 16,
 483                 .upper_margin   = 31,
 484                 .lower_margin   = 11,
 485                 .hsync_len      = 96,
 486                 .vsync_len      = 2,
 487                 .sync           = 0,
 488                 .vmode          = FB_VMODE_NONINTERLACED
 489 } }, {
 490         .bus    = -1,
 491         .addr   = 0,
 492         .di     = 1,
 493         .pixfmt = IPU_PIX_FMT_RGB24,
 494         .enable = enable_rgb,
 495         .mode   = {
 496                 .name           = "wvga-rgb",
 497                 .refresh        = 60,
 498                 .xres           = 800,
 499                 .yres           = 480,
 500                 .pixclock       = 25000,
 501                 .left_margin    = 40,
 502                 .right_margin   = 88,
 503                 .upper_margin   = 33,
 504                 .lower_margin   = 10,
 505                 .hsync_len      = 128,
 506                 .vsync_len      = 2,
 507                 .sync           = 0,
 508                 .vmode          = FB_VMODE_NONINTERLACED
 509 } }, {
 510         .bus    = -1,
 511         .addr   = 0,
 512         .pixfmt = IPU_PIX_FMT_LVDS666,
 513         .enable = enable_lvds,
 514         .mode   = {
 515                 .name           = "wsvga-lvds",
 516                 .refresh        = 60,
 517                 .xres           = 1024,
 518                 .yres           = 600,
 519                 .pixclock       = 15385,
 520                 .left_margin    = 220,
 521                 .right_margin   = 40,
 522                 .upper_margin   = 21,
 523                 .lower_margin   = 7,
 524                 .hsync_len      = 60,
 525                 .vsync_len      = 10,
 526                 .sync           = FB_SYNC_EXT,
 527                 .vmode          = FB_VMODE_NONINTERLACED
 528 } } };
 529 size_t display_count = ARRAY_SIZE(displays);
 530
 531 static void setup_display(void)
 532 {
 533         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 534         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 535         int reg;
 536
 537         enable_ipu_clock();
 538         imx_setup_hdmi();
 539         /* Turn on LDB0,IPU,IPU DI0 clocks */
 540         reg = __raw_readl(&mxc_ccm->CCGR3);
 541         reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
 542         writel(reg, &mxc_ccm->CCGR3);
 543
 544         /* set LDB0, LDB1 clk select to 011/011 */
 545         reg = readl(&mxc_ccm->cs2cdr);
 546         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 547                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 548         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 549               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 550         writel(reg, &mxc_ccm->cs2cdr);
 551
 552         reg = readl(&mxc_ccm->cscmr2);
 553         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 554         writel(reg, &mxc_ccm->cscmr2);
 555
 556         reg = readl(&mxc_ccm->chsccdr);
 557         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 558                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 559         writel(reg, &mxc_ccm->chsccdr);
 560
 561         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 562              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 563              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 564              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 565              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 566              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 567              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 568              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 569              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 570         writel(reg, &iomux->gpr[2]);
 571
 572         reg = readl(&iomux->gpr[3]);
 573         reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
 574                         |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
 575             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 576                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 577         writel(reg, &iomux->gpr[3]);
 578
 579         /* backlight unconditionally on for now */
 580         imx_iomux_v3_setup_multiple_pads(backlight_pads,
 581                                          ARRAY_SIZE(backlight_pads));
 582         /* use 0 for EDT 7", use 1 for LG fullHD panel */
 583         gpio_request(RGB_BACKLIGHTPWM_GP, "BKL1_PWM");
 584         gpio_request(RGB_BACKLIGHTPWM_OE, "BKL1_PWM_EN");
 585         gpio_request(RGB_BACKLIGHT_GP, "BKL1_ON");
 586         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
 587         gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
 588         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 589 }
 590
 591 /*
 592  * Backlight off before OS handover
 593  */
 594 void board_preboot_os(void)
 595 {
 596         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 1);
 597         gpio_direction_output(RGB_BACKLIGHT_GP, 0);
 598 }
 599 #endif /* defined(CONFIG_VIDEO_IPUV3) */
 600
 601 int board_early_init_f(void)
 602 {
 603         imx_iomux_v3_setup_multiple_pads(pwr_intb_pads,
 604                                          ARRAY_SIZE(pwr_intb_pads));
 605 #ifndef CONFIG_TDX_APALIS_IMX6_V1_0
 606         setup_iomux_dte_uart();
 607 #else
 608         setup_iomux_dce_uart();
 609 #endif
 610         return 0;
 611 }
 612
 613 /*
 614  * Do not overwrite the console
 615  * Use always serial for U-Boot console
 616  */
 617 int overwrite_console(void)
 618 {
 619         return 1;
 620 }
 621
 622 int board_init(void)
 623 {
 624         /* address of boot parameters */
 625         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 626
 627 #if defined(CONFIG_VIDEO_IPUV3)
 628         setup_display();
 629 #endif
 630
 631 #ifdef CONFIG_TDX_CMD_IMX_MFGR
 632         (void) pmic_init();
 633 #endif
 634
 635 #ifdef CONFIG_SATA
 636         setup_sata();
 637 #endif
 638
 639         setup_iomux_gpio();
 640
 641         return 0;
 642 }
 643
 644 #ifdef CONFIG_BOARD_LATE_INIT
 645 int board_late_init(void)
 646 {
 647 #if defined(CONFIG_REVISION_TAG) && \
 648     defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
 649         char env_str[256];
 650         u32 rev;
 651
 652         rev = get_board_rev();
 653         snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev);
 654         env_set("board_rev", env_str);
 655
 656 #ifndef CONFIG_TDX_APALIS_IMX6_V1_0
 657         if ((rev & 0xfff0) == 0x0100) {
 658                 char *fdt_env;
 659
 660                 /* reconfigure the UART to DCE mode dynamically if on V1.0 HW */
 661                 setup_iomux_dce_uart();
 662
 663                 /* if using the default device tree, use version for V1.0 HW */
 664                 fdt_env = env_get("fdt_file");
 665                 if ((fdt_env != NULL) && (strcmp(FDT_FILE, fdt_env) == 0)) {
 666                         env_set("fdt_file", FDT_FILE_V1_0);
 667                         printf("patching fdt_file to " FDT_FILE_V1_0 "\n");
 668 #ifndef CONFIG_ENV_IS_NOWHERE
 669                         env_save();
 670 #endif
 671                 }
 672         }
 673 #endif /* CONFIG_TDX_APALIS_IMX6_V1_0 */
 674 #endif /* CONFIG_REVISION_TAG */
 675
 676 #ifdef CONFIG_CMD_USB_SDP
 677         if (is_boot_from_usb()) {
 678                 printf("Serial Downloader recovery mode, using sdp command\n");
 679                 env_set("bootdelay", "0");
 680                 env_set("bootcmd", "sdp 0");
 681         }
 682 #endif /* CONFIG_CMD_USB_SDP */
 683
 684         return 0;
 685 }
 686 #endif /* CONFIG_BOARD_LATE_INIT */
 687
 688 int checkboard(void)
 689 {
 690         char it[] = " IT";
 691         int minc, maxc;
 692
 693         switch (get_cpu_temp_grade(&minc, &maxc)) {
 694         case TEMP_AUTOMOTIVE:
 695         case TEMP_INDUSTRIAL:
 696                 break;
 697         case TEMP_EXTCOMMERCIAL:
 698         default:
 699                 it[0] = 0;
 700         };
 701         printf("Model: Toradex Apalis iMX6 %s %s%s\n",
 702                is_cpu_type(MXC_CPU_MX6D) ? "Dual" : "Quad",
 703                (gd->ram_size == 0x80000000) ? "2GB" :
 704                (gd->ram_size == 0x40000000) ? "1GB" : "512MB", it);
 705         return 0;
 706 }
 707
 708 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 709 int ft_board_setup(void *blob, bd_t *bd)
 710 {
 711         return ft_common_board_setup(blob, bd);
 712 }
 713 #endif
 714
 715 #ifdef CONFIG_CMD_BMODE
 716 static const struct boot_mode board_boot_modes[] = {
 717         /* 4-bit bus width */
 718         {"mmc", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
 719         {"sd",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 720         {NULL,  0},
 721 };
 722 #endif
 723
 724 int misc_init_r(void)
 725 {
 726 #ifdef CONFIG_CMD_BMODE
 727         add_board_boot_modes(board_boot_modes);
 728 #endif
 729         return 0;
 730 }
 731
 732 #ifdef CONFIG_LDO_BYPASS_CHECK
 733 /* TODO, use external pmic, for now always ldo_enable */
 734 void ldo_mode_set(int ldo_bypass)
 735 {
 736         return;
 737 }
 738 #endif
 739
 740 #ifdef CONFIG_SPL_BUILD
 741 #include <spl.h>
 742 #include <linux/libfdt.h>
 743 #include "asm/arch/mx6q-ddr.h"
 744 #include "asm/arch/iomux.h"
 745 #include "asm/arch/crm_regs.h"
 746
 747 static int mx6_com_dcd_table[] = {
 748 /* ddr-setup.cfg */
 749 MX6_IOM_DRAM_SDQS0, 0x00000030,
 750 MX6_IOM_DRAM_SDQS1, 0x00000030,
 751 MX6_IOM_DRAM_SDQS2, 0x00000030,
 752 MX6_IOM_DRAM_SDQS3, 0x00000030,
 753 MX6_IOM_DRAM_SDQS4, 0x00000030,
 754 MX6_IOM_DRAM_SDQS5, 0x00000030,
 755 MX6_IOM_DRAM_SDQS6, 0x00000030,
 756 MX6_IOM_DRAM_SDQS7, 0x00000030,
 757
 758 MX6_IOM_GRP_B0DS, 0x00000030,
 759 MX6_IOM_GRP_B1DS, 0x00000030,
 760 MX6_IOM_GRP_B2DS, 0x00000030,
 761 MX6_IOM_GRP_B3DS, 0x00000030,
 762 MX6_IOM_GRP_B4DS, 0x00000030,
 763 MX6_IOM_GRP_B5DS, 0x00000030,
 764 MX6_IOM_GRP_B6DS, 0x00000030,
 765 MX6_IOM_GRP_B7DS, 0x00000030,
 766 MX6_IOM_GRP_ADDDS, 0x00000030,
 767 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 768 MX6_IOM_GRP_CTLDS, 0x00000030,
 769
 770 MX6_IOM_DRAM_DQM0, 0x00020030,
 771 MX6_IOM_DRAM_DQM1, 0x00020030,
 772 MX6_IOM_DRAM_DQM2, 0x00020030,
 773 MX6_IOM_DRAM_DQM3, 0x00020030,
 774 MX6_IOM_DRAM_DQM4, 0x00020030,
 775 MX6_IOM_DRAM_DQM5, 0x00020030,
 776 MX6_IOM_DRAM_DQM6, 0x00020030,
 777 MX6_IOM_DRAM_DQM7, 0x00020030,
 778
 779 MX6_IOM_DRAM_CAS, 0x00020030,
 780 MX6_IOM_DRAM_RAS, 0x00020030,
 781 MX6_IOM_DRAM_SDCLK_0, 0x00020030,
 782 MX6_IOM_DRAM_SDCLK_1, 0x00020030,
 783
 784 MX6_IOM_DRAM_RESET, 0x00020030,
 785 MX6_IOM_DRAM_SDCKE0, 0x00003000,
 786 MX6_IOM_DRAM_SDCKE1, 0x00003000,
 787
 788 MX6_IOM_DRAM_SDODT0, 0x00003030,
 789 MX6_IOM_DRAM_SDODT1, 0x00003030,
 790
 791 /* (differential input) */
 792 MX6_IOM_DDRMODE_CTL, 0x00020000,
 793 /* (differential input) */
 794 MX6_IOM_GRP_DDRMODE, 0x00020000,
 795 /* disable ddr pullups */
 796 MX6_IOM_GRP_DDRPKE, 0x00000000,
 797 MX6_IOM_DRAM_SDBA2, 0x00000000,
 798 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 799 MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
 800
 801 /* Read data DQ Byte0-3 delay */
 802 MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
 803 MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
 804 MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
 805 MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
 806 MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
 807 MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
 808 MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
 809 MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
 810
 811 /*
 812  * MDMISC       mirroring       interleaved (row/bank/col)
 813  */
 814 MX6_MMDC_P0_MDMISC, 0x00081740,
 815
 816 /*
 817  * MDSCR        con_req
 818  */
 819 MX6_MMDC_P0_MDSCR, 0x00008000,
 820
 821 /* 1066mhz_4x128mx16.cfg */
 822
 823 MX6_MMDC_P0_MDPDC, 0x00020036,
 824 MX6_MMDC_P0_MDCFG0, 0x555A7954,
 825 MX6_MMDC_P0_MDCFG1, 0xDB328F64,
 826 MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
 827 MX6_MMDC_P0_MDRWD, 0x000026D2,
 828 MX6_MMDC_P0_MDOR, 0x005A1023,
 829 MX6_MMDC_P0_MDOTC, 0x09555050,
 830 MX6_MMDC_P0_MDPDC, 0x00025576,
 831 MX6_MMDC_P0_MDASP, 0x00000027,
 832 MX6_MMDC_P0_MDCTL, 0x831A0000,
 833 MX6_MMDC_P0_MDSCR, 0x04088032,
 834 MX6_MMDC_P0_MDSCR, 0x00008033,
 835 MX6_MMDC_P0_MDSCR, 0x00428031,
 836 MX6_MMDC_P0_MDSCR, 0x19308030,
 837 MX6_MMDC_P0_MDSCR, 0x04008040,
 838 MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
 839 MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
 840 MX6_MMDC_P0_MDREF, 0x00005800,
 841 MX6_MMDC_P0_MPODTCTRL, 0x00000000,
 842 MX6_MMDC_P1_MPODTCTRL, 0x00000000,
 843
 844 MX6_MMDC_P0_MPDGCTRL0, 0x432A0338,
 845 MX6_MMDC_P0_MPDGCTRL1, 0x03260324,
 846 MX6_MMDC_P1_MPDGCTRL0, 0x43340344,
 847 MX6_MMDC_P1_MPDGCTRL1, 0x031E027C,
 848
 849 MX6_MMDC_P0_MPRDDLCTL, 0x33272D2E,
 850 MX6_MMDC_P1_MPRDDLCTL, 0x2F312B37,
 851
 852 MX6_MMDC_P0_MPWRDLCTL, 0x3A35433C,
 853 MX6_MMDC_P1_MPWRDLCTL, 0x4336453F,
 854
 855 MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E,
 856 MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B,
 857 MX6_MMDC_P1_MPWLDECTRL0, 0x00060015,
 858 MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E,
 859
 860 MX6_MMDC_P0_MPMUR0, 0x00000800,
 861 MX6_MMDC_P1_MPMUR0, 0x00000800,
 862 MX6_MMDC_P0_MDSCR, 0x00000000,
 863 MX6_MMDC_P0_MAPSR, 0x00011006,
 864 };
 865
 866 static int mx6_it_dcd_table[] = {
 867 /* ddr-setup.cfg */
 868 MX6_IOM_DRAM_SDQS0, 0x00000030,
 869 MX6_IOM_DRAM_SDQS1, 0x00000030,
 870 MX6_IOM_DRAM_SDQS2, 0x00000030,
 871 MX6_IOM_DRAM_SDQS3, 0x00000030,
 872 MX6_IOM_DRAM_SDQS4, 0x00000030,
 873 MX6_IOM_DRAM_SDQS5, 0x00000030,
 874 MX6_IOM_DRAM_SDQS6, 0x00000030,
 875 MX6_IOM_DRAM_SDQS7, 0x00000030,
 876
 877 MX6_IOM_GRP_B0DS, 0x00000030,
 878 MX6_IOM_GRP_B1DS, 0x00000030,
 879 MX6_IOM_GRP_B2DS, 0x00000030,
 880 MX6_IOM_GRP_B3DS, 0x00000030,
 881 MX6_IOM_GRP_B4DS, 0x00000030,
 882 MX6_IOM_GRP_B5DS, 0x00000030,
 883 MX6_IOM_GRP_B6DS, 0x00000030,
 884 MX6_IOM_GRP_B7DS, 0x00000030,
 885 MX6_IOM_GRP_ADDDS, 0x00000030,
 886 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 887 MX6_IOM_GRP_CTLDS, 0x00000030,
 888
 889 MX6_IOM_DRAM_DQM0, 0x00020030,
 890 MX6_IOM_DRAM_DQM1, 0x00020030,
 891 MX6_IOM_DRAM_DQM2, 0x00020030,
 892 MX6_IOM_DRAM_DQM3, 0x00020030,
 893 MX6_IOM_DRAM_DQM4, 0x00020030,
 894 MX6_IOM_DRAM_DQM5, 0x00020030,
 895 MX6_IOM_DRAM_DQM6, 0x00020030,
 896 MX6_IOM_DRAM_DQM7, 0x00020030,
 897
 898 MX6_IOM_DRAM_CAS, 0x00020030,
 899 MX6_IOM_DRAM_RAS, 0x00020030,
 900 MX6_IOM_DRAM_SDCLK_0, 0x00020030,
 901 MX6_IOM_DRAM_SDCLK_1, 0x00020030,
 902
 903 MX6_IOM_DRAM_RESET, 0x00020030,
 904 MX6_IOM_DRAM_SDCKE0, 0x00003000,
 905 MX6_IOM_DRAM_SDCKE1, 0x00003000,
 906
 907 MX6_IOM_DRAM_SDODT0, 0x00003030,
 908 MX6_IOM_DRAM_SDODT1, 0x00003030,
 909
 910 /* (differential input) */
 911 MX6_IOM_DDRMODE_CTL, 0x00020000,
 912 /* (differential input) */
 913 MX6_IOM_GRP_DDRMODE, 0x00020000,
 914 /* disable ddr pullups */
 915 MX6_IOM_GRP_DDRPKE, 0x00000000,
 916 MX6_IOM_DRAM_SDBA2, 0x00000000,
 917 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 918 MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
 919
 920 /* Read data DQ Byte0-3 delay */
 921 MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
 922 MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
 923 MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
 924 MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
 925 MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
 926 MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
 927 MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
 928 MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
 929
 930 /*
 931  * MDMISC       mirroring       interleaved (row/bank/col)
 932  */
 933 MX6_MMDC_P0_MDMISC, 0x00081740,
 934
 935 /*
 936  * MDSCR        con_req
 937  */
 938 MX6_MMDC_P0_MDSCR, 0x00008000,
 939
 940 /* 1066mhz_4x256mx16.cfg */
 941
 942 MX6_MMDC_P0_MDPDC, 0x00020036,
 943 MX6_MMDC_P0_MDCFG0, 0x898E78f5,
 944 MX6_MMDC_P0_MDCFG1, 0xff328f64,
 945 MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
 946 MX6_MMDC_P0_MDRWD, 0x000026D2,
 947 MX6_MMDC_P0_MDOR, 0x008E1023,
 948 MX6_MMDC_P0_MDOTC, 0x09444040,
 949 MX6_MMDC_P0_MDPDC, 0x00025576,
 950 MX6_MMDC_P0_MDASP, 0x00000047,
 951 MX6_MMDC_P0_MDCTL, 0x841A0000,
 952 MX6_MMDC_P0_MDSCR, 0x02888032,
 953 MX6_MMDC_P0_MDSCR, 0x00008033,
 954 MX6_MMDC_P0_MDSCR, 0x00048031,
 955 MX6_MMDC_P0_MDSCR, 0x19408030,
 956 MX6_MMDC_P0_MDSCR, 0x04008040,
 957 MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
 958 MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
 959 MX6_MMDC_P0_MDREF, 0x00007800,
 960 MX6_MMDC_P0_MPODTCTRL, 0x00022227,
 961 MX6_MMDC_P1_MPODTCTRL, 0x00022227,
 962
 963 MX6_MMDC_P0_MPDGCTRL0, 0x03300338,
 964 MX6_MMDC_P0_MPDGCTRL1, 0x03240324,
 965 MX6_MMDC_P1_MPDGCTRL0, 0x03440350,
 966 MX6_MMDC_P1_MPDGCTRL1, 0x032C0308,
 967
 968 MX6_MMDC_P0_MPRDDLCTL, 0x40363C3E,
 969 MX6_MMDC_P1_MPRDDLCTL, 0x3C3E3C46,
 970
 971 MX6_MMDC_P0_MPWRDLCTL, 0x403E463E,
 972 MX6_MMDC_P1_MPWRDLCTL, 0x4A384C46,
 973
 974 MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E,
 975 MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B,
 976 MX6_MMDC_P1_MPWLDECTRL0, 0x00060015,
 977 MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E,
 978
 979 MX6_MMDC_P0_MPMUR0, 0x00000800,
 980 MX6_MMDC_P1_MPMUR0, 0x00000800,
 981 MX6_MMDC_P0_MDSCR, 0x00000000,
 982 MX6_MMDC_P0_MAPSR, 0x00011006,
 983 };
 984
 985 static void ccgr_init(void)
 986 {
 987         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 988
 989         writel(0x00C03F3F, &ccm->CCGR0);
 990         writel(0x0030FC03, &ccm->CCGR1);
 991         writel(0x0FFFFFF3, &ccm->CCGR2);
 992         writel(0x3FF0300F, &ccm->CCGR3);
 993         writel(0x00FFF300, &ccm->CCGR4);
 994         writel(0x0F0000F3, &ccm->CCGR5);
 995         writel(0x000003FF, &ccm->CCGR6);
 996
 997 /*
 998  * Setup CCM_CCOSR register as follows:
 999  *
1000  * cko1_en  = 1    --> CKO1 enabled
1001  * cko1_div = 111  --> divide by 8
1002  * cko1_sel = 1011 --> ahb_clk_root
1003  *
1004  * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
1005  */
1006         writel(0x000000FB, &ccm->ccosr);
1007 }
1008
1009 static void ddr_init(int *table, int size)
1010 {
1011         int i;
1012
1013         for (i = 0; i < size / 2 ; i++)
1014                 writel(table[2 * i + 1], table[2 * i]);
1015 }
1016
1017 static void spl_dram_init(void)
1018 {
1019         int minc, maxc;
1020
1021         switch (get_cpu_temp_grade(&minc, &maxc)) {
1022         case TEMP_COMMERCIAL:
1023         case TEMP_EXTCOMMERCIAL:
1024                 puts("Commercial temperature grade DDR3 timings.\n");
1025                 ddr_init(mx6_com_dcd_table, ARRAY_SIZE(mx6_com_dcd_table));
1026                 break;
1027         case TEMP_INDUSTRIAL:
1028         case TEMP_AUTOMOTIVE:
1029         default:
1030                 puts("Industrial temperature grade DDR3 timings.\n");
1031                 ddr_init(mx6_it_dcd_table, ARRAY_SIZE(mx6_it_dcd_table));
1032                 break;
1033         };
1034         udelay(100);
1035 }
1036
1037 void board_init_f(ulong dummy)
1038 {
1039         /* setup AIPS and disable watchdog */
1040         arch_cpu_init();
1041
1042         ccgr_init();
1043         gpr_init();
1044
1045         /* iomux */
1046         board_early_init_f();
1047
1048         /* setup GP timer */
1049         timer_init();
1050
1051         /* UART clocks enabled and gd valid - init serial console */
1052         preloader_console_init();
1053
1054 #ifndef CONFIG_TDX_APALIS_IMX6_V1_0
1055         /* Make sure we use dte mode */
1056         setup_dtemode_uart();
1057 #endif
1058
1059         /* DDR initialization */
1060         spl_dram_init();
1061
1062         /* Clear the BSS. */
1063         memset(__bss_start, 0, __bss_end - __bss_start);
1064
1065         /* load/boot image from boot device */
1066         board_init_r(NULL, 0);
1067 }
1068
1069 #ifdef CONFIG_SPL_LOAD_FIT
1070 int board_fit_config_name_match(const char *name)
1071 {
1072         if (!strcmp(name, "imx6-apalis"))
1073                 return 0;
1074
1075         return -1;
1076 }
1077 #endif
1078
1079 void reset_cpu(ulong addr)
1080 {
1081 }
1082
1083 #endif /* CONFIG_SPL_BUILD */
1084
1085 static struct mxc_serial_platdata mxc_serial_plat = {
1086         .reg = (struct mxc_uart *)UART1_BASE,
1087         .use_dte = true,
1088 };
1089
1090 U_BOOT_DEVICE(mxc_serial) = {
1091         .name = "serial_mxc",
1092         .platdata = &mxc_serial_plat,
1093 };