board/toradex/apalis_imx6/apalis_imx6.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
   4  * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
   5  * Copyright (C) 2014-2019, Toradex AG
   6  * copied from nitrogen6x
   7  */
   8
   9 #include <common.h>
  10 #include <dm.h>
  11
  12 #include <ahci.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/crm_regs.h>
  15 #include <asm/arch/imx-regs.h>
  16 #include <asm/arch/mx6-ddr.h>
  17 #include <asm/arch/mx6-pins.h>
  18 #include <asm/arch/mxc_hdmi.h>
  19 #include <asm/arch/sys_proto.h>
  20 #include <asm/bootm.h>
  21 #include <asm/gpio.h>
  22 #include <asm/mach-imx/boot_mode.h>
  23 #include <asm/mach-imx/iomux-v3.h>
  24 #include <asm/mach-imx/sata.h>
  25 #include <asm/mach-imx/video.h>
  26 #include <dm/device-internal.h>
  27 #include <dm/platform_data/serial_mxc.h>
  28 #include <dwc_ahsata.h>
  29 #include <environment.h>
  30 #include <fsl_esdhc.h>
  31 #include <imx_thermal.h>
  32 #include <micrel.h>
  33 #include <miiphy.h>
  34 #include <netdev.h>
  35
  36 #include "../common/tdx-cfg-block.h"
  37 #ifdef CONFIG_TDX_CMD_IMX_MFGR
  38 #include "pf0100.h"
  39 #endif
  40
  41 DECLARE_GLOBAL_DATA_PTR;
  42
  43 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  44         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  45         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  46
  47 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  48         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  49         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  50
  51 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  52         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  53
  54 #define WEAK_PULLUP     (PAD_CTL_PUS_100K_UP |                  \
  55         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  56         PAD_CTL_SRE_SLOW)
  57
  58 #define WEAK_PULLDOWN   (PAD_CTL_PUS_100K_DOWN |                \
  59         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  60         PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
  61
  62 #define TRISTATE        (PAD_CTL_HYS | PAD_CTL_SPEED_MED)
  63
  64 #define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST)
  65
  66 #define APALIS_IMX6_SATA_INIT_RETRIES   10
  67
  68 int dram_init(void)
  69 {
  70         /* use the DDR controllers configured size */
  71         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  72                                     (ulong)imx_ddr_size());
  73
  74         return 0;
  75 }
  76
  77 /* Apalis UART1 */
  78 iomux_v3_cfg_t const uart1_pads_dce[] = {
  79         MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  80         MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  81 };
  82 iomux_v3_cfg_t const uart1_pads_dte[] = {
  83         MX6_PAD_CSI0_DAT10__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  84         MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  85 };
  86
  87 #if defined(CONFIG_FSL_ESDHC) && defined(CONFIG_SPL_BUILD)
  88 /* Apalis MMC1 */
  89 iomux_v3_cfg_t const usdhc1_pads[] = {
  90         MX6_PAD_SD1_CLK__SD1_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  91         MX6_PAD_SD1_CMD__SD1_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  92         MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  93         MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  94         MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  95         MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  96         MX6_PAD_NANDF_D0__SD1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  97         MX6_PAD_NANDF_D1__SD1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  98         MX6_PAD_NANDF_D2__SD1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  99         MX6_PAD_NANDF_D3__SD1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 100         MX6_PAD_DI0_PIN4__GPIO4_IO20   | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 101 #       define GPIO_MMC_CD IMX_GPIO_NR(4, 20)
 102 };
 103
 104 /* Apalis SD1 */
 105 iomux_v3_cfg_t const usdhc2_pads[] = {
 106         MX6_PAD_SD2_CLK__SD2_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 107         MX6_PAD_SD2_CMD__SD2_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 108         MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 109         MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 110         MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 111         MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 112         MX6_PAD_NANDF_CS1__GPIO6_IO14  | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 113 #       define GPIO_SD_CD IMX_GPIO_NR(6, 14)
 114 };
 115
 116 /* eMMC */
 117 iomux_v3_cfg_t const usdhc3_pads[] = {
 118         MX6_PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 119         MX6_PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 120         MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 121         MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 122         MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 123         MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 124         MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 125         MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 126         MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 127         MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 128         MX6_PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) | MUX_MODE_SION,
 129 };
 130 #endif /* CONFIG_FSL_ESDHC & CONFIG_SPL_BUILD */
 131
 132 int mx6_rgmii_rework(struct phy_device *phydev)
 133 {
 134         /* control data pad skew - devaddr = 0x02, register = 0x04 */
 135         ksz9031_phy_extended_write(phydev, 0x02,
 136                                    MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
 137                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
 138         /* rx data pad skew - devaddr = 0x02, register = 0x05 */
 139         ksz9031_phy_extended_write(phydev, 0x02,
 140                                    MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
 141                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
 142         /* tx data pad skew - devaddr = 0x02, register = 0x05 */
 143         ksz9031_phy_extended_write(phydev, 0x02,
 144                                    MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
 145                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
 146         /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
 147         ksz9031_phy_extended_write(phydev, 0x02,
 148                                    MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
 149                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
 150         return 0;
 151 }
 152
 153 iomux_v3_cfg_t const enet_pads[] = {
 154         MX6_PAD_ENET_MDIO__ENET_MDIO            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 155         MX6_PAD_ENET_MDC__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
 156         MX6_PAD_RGMII_TXC__RGMII_TXC            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 157         MX6_PAD_RGMII_TD0__RGMII_TD0            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 158         MX6_PAD_RGMII_TD1__RGMII_TD1            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 159         MX6_PAD_RGMII_TD2__RGMII_TD2            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 160         MX6_PAD_RGMII_TD3__RGMII_TD3            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 161         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 162         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 163         MX6_PAD_RGMII_RXC__RGMII_RXC            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 164         MX6_PAD_RGMII_RD0__RGMII_RD0            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 165         MX6_PAD_RGMII_RD1__RGMII_RD1            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 166         MX6_PAD_RGMII_RD2__RGMII_RD2            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 167         MX6_PAD_RGMII_RD3__RGMII_RD3            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 168         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 169         /* KSZ9031 PHY Reset */
 170         MX6_PAD_ENET_CRS_DV__GPIO1_IO25         | MUX_PAD_CTRL(NO_PAD_CTRL) |
 171                                                   MUX_MODE_SION,
 172 #       define GPIO_ENET_PHY_RESET IMX_GPIO_NR(1, 25)
 173 };
 174
 175 static void setup_iomux_enet(void)
 176 {
 177         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
 178 }
 179
 180 static int reset_enet_phy(struct mii_dev *bus)
 181 {
 182         /* Reset KSZ9031 PHY */
 183         gpio_request(GPIO_ENET_PHY_RESET, "ETH_RESET#");
 184         gpio_direction_output(GPIO_ENET_PHY_RESET, 0);
 185         mdelay(10);
 186         gpio_set_value(GPIO_ENET_PHY_RESET, 1);
 187
 188         return 0;
 189 }
 190
 191 /* mux the Apalis GPIO pins, so they can be used from the U-Boot cmdline */
 192 iomux_v3_cfg_t const gpio_pads[] = {
 193         /* Apalis GPIO1 - GPIO8 */
 194         MX6_PAD_NANDF_D4__GPIO2_IO04    | MUX_PAD_CTRL(WEAK_PULLUP) |
 195                                           MUX_MODE_SION,
 196         MX6_PAD_NANDF_D5__GPIO2_IO05    | MUX_PAD_CTRL(WEAK_PULLUP) |
 197                                           MUX_MODE_SION,
 198         MX6_PAD_NANDF_D6__GPIO2_IO06    | MUX_PAD_CTRL(WEAK_PULLUP) |
 199                                           MUX_MODE_SION,
 200         MX6_PAD_NANDF_D7__GPIO2_IO07    | MUX_PAD_CTRL(WEAK_PULLUP) |
 201                                           MUX_MODE_SION,
 202         MX6_PAD_NANDF_RB0__GPIO6_IO10   | MUX_PAD_CTRL(WEAK_PULLUP) |
 203                                           MUX_MODE_SION,
 204         MX6_PAD_NANDF_WP_B__GPIO6_IO09  | MUX_PAD_CTRL(WEAK_PULLUP) |
 205                                           MUX_MODE_SION,
 206         MX6_PAD_GPIO_2__GPIO1_IO02      | MUX_PAD_CTRL(WEAK_PULLDOWN) |
 207                                           MUX_MODE_SION,
 208         MX6_PAD_GPIO_6__GPIO1_IO06      | MUX_PAD_CTRL(WEAK_PULLUP) |
 209                                           MUX_MODE_SION,
 210         MX6_PAD_GPIO_4__GPIO1_IO04      | MUX_PAD_CTRL(WEAK_PULLUP) |
 211                                           MUX_MODE_SION,
 212 };
 213
 214 static void setup_iomux_gpio(void)
 215 {
 216         imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
 217 }
 218
 219 iomux_v3_cfg_t const usb_pads[] = {
 220         /* USBH_EN */
 221         MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
 222 #       define GPIO_USBH_EN IMX_GPIO_NR(1, 0)
 223         /* USB_VBUS_DET */
 224         MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
 225 #       define GPIO_USB_VBUS_DET IMX_GPIO_NR(3, 28)
 226         /* USBO1_ID */
 227         MX6_PAD_ENET_RX_ER__USB_OTG_ID  | MUX_PAD_CTRL(WEAK_PULLUP),
 228         /* USBO1_EN */
 229         MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
 230 #       define GPIO_USBO_EN IMX_GPIO_NR(3, 22)
 231 };
 232
 233 /*
 234  * UARTs are used in DTE mode, switch the mode on all UARTs before
 235  * any pinmuxing connects a (DCE) output to a transceiver output.
 236  */
 237 #define UFCR            0x90    /* FIFO Control Register */
 238 #define UFCR_DCEDTE     (1<<6)  /* DCE=0 */
 239
 240 static void setup_dtemode_uart(void)
 241 {
 242         setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
 243         setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
 244         setbits_le32((u32 *)(UART4_BASE + UFCR), UFCR_DCEDTE);
 245         setbits_le32((u32 *)(UART5_BASE + UFCR), UFCR_DCEDTE);
 246 }
 247 static void setup_dcemode_uart(void)
 248 {
 249         clrbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
 250         clrbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
 251         clrbits_le32((u32 *)(UART4_BASE + UFCR), UFCR_DCEDTE);
 252         clrbits_le32((u32 *)(UART5_BASE + UFCR), UFCR_DCEDTE);
 253 }
 254
 255 static void setup_iomux_dte_uart(void)
 256 {
 257         setup_dtemode_uart();
 258         imx_iomux_v3_setup_multiple_pads(uart1_pads_dte,
 259                                          ARRAY_SIZE(uart1_pads_dte));
 260 }
 261 static void setup_iomux_dce_uart(void)
 262 {
 263         setup_dcemode_uart();
 264         imx_iomux_v3_setup_multiple_pads(uart1_pads_dce,
 265                                          ARRAY_SIZE(uart1_pads_dce));
 266 }
 267
 268 #ifdef CONFIG_USB_EHCI_MX6
 269 int board_ehci_hcd_init(int port)
 270 {
 271         imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
 272         return 0;
 273 }
 274 #endif
 275
 276 #if defined(CONFIG_FSL_ESDHC) && defined(CONFIG_SPL_BUILD)
 277 /* use the following sequence: eMMC, MMC1, SD1 */
 278 struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
 279         {USDHC3_BASE_ADDR},
 280         {USDHC1_BASE_ADDR},
 281         {USDHC2_BASE_ADDR},
 282 };
 283
 284 int board_mmc_getcd(struct mmc *mmc)
 285 {
 286         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 287         int ret = true; /* default: assume inserted */
 288
 289         switch (cfg->esdhc_base) {
 290         case USDHC1_BASE_ADDR:
 291                 gpio_request(GPIO_MMC_CD, "MMC_CD");
 292                 gpio_direction_input(GPIO_MMC_CD);
 293                 ret = !gpio_get_value(GPIO_MMC_CD);
 294                 break;
 295         case USDHC2_BASE_ADDR:
 296                 gpio_request(GPIO_MMC_CD, "SD_CD");
 297                 gpio_direction_input(GPIO_SD_CD);
 298                 ret = !gpio_get_value(GPIO_SD_CD);
 299                 break;
 300         }
 301
 302         return ret;
 303 }
 304
 305 int board_mmc_init(bd_t *bis)
 306 {
 307         struct src *psrc = (struct src *)SRC_BASE_ADDR;
 308         unsigned reg = readl(&psrc->sbmr1) >> 11;
 309         /*
 310          * Upon reading BOOT_CFG register the following map is done:
 311          * Bit 11 and 12 of BOOT_CFG register can determine the current
 312          * mmc port
 313          * 0x1                  SD1
 314          * 0x2                  SD2
 315          * 0x3                  SD4
 316          */
 317
 318         switch (reg & 0x3) {
 319         case 0x0:
 320                 imx_iomux_v3_setup_multiple_pads(
 321                         usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
 322                 usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
 323                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 324                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 325                 break;
 326         case 0x1:
 327                 imx_iomux_v3_setup_multiple_pads(
 328                         usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 329                 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
 330                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 331                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 332                 break;
 333         case 0x2:
 334                 imx_iomux_v3_setup_multiple_pads(
 335                         usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 336                 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
 337                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 338                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 339                 break;
 340         default:
 341                 puts("MMC boot device not available");
 342         }
 343
 344         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 345 }
 346 #endif /* CONFIG_FSL_ESDHC & CONFIG_SPL_BUILD */
 347
 348 int board_phy_config(struct phy_device *phydev)
 349 {
 350         mx6_rgmii_rework(phydev);
 351         if (phydev->drv->config)
 352                 phydev->drv->config(phydev);
 353
 354         return 0;
 355 }
 356
 357 int board_eth_init(bd_t *bis)
 358 {
 359         uint32_t base = IMX_FEC_BASE;
 360         struct mii_dev *bus = NULL;
 361         struct phy_device *phydev = NULL;
 362         int ret;
 363
 364         setup_iomux_enet();
 365
 366 #ifdef CONFIG_FEC_MXC
 367         bus = fec_get_miibus(base, -1);
 368         if (!bus)
 369                 return 0;
 370
 371         bus->reset = reset_enet_phy;
 372         /* scan PHY 4,5,6,7 */
 373         phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
 374         if (!phydev) {
 375                 free(bus);
 376                 puts("no PHY found\n");
 377                 return 0;
 378         }
 379
 380         printf("using PHY at %d\n", phydev->addr);
 381         ret = fec_probe(bis, -1, base, bus, phydev);
 382         if (ret) {
 383                 printf("FEC MXC: %s:failed\n", __func__);
 384                 free(phydev);
 385                 free(bus);
 386         }
 387 #endif /* CONFIG_FEC_MXC */
 388
 389         return 0;
 390 }
 391
 392 static iomux_v3_cfg_t const pwr_intb_pads[] = {
 393         /*
 394          * the bootrom sets the iomux to vselect, potentially connecting
 395          * two outputs. Set this back to GPIO
 396          */
 397         MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)
 398 };
 399
 400 #if defined(CONFIG_VIDEO_IPUV3)
 401
 402 static iomux_v3_cfg_t const backlight_pads[] = {
 403         /* Backlight on RGB connector: J15 */
 404         MX6_PAD_EIM_DA13__GPIO3_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL) |
 405                                        MUX_MODE_SION,
 406 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 13)
 407         /* additional CPU pin on BKL_PWM, keep in tristate */
 408         MX6_PAD_EIM_DA14__GPIO3_IO14 | MUX_PAD_CTRL(TRISTATE),
 409         /* Backlight PWM, used as GPIO in U-Boot */
 410         MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL) |
 411                                        MUX_MODE_SION,
 412 #define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 10)
 413         /* buffer output enable 0: buffer enabled */
 414         MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(WEAK_PULLUP) | MUX_MODE_SION,
 415 #define RGB_BACKLIGHTPWM_OE IMX_GPIO_NR(5, 2)
 416         /* PSAVE# integrated VDAC */
 417         MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL) |
 418                                        MUX_MODE_SION,
 419 #define VGA_PSAVE_NOT_GP IMX_GPIO_NR(6, 31)
 420 };
 421
 422 static iomux_v3_cfg_t const rgb_pads[] = {
 423         MX6_PAD_EIM_A16__IPU1_DI1_DISP_CLK | MUX_PAD_CTRL(OUTPUT_RGB),
 424         MX6_PAD_EIM_DA10__IPU1_DI1_PIN15 | MUX_PAD_CTRL(OUTPUT_RGB),
 425         MX6_PAD_EIM_DA11__IPU1_DI1_PIN02 | MUX_PAD_CTRL(OUTPUT_RGB),
 426         MX6_PAD_EIM_DA12__IPU1_DI1_PIN03 | MUX_PAD_CTRL(OUTPUT_RGB),
 427         MX6_PAD_EIM_DA9__IPU1_DISP1_DATA00 | MUX_PAD_CTRL(OUTPUT_RGB),
 428         MX6_PAD_EIM_DA8__IPU1_DISP1_DATA01 | MUX_PAD_CTRL(OUTPUT_RGB),
 429         MX6_PAD_EIM_DA7__IPU1_DISP1_DATA02 | MUX_PAD_CTRL(OUTPUT_RGB),
 430         MX6_PAD_EIM_DA6__IPU1_DISP1_DATA03 | MUX_PAD_CTRL(OUTPUT_RGB),
 431         MX6_PAD_EIM_DA5__IPU1_DISP1_DATA04 | MUX_PAD_CTRL(OUTPUT_RGB),
 432         MX6_PAD_EIM_DA4__IPU1_DISP1_DATA05 | MUX_PAD_CTRL(OUTPUT_RGB),
 433         MX6_PAD_EIM_DA3__IPU1_DISP1_DATA06 | MUX_PAD_CTRL(OUTPUT_RGB),
 434         MX6_PAD_EIM_DA2__IPU1_DISP1_DATA07 | MUX_PAD_CTRL(OUTPUT_RGB),
 435         MX6_PAD_EIM_DA1__IPU1_DISP1_DATA08 | MUX_PAD_CTRL(OUTPUT_RGB),
 436         MX6_PAD_EIM_DA0__IPU1_DISP1_DATA09 | MUX_PAD_CTRL(OUTPUT_RGB),
 437         MX6_PAD_EIM_EB1__IPU1_DISP1_DATA10 | MUX_PAD_CTRL(OUTPUT_RGB),
 438         MX6_PAD_EIM_EB0__IPU1_DISP1_DATA11 | MUX_PAD_CTRL(OUTPUT_RGB),
 439         MX6_PAD_EIM_A17__IPU1_DISP1_DATA12 | MUX_PAD_CTRL(OUTPUT_RGB),
 440         MX6_PAD_EIM_A18__IPU1_DISP1_DATA13 | MUX_PAD_CTRL(OUTPUT_RGB),
 441         MX6_PAD_EIM_A19__IPU1_DISP1_DATA14 | MUX_PAD_CTRL(OUTPUT_RGB),
 442         MX6_PAD_EIM_A20__IPU1_DISP1_DATA15 | MUX_PAD_CTRL(OUTPUT_RGB),
 443         MX6_PAD_EIM_A21__IPU1_DISP1_DATA16 | MUX_PAD_CTRL(OUTPUT_RGB),
 444         MX6_PAD_EIM_A22__IPU1_DISP1_DATA17 | MUX_PAD_CTRL(OUTPUT_RGB),
 445         MX6_PAD_EIM_A23__IPU1_DISP1_DATA18 | MUX_PAD_CTRL(OUTPUT_RGB),
 446         MX6_PAD_EIM_A24__IPU1_DISP1_DATA19 | MUX_PAD_CTRL(OUTPUT_RGB),
 447         MX6_PAD_EIM_D26__IPU1_DISP1_DATA22 | MUX_PAD_CTRL(OUTPUT_RGB),
 448         MX6_PAD_EIM_D27__IPU1_DISP1_DATA23 | MUX_PAD_CTRL(OUTPUT_RGB),
 449         MX6_PAD_EIM_D30__IPU1_DISP1_DATA21 | MUX_PAD_CTRL(OUTPUT_RGB),
 450         MX6_PAD_EIM_D31__IPU1_DISP1_DATA20 | MUX_PAD_CTRL(OUTPUT_RGB),
 451 };
 452
 453 static void do_enable_hdmi(struct display_info_t const *dev)
 454 {
 455         imx_enable_hdmi_phy();
 456 }
 457
 458 static void enable_lvds(struct display_info_t const *dev)
 459 {
 460         struct iomuxc *iomux = (struct iomuxc *)
 461                                 IOMUXC_BASE_ADDR;
 462         u32 reg = readl(&iomux->gpr[2]);
 463         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
 464         writel(reg, &iomux->gpr[2]);
 465         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 466         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
 467         gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
 468 }
 469
 470 static void enable_rgb(struct display_info_t const *dev)
 471 {
 472         imx_iomux_v3_setup_multiple_pads(
 473                 rgb_pads,
 474                 ARRAY_SIZE(rgb_pads));
 475         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 476         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
 477         gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
 478 }
 479
 480 static int detect_default(struct display_info_t const *dev)
 481 {
 482         (void) dev;
 483         return 1;
 484 }
 485
 486 struct display_info_t const displays[] = {{
 487         .bus    = -1,
 488         .addr   = 0,
 489         .pixfmt = IPU_PIX_FMT_RGB24,
 490         .detect = detect_hdmi,
 491         .enable = do_enable_hdmi,
 492         .mode   = {
 493                 .name           = "HDMI",
 494                 .refresh        = 60,
 495                 .xres           = 1024,
 496                 .yres           = 768,
 497                 .pixclock       = 15385,
 498                 .left_margin    = 220,
 499                 .right_margin   = 40,
 500                 .upper_margin   = 21,
 501                 .lower_margin   = 7,
 502                 .hsync_len      = 60,
 503                 .vsync_len      = 10,
 504                 .sync           = FB_SYNC_EXT,
 505                 .vmode          = FB_VMODE_NONINTERLACED
 506 } }, {
 507         .bus    = -1,
 508         .addr   = 0,
 509         .di     = 1,
 510         .pixfmt = IPU_PIX_FMT_RGB24,
 511         .detect = detect_default,
 512         .enable = enable_rgb,
 513         .mode   = {
 514                 .name           = "vga-rgb",
 515                 .refresh        = 60,
 516                 .xres           = 640,
 517                 .yres           = 480,
 518                 .pixclock       = 33000,
 519                 .left_margin    = 48,
 520                 .right_margin   = 16,
 521                 .upper_margin   = 31,
 522                 .lower_margin   = 11,
 523                 .hsync_len      = 96,
 524                 .vsync_len      = 2,
 525                 .sync           = 0,
 526                 .vmode          = FB_VMODE_NONINTERLACED
 527 } }, {
 528         .bus    = -1,
 529         .addr   = 0,
 530         .di     = 1,
 531         .pixfmt = IPU_PIX_FMT_RGB24,
 532         .enable = enable_rgb,
 533         .mode   = {
 534                 .name           = "wvga-rgb",
 535                 .refresh        = 60,
 536                 .xres           = 800,
 537                 .yres           = 480,
 538                 .pixclock       = 25000,
 539                 .left_margin    = 40,
 540                 .right_margin   = 88,
 541                 .upper_margin   = 33,
 542                 .lower_margin   = 10,
 543                 .hsync_len      = 128,
 544                 .vsync_len      = 2,
 545                 .sync           = 0,
 546                 .vmode          = FB_VMODE_NONINTERLACED
 547 } }, {
 548         .bus    = -1,
 549         .addr   = 0,
 550         .pixfmt = IPU_PIX_FMT_LVDS666,
 551         .enable = enable_lvds,
 552         .mode   = {
 553                 .name           = "wsvga-lvds",
 554                 .refresh        = 60,
 555                 .xres           = 1024,
 556                 .yres           = 600,
 557                 .pixclock       = 15385,
 558                 .left_margin    = 220,
 559                 .right_margin   = 40,
 560                 .upper_margin   = 21,
 561                 .lower_margin   = 7,
 562                 .hsync_len      = 60,
 563                 .vsync_len      = 10,
 564                 .sync           = FB_SYNC_EXT,
 565                 .vmode          = FB_VMODE_NONINTERLACED
 566 } } };
 567 size_t display_count = ARRAY_SIZE(displays);
 568
 569 static void setup_display(void)
 570 {
 571         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 572         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 573         int reg;
 574
 575         enable_ipu_clock();
 576         imx_setup_hdmi();
 577         /* Turn on LDB0,IPU,IPU DI0 clocks */
 578         reg = __raw_readl(&mxc_ccm->CCGR3);
 579         reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
 580         writel(reg, &mxc_ccm->CCGR3);
 581
 582         /* set LDB0, LDB1 clk select to 011/011 */
 583         reg = readl(&mxc_ccm->cs2cdr);
 584         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 585                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 586         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 587               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 588         writel(reg, &mxc_ccm->cs2cdr);
 589
 590         reg = readl(&mxc_ccm->cscmr2);
 591         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 592         writel(reg, &mxc_ccm->cscmr2);
 593
 594         reg = readl(&mxc_ccm->chsccdr);
 595         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 596                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 597         writel(reg, &mxc_ccm->chsccdr);
 598
 599         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 600              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 601              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 602              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 603              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 604              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 605              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 606              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 607              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 608         writel(reg, &iomux->gpr[2]);
 609
 610         reg = readl(&iomux->gpr[3]);
 611         reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
 612                         |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
 613             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 614                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 615         writel(reg, &iomux->gpr[3]);
 616
 617         /* backlight unconditionally on for now */
 618         imx_iomux_v3_setup_multiple_pads(backlight_pads,
 619                                          ARRAY_SIZE(backlight_pads));
 620         /* use 0 for EDT 7", use 1 for LG fullHD panel */
 621         gpio_request(RGB_BACKLIGHTPWM_GP, "BKL1_PWM");
 622         gpio_request(RGB_BACKLIGHTPWM_OE, "BKL1_PWM_EN");
 623         gpio_request(RGB_BACKLIGHT_GP, "BKL1_ON");
 624         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
 625         gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
 626         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 627 }
 628
 629 /*
 630  * Backlight off before OS handover
 631  */
 632 void board_preboot_os(void)
 633 {
 634         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 1);
 635         gpio_direction_output(RGB_BACKLIGHT_GP, 0);
 636 }
 637 #endif /* defined(CONFIG_VIDEO_IPUV3) */
 638
 639 int board_early_init_f(void)
 640 {
 641         imx_iomux_v3_setup_multiple_pads(pwr_intb_pads,
 642                                          ARRAY_SIZE(pwr_intb_pads));
 643 #ifndef CONFIG_TDX_APALIS_IMX6_V1_0
 644         setup_iomux_dte_uart();
 645 #else
 646         setup_iomux_dce_uart();
 647 #endif
 648         return 0;
 649 }
 650
 651 /*
 652  * Do not overwrite the console
 653  * Use always serial for U-Boot console
 654  */
 655 int overwrite_console(void)
 656 {
 657         return 1;
 658 }
 659
 660 int board_init(void)
 661 {
 662         /* address of boot parameters */
 663         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 664
 665 #if defined(CONFIG_VIDEO_IPUV3)
 666         setup_display();
 667 #endif
 668
 669 #ifdef CONFIG_TDX_CMD_IMX_MFGR
 670         (void) pmic_init();
 671 #endif
 672
 673 #ifdef CONFIG_SATA
 674         setup_sata();
 675 #endif
 676
 677         setup_iomux_gpio();
 678
 679         return 0;
 680 }
 681
 682 #ifdef CONFIG_BOARD_LATE_INIT
 683 int board_late_init(void)
 684 {
 685 #if defined(CONFIG_REVISION_TAG) && \
 686     defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
 687         char env_str[256];
 688         u32 rev;
 689
 690         rev = get_board_rev();
 691         snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev);
 692         env_set("board_rev", env_str);
 693
 694 #ifndef CONFIG_TDX_APALIS_IMX6_V1_0
 695         if ((rev & 0xfff0) == 0x0100) {
 696                 char *fdt_env;
 697
 698                 /* reconfigure the UART to DCE mode dynamically if on V1.0 HW */
 699                 setup_iomux_dce_uart();
 700
 701                 /* if using the default device tree, use version for V1.0 HW */
 702                 fdt_env = env_get("fdt_file");
 703                 if ((fdt_env != NULL) && (strcmp(FDT_FILE, fdt_env) == 0)) {
 704                         env_set("fdt_file", FDT_FILE_V1_0);
 705                         printf("patching fdt_file to " FDT_FILE_V1_0 "\n");
 706 #ifndef CONFIG_ENV_IS_NOWHERE
 707                         env_save();
 708 #endif
 709                 }
 710         }
 711 #endif /* CONFIG_TDX_APALIS_IMX6_V1_0 */
 712 #endif /* CONFIG_REVISION_TAG */
 713
 714         return 0;
 715 }
 716 #endif /* CONFIG_BOARD_LATE_INIT */
 717
 718 int checkboard(void)
 719 {
 720         char it[] = " IT";
 721         int minc, maxc;
 722
 723         switch (get_cpu_temp_grade(&minc, &maxc)) {
 724         case TEMP_AUTOMOTIVE:
 725         case TEMP_INDUSTRIAL:
 726                 break;
 727         case TEMP_EXTCOMMERCIAL:
 728         default:
 729                 it[0] = 0;
 730         };
 731         printf("Model: Toradex Apalis iMX6 %s %s%s\n",
 732                is_cpu_type(MXC_CPU_MX6D) ? "Dual" : "Quad",
 733                (gd->ram_size == 0x80000000) ? "2GB" :
 734                (gd->ram_size == 0x40000000) ? "1GB" : "512MB", it);
 735         return 0;
 736 }
 737
 738 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 739 int ft_board_setup(void *blob, bd_t *bd)
 740 {
 741         return ft_common_board_setup(blob, bd);
 742 }
 743 #endif
 744
 745 #ifdef CONFIG_CMD_BMODE
 746 static const struct boot_mode board_boot_modes[] = {
 747         /* 4-bit bus width */
 748         {"mmc", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
 749         {"sd",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 750         {NULL,  0},
 751 };
 752 #endif
 753
 754 int misc_init_r(void)
 755 {
 756 #ifdef CONFIG_CMD_BMODE
 757         add_board_boot_modes(board_boot_modes);
 758 #endif
 759         return 0;
 760 }
 761
 762 #ifdef CONFIG_LDO_BYPASS_CHECK
 763 /* TODO, use external pmic, for now always ldo_enable */
 764 void ldo_mode_set(int ldo_bypass)
 765 {
 766         return;
 767 }
 768 #endif
 769
 770 #ifdef CONFIG_SPL_BUILD
 771 #include <spl.h>
 772 #include <linux/libfdt.h>
 773 #include "asm/arch/mx6q-ddr.h"
 774 #include "asm/arch/iomux.h"
 775 #include "asm/arch/crm_regs.h"
 776
 777 static int mx6_com_dcd_table[] = {
 778 /* ddr-setup.cfg */
 779 MX6_IOM_DRAM_SDQS0, 0x00000030,
 780 MX6_IOM_DRAM_SDQS1, 0x00000030,
 781 MX6_IOM_DRAM_SDQS2, 0x00000030,
 782 MX6_IOM_DRAM_SDQS3, 0x00000030,
 783 MX6_IOM_DRAM_SDQS4, 0x00000030,
 784 MX6_IOM_DRAM_SDQS5, 0x00000030,
 785 MX6_IOM_DRAM_SDQS6, 0x00000030,
 786 MX6_IOM_DRAM_SDQS7, 0x00000030,
 787
 788 MX6_IOM_GRP_B0DS, 0x00000030,
 789 MX6_IOM_GRP_B1DS, 0x00000030,
 790 MX6_IOM_GRP_B2DS, 0x00000030,
 791 MX6_IOM_GRP_B3DS, 0x00000030,
 792 MX6_IOM_GRP_B4DS, 0x00000030,
 793 MX6_IOM_GRP_B5DS, 0x00000030,
 794 MX6_IOM_GRP_B6DS, 0x00000030,
 795 MX6_IOM_GRP_B7DS, 0x00000030,
 796 MX6_IOM_GRP_ADDDS, 0x00000030,
 797 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 798 MX6_IOM_GRP_CTLDS, 0x00000030,
 799
 800 MX6_IOM_DRAM_DQM0, 0x00020030,
 801 MX6_IOM_DRAM_DQM1, 0x00020030,
 802 MX6_IOM_DRAM_DQM2, 0x00020030,
 803 MX6_IOM_DRAM_DQM3, 0x00020030,
 804 MX6_IOM_DRAM_DQM4, 0x00020030,
 805 MX6_IOM_DRAM_DQM5, 0x00020030,
 806 MX6_IOM_DRAM_DQM6, 0x00020030,
 807 MX6_IOM_DRAM_DQM7, 0x00020030,
 808
 809 MX6_IOM_DRAM_CAS, 0x00020030,
 810 MX6_IOM_DRAM_RAS, 0x00020030,
 811 MX6_IOM_DRAM_SDCLK_0, 0x00020030,
 812 MX6_IOM_DRAM_SDCLK_1, 0x00020030,
 813
 814 MX6_IOM_DRAM_RESET, 0x00020030,
 815 MX6_IOM_DRAM_SDCKE0, 0x00003000,
 816 MX6_IOM_DRAM_SDCKE1, 0x00003000,
 817
 818 MX6_IOM_DRAM_SDODT0, 0x00003030,
 819 MX6_IOM_DRAM_SDODT1, 0x00003030,
 820
 821 /* (differential input) */
 822 MX6_IOM_DDRMODE_CTL, 0x00020000,
 823 /* (differential input) */
 824 MX6_IOM_GRP_DDRMODE, 0x00020000,
 825 /* disable ddr pullups */
 826 MX6_IOM_GRP_DDRPKE, 0x00000000,
 827 MX6_IOM_DRAM_SDBA2, 0x00000000,
 828 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 829 MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
 830
 831 /* Read data DQ Byte0-3 delay */
 832 MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
 833 MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
 834 MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
 835 MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
 836 MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
 837 MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
 838 MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
 839 MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
 840
 841 /*
 842  * MDMISC       mirroring       interleaved (row/bank/col)
 843  */
 844 MX6_MMDC_P0_MDMISC, 0x00081740,
 845
 846 /*
 847  * MDSCR        con_req
 848  */
 849 MX6_MMDC_P0_MDSCR, 0x00008000,
 850
 851 /* 1066mhz_4x128mx16.cfg */
 852
 853 MX6_MMDC_P0_MDPDC, 0x00020036,
 854 MX6_MMDC_P0_MDCFG0, 0x555A7954,
 855 MX6_MMDC_P0_MDCFG1, 0xDB328F64,
 856 MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
 857 MX6_MMDC_P0_MDRWD, 0x000026D2,
 858 MX6_MMDC_P0_MDOR, 0x005A1023,
 859 MX6_MMDC_P0_MDOTC, 0x09555050,
 860 MX6_MMDC_P0_MDPDC, 0x00025576,
 861 MX6_MMDC_P0_MDASP, 0x00000027,
 862 MX6_MMDC_P0_MDCTL, 0x831A0000,
 863 MX6_MMDC_P0_MDSCR, 0x04088032,
 864 MX6_MMDC_P0_MDSCR, 0x00008033,
 865 MX6_MMDC_P0_MDSCR, 0x00428031,
 866 MX6_MMDC_P0_MDSCR, 0x19308030,
 867 MX6_MMDC_P0_MDSCR, 0x04008040,
 868 MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
 869 MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
 870 MX6_MMDC_P0_MDREF, 0x00005800,
 871 MX6_MMDC_P0_MPODTCTRL, 0x00000000,
 872 MX6_MMDC_P1_MPODTCTRL, 0x00000000,
 873
 874 MX6_MMDC_P0_MPDGCTRL0, 0x432A0338,
 875 MX6_MMDC_P0_MPDGCTRL1, 0x03260324,
 876 MX6_MMDC_P1_MPDGCTRL0, 0x43340344,
 877 MX6_MMDC_P1_MPDGCTRL1, 0x031E027C,
 878
 879 MX6_MMDC_P0_MPRDDLCTL, 0x33272D2E,
 880 MX6_MMDC_P1_MPRDDLCTL, 0x2F312B37,
 881
 882 MX6_MMDC_P0_MPWRDLCTL, 0x3A35433C,
 883 MX6_MMDC_P1_MPWRDLCTL, 0x4336453F,
 884
 885 MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E,
 886 MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B,
 887 MX6_MMDC_P1_MPWLDECTRL0, 0x00060015,
 888 MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E,
 889
 890 MX6_MMDC_P0_MPMUR0, 0x00000800,
 891 MX6_MMDC_P1_MPMUR0, 0x00000800,
 892 MX6_MMDC_P0_MDSCR, 0x00000000,
 893 MX6_MMDC_P0_MAPSR, 0x00011006,
 894 };
 895
 896 static int mx6_it_dcd_table[] = {
 897 /* ddr-setup.cfg */
 898 MX6_IOM_DRAM_SDQS0, 0x00000030,
 899 MX6_IOM_DRAM_SDQS1, 0x00000030,
 900 MX6_IOM_DRAM_SDQS2, 0x00000030,
 901 MX6_IOM_DRAM_SDQS3, 0x00000030,
 902 MX6_IOM_DRAM_SDQS4, 0x00000030,
 903 MX6_IOM_DRAM_SDQS5, 0x00000030,
 904 MX6_IOM_DRAM_SDQS6, 0x00000030,
 905 MX6_IOM_DRAM_SDQS7, 0x00000030,
 906
 907 MX6_IOM_GRP_B0DS, 0x00000030,
 908 MX6_IOM_GRP_B1DS, 0x00000030,
 909 MX6_IOM_GRP_B2DS, 0x00000030,
 910 MX6_IOM_GRP_B3DS, 0x00000030,
 911 MX6_IOM_GRP_B4DS, 0x00000030,
 912 MX6_IOM_GRP_B5DS, 0x00000030,
 913 MX6_IOM_GRP_B6DS, 0x00000030,
 914 MX6_IOM_GRP_B7DS, 0x00000030,
 915 MX6_IOM_GRP_ADDDS, 0x00000030,
 916 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 917 MX6_IOM_GRP_CTLDS, 0x00000030,
 918
 919 MX6_IOM_DRAM_DQM0, 0x00020030,
 920 MX6_IOM_DRAM_DQM1, 0x00020030,
 921 MX6_IOM_DRAM_DQM2, 0x00020030,
 922 MX6_IOM_DRAM_DQM3, 0x00020030,
 923 MX6_IOM_DRAM_DQM4, 0x00020030,
 924 MX6_IOM_DRAM_DQM5, 0x00020030,
 925 MX6_IOM_DRAM_DQM6, 0x00020030,
 926 MX6_IOM_DRAM_DQM7, 0x00020030,
 927
 928 MX6_IOM_DRAM_CAS, 0x00020030,
 929 MX6_IOM_DRAM_RAS, 0x00020030,
 930 MX6_IOM_DRAM_SDCLK_0, 0x00020030,
 931 MX6_IOM_DRAM_SDCLK_1, 0x00020030,
 932
 933 MX6_IOM_DRAM_RESET, 0x00020030,
 934 MX6_IOM_DRAM_SDCKE0, 0x00003000,
 935 MX6_IOM_DRAM_SDCKE1, 0x00003000,
 936
 937 MX6_IOM_DRAM_SDODT0, 0x00003030,
 938 MX6_IOM_DRAM_SDODT1, 0x00003030,
 939
 940 /* (differential input) */
 941 MX6_IOM_DDRMODE_CTL, 0x00020000,
 942 /* (differential input) */
 943 MX6_IOM_GRP_DDRMODE, 0x00020000,
 944 /* disable ddr pullups */
 945 MX6_IOM_GRP_DDRPKE, 0x00000000,
 946 MX6_IOM_DRAM_SDBA2, 0x00000000,
 947 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 948 MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
 949
 950 /* Read data DQ Byte0-3 delay */
 951 MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
 952 MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
 953 MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
 954 MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
 955 MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
 956 MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
 957 MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
 958 MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
 959
 960 /*
 961  * MDMISC       mirroring       interleaved (row/bank/col)
 962  */
 963 MX6_MMDC_P0_MDMISC, 0x00081740,
 964
 965 /*
 966  * MDSCR        con_req
 967  */
 968 MX6_MMDC_P0_MDSCR, 0x00008000,
 969
 970 /* 1066mhz_4x256mx16.cfg */
 971
 972 MX6_MMDC_P0_MDPDC, 0x00020036,
 973 MX6_MMDC_P0_MDCFG0, 0x898E78f5,
 974 MX6_MMDC_P0_MDCFG1, 0xff328f64,
 975 MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
 976 MX6_MMDC_P0_MDRWD, 0x000026D2,
 977 MX6_MMDC_P0_MDOR, 0x008E1023,
 978 MX6_MMDC_P0_MDOTC, 0x09444040,
 979 MX6_MMDC_P0_MDPDC, 0x00025576,
 980 MX6_MMDC_P0_MDASP, 0x00000047,
 981 MX6_MMDC_P0_MDCTL, 0x841A0000,
 982 MX6_MMDC_P0_MDSCR, 0x02888032,
 983 MX6_MMDC_P0_MDSCR, 0x00008033,
 984 MX6_MMDC_P0_MDSCR, 0x00048031,
 985 MX6_MMDC_P0_MDSCR, 0x19408030,
 986 MX6_MMDC_P0_MDSCR, 0x04008040,
 987 MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
 988 MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
 989 MX6_MMDC_P0_MDREF, 0x00007800,
 990 MX6_MMDC_P0_MPODTCTRL, 0x00022227,
 991 MX6_MMDC_P1_MPODTCTRL, 0x00022227,
 992
 993 MX6_MMDC_P0_MPDGCTRL0, 0x03300338,
 994 MX6_MMDC_P0_MPDGCTRL1, 0x03240324,
 995 MX6_MMDC_P1_MPDGCTRL0, 0x03440350,
 996 MX6_MMDC_P1_MPDGCTRL1, 0x032C0308,
 997
 998 MX6_MMDC_P0_MPRDDLCTL, 0x40363C3E,
 999 MX6_MMDC_P1_MPRDDLCTL, 0x3C3E3C46,
1000
1001 MX6_MMDC_P0_MPWRDLCTL, 0x403E463E,
1002 MX6_MMDC_P1_MPWRDLCTL, 0x4A384C46,
1003
1004 MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E,
1005 MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B,
1006 MX6_MMDC_P1_MPWLDECTRL0, 0x00060015,
1007 MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E,
1008
1009 MX6_MMDC_P0_MPMUR0, 0x00000800,
1010 MX6_MMDC_P1_MPMUR0, 0x00000800,
1011 MX6_MMDC_P0_MDSCR, 0x00000000,
1012 MX6_MMDC_P0_MAPSR, 0x00011006,
1013 };
1014
1015 static void ccgr_init(void)
1016 {
1017         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1018
1019         writel(0x00C03F3F, &ccm->CCGR0);
1020         writel(0x0030FC03, &ccm->CCGR1);
1021         writel(0x0FFFFFF3, &ccm->CCGR2);
1022         writel(0x3FF0300F, &ccm->CCGR3);
1023         writel(0x00FFF300, &ccm->CCGR4);
1024         writel(0x0F0000F3, &ccm->CCGR5);
1025         writel(0x000003FF, &ccm->CCGR6);
1026
1027 /*
1028  * Setup CCM_CCOSR register as follows:
1029  *
1030  * cko1_en  = 1    --> CKO1 enabled
1031  * cko1_div = 111  --> divide by 8
1032  * cko1_sel = 1011 --> ahb_clk_root
1033  *
1034  * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
1035  */
1036         writel(0x000000FB, &ccm->ccosr);
1037 }
1038
1039 static void ddr_init(int *table, int size)
1040 {
1041         int i;
1042
1043         for (i = 0; i < size / 2 ; i++)
1044                 writel(table[2 * i + 1], table[2 * i]);
1045 }
1046
1047 static void spl_dram_init(void)
1048 {
1049         int minc, maxc;
1050
1051         switch (get_cpu_temp_grade(&minc, &maxc)) {
1052         case TEMP_COMMERCIAL:
1053         case TEMP_EXTCOMMERCIAL:
1054                 puts("Commercial temperature grade DDR3 timings.\n");
1055                 ddr_init(mx6_com_dcd_table, ARRAY_SIZE(mx6_com_dcd_table));
1056                 break;
1057         case TEMP_INDUSTRIAL:
1058         case TEMP_AUTOMOTIVE:
1059         default:
1060                 puts("Industrial temperature grade DDR3 timings.\n");
1061                 ddr_init(mx6_it_dcd_table, ARRAY_SIZE(mx6_it_dcd_table));
1062                 break;
1063         };
1064         udelay(100);
1065 }
1066
1067 void board_init_f(ulong dummy)
1068 {
1069         /* setup AIPS and disable watchdog */
1070         arch_cpu_init();
1071
1072         ccgr_init();
1073         gpr_init();
1074
1075         /* iomux */
1076         board_early_init_f();
1077
1078         /* setup GP timer */
1079         timer_init();
1080
1081         /* UART clocks enabled and gd valid - init serial console */
1082         preloader_console_init();
1083
1084 #ifndef CONFIG_TDX_APALIS_IMX6_V1_0
1085         /* Make sure we use dte mode */
1086         setup_dtemode_uart();
1087 #endif
1088
1089         /* DDR initialization */
1090         spl_dram_init();
1091
1092         /* Clear the BSS. */
1093         memset(__bss_start, 0, __bss_end - __bss_start);
1094
1095         /* load/boot image from boot device */
1096         board_init_r(NULL, 0);
1097 }
1098
1099 void reset_cpu(ulong addr)
1100 {
1101 }
1102
1103 #endif /* CONFIG_SPL_BUILD */
1104
1105 static struct mxc_serial_platdata mxc_serial_plat = {
1106         .reg = (struct mxc_uart *)UART1_BASE,
1107         .use_dte = true,
1108 };
1109
1110 U_BOOT_DEVICE(mxc_serial) = {
1111         .name = "serial_mxc",
1112         .platdata = &mxc_serial_plat,
1113 };
1114
1115 #if CONFIG_IS_ENABLED(AHCI)
1116 static int sata_imx_probe(struct udevice *dev)
1117 {
1118         int i, err;
1119
1120         for (i = 0; i < APALIS_IMX6_SATA_INIT_RETRIES; i++) {
1121                 err = setup_sata();
1122                 if (err) {
1123                         printf("SATA setup failed: %d\n", err);
1124                         return err;
1125                 }
1126
1127                 udelay(100);
1128
1129                 err = dwc_ahsata_probe(dev);
1130                 if (!err)
1131                         break;
1132
1133                 /* There is no device on the SATA port */
1134                 if (sata_dm_port_status(0, 0) == 0)
1135                         break;
1136
1137                 /* There's a device, but link not established. Retry */
1138                 device_remove(dev, DM_REMOVE_NORMAL);
1139         }
1140
1141         return 0;
1142 }
1143
1144 struct ahci_ops sata_imx_ops = {
1145         .port_status = dwc_ahsata_port_status,
1146         .reset  = dwc_ahsata_bus_reset,
1147         .scan   = dwc_ahsata_scan,
1148 };
1149
1150 static const struct udevice_id sata_imx_ids[] = {
1151         { .compatible = "fsl,imx6q-ahci" },
1152         { }
1153 };
1154
1155 U_BOOT_DRIVER(sata_imx) = {
1156         .name           = "dwc_ahci",
1157         .id             = UCLASS_AHCI,
1158         .of_match       = sata_imx_ids,
1159         .ops            = &sata_imx_ops,
1160         .probe          = sata_imx_probe,
1161 };
1162 #endif /* AHCI */