1 // SPDX-License-Identifier: GPL-2.0+
3 * Timll DevKit3250 board support, SPL board configuration
5 * (C) Copyright 2015 Vladimir Zapolskiy <vz@mleia.com>
10 #include <asm/arch/sys_proto.h>
11 #include <asm/arch/cpu.h>
12 #include <asm/arch/emc.h>
13 #include <asm/arch-lpc32xx/gpio.h>
16 static struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE;
19 * SDRAM K4S561632N-LC60 settings are selected in assumption that
20 * SDRAM clock may be set up to 166 MHz, however at the moment
21 * it is 104 MHz. Most delay values are converted to be a multiple of
22 * base clock, and precise pinned values are not needed here.
24 struct emc_dram_settings dram_64mb = {
25 .cmddelay = 0x0001C000,
26 .config0 = 0x00005682,
27 .rascas0 = 0x00000302,
28 .rdconfig = 0x00000011, /* undocumented but crucial value */
33 .twr = 83000000, /* tWR = tRDL = 2 CLK */
41 .refresh = 130000, /* 800 clock cycles */
47 void spl_board_init(void)
49 /* First of all silence buzzer controlled by GPO_20 */
50 writel((1 << 20), &gpio->p3_outp_clr);
52 lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART);
53 preloader_console_init();
58 * NAND initialization is done by nand_init(),
59 * here just enable NAND SLC clocks
61 lpc32xx_slc_nand_init();
64 u32 spl_boot_device(void)
66 return BOOT_DEVICE_NAND;