2 * (C) Copyright 2004-2009
3 * Texas Instruments Incorporated, <www.ti.com>
4 * Richard Woodruff <r-woodruff2@ti.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/arch/mmc_host_def.h>
29 #include <asm/arch/mux.h>
30 #include <asm/arch/mem.h>
31 #include <asm/arch/sys_proto.h>
32 #include <asm/mach-types.h>
35 DECLARE_GLOBAL_DATA_PTR;
37 const omap3_sysinfo sysinfo = {
39 "OMAP3 SDP3430 board",
40 #if defined(CONFIG_ENV_IS_IN_ONENAND)
42 #elif defined(CONFIG_ENV_IS_IN_NAND)
49 /* Timing definitions for GPMC controller for Sibley NOR */
50 static const u32 gpmc_sdp_nor[] = {
51 SDP3430_NOR_GPMC_CONF1,
52 SDP3430_NOR_GPMC_CONF2,
53 SDP3430_NOR_GPMC_CONF3,
54 SDP3430_NOR_GPMC_CONF4,
55 SDP3430_NOR_GPMC_CONF5,
56 SDP3430_NOR_GPMC_CONF6,
57 /*CONF7- computed as params */
61 * Timing definitions for GPMC controller for Debug Board
62 * Debug board contains access to ethernet and DIP Switch setting
65 static const u32 gpmc_sdp_debug[] = {
66 SDP3430_DEBUG_GPMC_CONF1,
67 SDP3430_DEBUG_GPMC_CONF2,
68 SDP3430_DEBUG_GPMC_CONF3,
69 SDP3430_DEBUG_GPMC_CONF4,
70 SDP3430_DEBUG_GPMC_CONF5,
71 SDP3430_DEBUG_GPMC_CONF6,
72 /*CONF7- computed as params */
75 /* Timing defintions for GPMC OneNAND */
76 static const u32 gpmc_sdp_onenand[] = {
77 SDP3430_ONENAND_GPMC_CONF1,
78 SDP3430_ONENAND_GPMC_CONF2,
79 SDP3430_ONENAND_GPMC_CONF3,
80 SDP3430_ONENAND_GPMC_CONF4,
81 SDP3430_ONENAND_GPMC_CONF5,
82 SDP3430_ONENAND_GPMC_CONF6,
83 /*CONF7- computed as params */
86 /* GPMC definitions for GPMC NAND */
87 static const u32 gpmc_sdp_nand[] = {
88 SDP3430_NAND_GPMC_CONF1,
89 SDP3430_NAND_GPMC_CONF2,
90 SDP3430_NAND_GPMC_CONF3,
91 SDP3430_NAND_GPMC_CONF4,
92 SDP3430_NAND_GPMC_CONF5,
93 SDP3430_NAND_GPMC_CONF6,
94 /*CONF7- computed as params */
97 /* gpmc_cfg is initialized by gpmc_init and we use it here */
98 extern struct gpmc *gpmc_cfg;
101 * @brief board_init - gpmc and basic setup as phase1 of boot sequence
107 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
108 /* TODO: Dynamically pop out CS mapping and program accordingly */
109 /* Configure devices for default ON ON ON settings */
110 enable_gpmc_cs_config(gpmc_sdp_nor, &gpmc_cfg->cs[0],
111 CONFIG_SYS_FLASH_BASE, GPMC_SIZE_128M);
112 enable_gpmc_cs_config(gpmc_sdp_nand, &gpmc_cfg->cs[1], 0x28000000,
114 enable_gpmc_cs_config(gpmc_sdp_onenand, &gpmc_cfg->cs[2], 0x20000000,
116 enable_gpmc_cs_config(gpmc_sdp_debug, &gpmc_cfg->cs[3], DEBUG_BASE,
118 /* board id for Linux */
119 gd->bd->bi_arch_number = MACH_TYPE_OMAP_3430SDP;
120 /* boot param addr */
121 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
126 #define LAN_RESET_REGISTER (CONFIG_LAN91C96_BASE + 0x01c)
127 #define ETH_CONTROL_REG (CONFIG_LAN91C96_BASE + 0x30b)
130 * @brief board_eth_init Take the Ethernet controller out of reset and wait
131 * for the EEPROM load to complete.
133 int board_eth_init(bd_t *bis)
136 #ifdef CONFIG_LAN91C96
139 writew(0x0, LAN_RESET_REGISTER);
141 writew(0x1, LAN_RESET_REGISTER);
146 } while (readw(LAN_RESET_REGISTER) != 0x1);
151 writew(0x0, LAN_RESET_REGISTER);
156 } while (readw(LAN_RESET_REGISTER) != 0x0000);
159 writeb(readb(ETH_CONTROL_REG) & ~0x1, ETH_CONTROL_REG);
161 rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
169 * @brief misc_init_r - Configure SDP board specific configurations
170 * such as power configurations, ethernet initialization as phase2 of
175 int misc_init_r(void)
178 * VAUX3 - 2.8V for DVI
181 * and turns on LEDA/LEDB (not needed ... NOP?)
183 twl4030_power_init();
185 /* FIXME finish setup:
186 * VAUX1 - 2.8V for mainboard I/O
187 * VAUX2 - 2.8V for camera
188 * VAUX4 - 1.8V for OMAP3 CSI
189 * VMMC1 - 3.15V (init, variable) for MMC1
190 * VMMC2 - 1.85V for MMC2
191 * VSIM - off (init, variable) for MMC1.DAT[3..7], SIM
199 * @brief set_muxconf_regs Setting up the configuration Mux registers
200 * specific to the hardware. Many pins need to be moved from protect
203 void set_muxconf_regs(void)
205 /* platform specific muxes */
209 #ifdef CONFIG_GENERIC_MMC
210 int board_mmc_init(bd_t *bis)