3 * Texas Instruments Incorporated, <www.ti.com>
4 * Aneesh V <aneesh@ti.com>
5 * Steve Sakoman <steve@sakoman.com>
7 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/omap.h>
12 #include <asm/arch/sys_proto.h>
13 #include <asm/arch/mmc_host_def.h>
16 #include <linux/usb/gadget.h>
17 #include <dwc3-uboot.h>
18 #include <dwc3-omap-uboot.h>
19 #include <ti-usb-phy-uboot.h>
23 #if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_XHCI_OMAP)
27 #include <asm/arch/clock.h>
28 #include <asm/arch/ehci.h>
29 #include <asm/ehci-omap.h>
30 #include <asm/arch/sata.h>
32 #define DIE_ID_REG_BASE (OMAP54XX_L4_CORE_BASE + 0x2000)
33 #define DIE_ID_REG_OFFSET 0x200
37 DECLARE_GLOBAL_DATA_PTR;
39 const struct omap_sysinfo sysinfo = {
40 "Board: OMAP5432 uEVM\n"
44 * @brief tca642x_init - uEVM default values for the GPIO expander
45 * input reg, output reg, polarity reg, configuration reg
47 struct tca642x_bank_info tca642x_init[] = {
51 .configuration_reg = 0x80 },
55 .configuration_reg = 0xff },
59 .configuration_reg = 0x40 },
62 #ifdef CONFIG_USB_DWC3
63 static struct dwc3_device usb_otg_ss = {
64 .maximum_speed = USB_SPEED_SUPER,
65 .base = OMAP5XX_USB_OTG_SS_BASE,
66 .tx_fifo_resize = false,
70 static struct dwc3_omap_device usb_otg_ss_glue = {
71 .base = (void *)OMAP5XX_USB_OTG_SS_GLUE_BASE,
72 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
76 static struct ti_usb_phy_device usb_phy_device = {
77 .pll_ctrl_base = (void *)OMAP5XX_USB3_PHY_PLL_CTRL,
78 .usb2_phy_power = (void *)OMAP5XX_USB2_PHY_POWER,
79 .usb3_phy_power = (void *)OMAP5XX_USB3_PHY_POWER,
83 int board_usb_init(int index, enum usb_init_type init)
86 printf("Invalid Controller Index\n");
90 if (init == USB_INIT_DEVICE) {
91 usb_otg_ss.dr_mode = USB_DR_MODE_PERIPHERAL;
92 usb_otg_ss_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
94 usb_otg_ss.dr_mode = USB_DR_MODE_HOST;
95 usb_otg_ss_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
98 enable_usb_clocks(index);
99 ti_usb_phy_uboot_init(&usb_phy_device);
100 dwc3_omap_uboot_init(&usb_otg_ss_glue);
101 dwc3_uboot_init(&usb_otg_ss);
106 int board_usb_cleanup(int index, enum usb_init_type init)
109 printf("Invalid Controller Index\n");
113 ti_usb_phy_uboot_exit(index);
114 dwc3_uboot_exit(index);
115 dwc3_omap_uboot_exit(index);
116 disable_usb_clocks(index);
121 int usb_gadget_handle_interrupts(int index)
125 status = dwc3_omap_uboot_interrupt_status(index);
127 dwc3_uboot_handle_interrupt(index);
141 gd->bd->bi_arch_number = MACH_TYPE_OMAP5_SEVM;
142 gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
144 tca642x_set_inital_state(CONFIG_SYS_I2C_TCA642X_ADDR, tca642x_init);
149 int board_eth_init(bd_t *bis)
154 #if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_XHCI_OMAP)
155 static void enable_host_clocks(void)
158 int hs_clk_ctrl_val = (OPTFCLKEN_HSIC60M_P3_CLK |
159 OPTFCLKEN_HSIC480M_P3_CLK |
160 OPTFCLKEN_HSIC60M_P2_CLK |
161 OPTFCLKEN_HSIC480M_P2_CLK |
162 OPTFCLKEN_UTMI_P3_CLK | OPTFCLKEN_UTMI_P2_CLK);
164 /* Enable port 2 and 3 clocks*/
165 setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, hs_clk_ctrl_val);
167 /* Enable port 2 and 3 usb host ports tll clocks*/
168 setbits_le32((*prcm)->cm_l3init_hsusbtll_clkctrl,
169 (OPTFCLKEN_USB_CH1_CLK_ENABLE | OPTFCLKEN_USB_CH2_CLK_ENABLE));
170 #ifdef CONFIG_USB_XHCI_OMAP
171 /* Enable the USB OTG Super speed clocks */
172 setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl,
173 (OPTFCLKEN_REFCLK960M | OTG_SS_CLKCTRL_MODULEMODE_HW));
176 auxclk = readl((*prcm)->scrm_auxclk1);
177 /* Request auxilary clock */
178 auxclk |= AUXCLK_ENABLE_MASK;
179 writel(auxclk, (*prcm)->scrm_auxclk1);
184 * @brief misc_init_r - Configure EVM board specific configurations
185 * such as power configurations, ethernet initialization as phase2 of
190 int misc_init_r(void)
192 #ifdef CONFIG_PALMAS_POWER
193 palmas_init_settings();
196 omap_die_id_usbethaddr();
201 void set_muxconf_regs(void)
203 do_set_mux((*ctrl)->control_padconf_core_base,
204 core_padconf_array_essential,
205 sizeof(core_padconf_array_essential) /
206 sizeof(struct pad_conf_entry));
208 do_set_mux((*ctrl)->control_padconf_wkup_base,
209 wkup_padconf_array_essential,
210 sizeof(wkup_padconf_array_essential) /
211 sizeof(struct pad_conf_entry));
214 #if defined(CONFIG_MMC)
215 int board_mmc_init(bd_t *bis)
217 omap_mmc_init(0, 0, 0, -1, -1);
218 omap_mmc_init(1, 0, 0, -1, -1);
223 #ifdef CONFIG_USB_EHCI_HCD
224 static struct omap_usbhs_board_data usbhs_bdata = {
225 .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
226 .port_mode[1] = OMAP_EHCI_PORT_MODE_HSIC,
227 .port_mode[2] = OMAP_EHCI_PORT_MODE_HSIC,
230 int ehci_hcd_init(int index, enum usb_init_type init,
231 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
235 enable_host_clocks();
237 ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
239 puts("Failed to initialize ehci\n");
246 int ehci_hcd_stop(void)
248 return omap_ehci_hcd_stop();
251 void usb_hub_reset_devices(int port)
253 /* The LAN9730 needs to be reset after the port power has been set. */
255 gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 0);
257 gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 1);
262 #ifdef CONFIG_USB_XHCI_OMAP
264 * @brief board_usb_init - Configure EVM board specific configurations
265 * for the LDO's and clocks for the USB blocks.
269 int board_usb_init(int index, enum usb_init_type init)
272 #ifdef CONFIG_PALMAS_USB_SS_PWR
273 ret = palmas_enable_ss_ldo();
276 enable_host_clocks();