2 * Board specific setup info
5 * Texas Instruments, <www.ti.com>
6 * Kshitij Gupta <Kshitij@ti.com>
8 * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
10 * Modified for OMAP 5912 OSK board by Rishi Bhattacharya, Apr 2004
11 * SPDX-License-Identifier: GPL-2.0+
17 #if defined(CONFIG_OMAP1610)
18 #include <./configs/omap1510.h>
24 /*------------------------------------------------------*
25 * Ensure i-cache is enabled *
26 * To configure TC regs without fetching instruction *
27 *------------------------------------------------------*/
28 mrc p15, 0, r0, c1, c0
30 mcr p15, 0, r0, c1, c0
32 /*------------------------------------------------------*
33 *mask all IRQs by setting all bits in the INTMR default*
34 *------------------------------------------------------*/
41 /*------------------------------------------------------*
42 * Set up ARM CLM registers (IDLECT1) *
43 *------------------------------------------------------*/
44 ldr r0, REG_ARM_IDLECT1
45 ldr r1, VAL_ARM_IDLECT1
48 /*------------------------------------------------------*
49 * Set up ARM CLM registers (IDLECT2) *
50 *------------------------------------------------------*/
51 ldr r0, REG_ARM_IDLECT2
52 ldr r1, VAL_ARM_IDLECT2
55 /*------------------------------------------------------*
56 * Set up ARM CLM registers (IDLECT3) *
57 *------------------------------------------------------*/
58 ldr r0, REG_ARM_IDLECT3
59 ldr r1, VAL_ARM_IDLECT3
62 mov r1, #0x01 /* PER_EN bit */
63 ldr r0, REG_ARM_RSTCT2
64 strh r1, [r0] /* CLKM; Peripheral reset. */
66 /* Set CLKM to Sync-Scalable */
74 cmp r2, #0x100 /* wait for any bubbles to finish */
81 /* a few nops to let settle */
94 /* Ramp up the clock to 96Mhz */
98 ands r1, r1, #0x10 /* Check if PLL is enabled. */
99 beq lock_end /* Do not look for lock if BYPASS selected */
102 ands r1, r1, #0x01 /* Check the LOCK bit.*/
103 beq 2b /* loop until bit goes hi. */
106 /*------------------------------------------------------*
107 * Turn off the watchdog during init... *
108 *------------------------------------------------------*/
110 ldr r1, WATCHDOG_VAL1
112 ldr r1, WATCHDOG_VAL2
133 /* Set memory timings corresponding to the new clock speed */
134 ldr r3, VAL_SDRAM_CONFIG_SDF0
136 /* Check execution location to determine current execution location
137 * and branch to appropriate initialization code.
139 mov r0, #0x10000000 /* Load physical SDRAM base. */
140 mov r1, pc /* Get current execution location. */
141 cmp r1, r0 /* Compare. */
142 bge skip_sdram /* Skip over EMIF-fast initialization if running from SDRAM. */
144 /* identify the device revision, -- TMX or TMP(TMS) */
145 ldr r0, REG_DEVICE_ID
148 ldr r0, VAL_DEVICE_ID_TMP
154 /* Enable TMP/TMS device new features */
156 ldr r1, REG_TC_EMIFF_DOUBLER
159 /* Enable new ac parameters */
161 ldr r1, REG_SDRAM_CONFIG2
164 ldr r3, VAL_SDRAM_CONFIG_SDF1
169 * Delay for SDRAM initialization.
171 mov r0, #0x1800 /* value should be checked */
173 subs r0, r0, #0x1 /* Decrement count */
177 * Set SDRAM control values. Disable refresh before MRS command.
180 /* mobile ddr operation */
181 ldr r0, REG_SDRAM_OPERATION
185 /* config register */
186 ldr r0, REG_SDRAM_CONFIG
189 /* manual command register */
190 ldr r0, REG_SDRAM_MANUAL_CMD
192 /* issue set cke high */
193 mov r1, #CMD_SDRAM_CKE_SET_HIGH
197 mov r1, #CMD_SDRAM_NOP
203 bne waitMDDR1 /* delay loop */
205 /* issue precharge */
206 mov r1, #CMD_SDRAM_PRECHARGE
209 /* issue autorefresh x 2 */
210 mov r1, #CMD_SDRAM_AUTOREFRESH
214 /* mrs register ddr mobile */
215 ldr r0, REG_SDRAM_MRS
219 /* emrs1 low-power register */
220 ldr r0, REG_SDRAM_EMRS1
221 /* self refresh on all banks */
225 ldr r0, REG_DLL_URD_CONTROL
226 ldr r1, DLL_URD_CONTROL_VAL
229 ldr r0, REG_DLL_LRD_CONTROL
230 ldr r1, DLL_LRD_CONTROL_VAL
233 ldr r0, REG_DLL_WRT_CONTROL
234 ldr r1, DLL_WRT_CONTROL_VAL
244 * Delay for SDRAM initialization.
248 subs r0, r0, #1 /* Decrement count. */
253 ldr r0, REG_SDRAM_CONFIG
258 ldr r1, VAL_TC_EMIFS_CS0_CONFIG
259 ldr r0, REG_TC_EMIFS_CS0_CONFIG
260 str r1, [r0] /* Chip Select 0 */
262 ldr r1, VAL_TC_EMIFS_CS1_CONFIG
263 ldr r0, REG_TC_EMIFS_CS1_CONFIG
264 str r1, [r0] /* Chip Select 1 */
266 ldr r1, VAL_TC_EMIFS_CS3_CONFIG
267 ldr r0, REG_TC_EMIFS_CS3_CONFIG
268 str r1, [r0] /* Chip Select 3 */
270 ldr r1, VAL_TC_EMIFS_DWS
271 ldr r0, REG_TC_EMIFS_DWS
272 str r1, [r0] /* Enable EMIFS.RDY for CS1 (ether) */
274 #ifdef CONFIG_H2_OMAP1610
275 /* inserting additional 2 clock cycle hold time for LAN */
276 ldr r0, REG_TC_EMIFS_CS1_ADVANCED
277 ldr r1, VAL_TC_EMIFS_CS1_ADVANCED
280 /* Start MPU Timer 1 */
281 ldr r0, REG_MPU_LOAD_TIMER
282 ldr r1, VAL_MPU_LOAD_TIMER
285 ldr r0, REG_MPU_CNTL_TIMER
286 ldr r1, VAL_MPU_CNTL_TIMER
290 * Setup a temporary stack
293 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
296 * Save the old lr(passed in ip) and the current lr to stack
301 * go setup pll, mux, memory
306 /* back to arch calling code */
309 /* the literal pools origin */
312 REG_DEVICE_ID: /* 32 bits */
316 REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */
318 REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */
320 REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */
322 REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */
324 REG_TC_EMIFS_DWS: /* 32 bits */
326 #ifdef CONFIG_H2_OMAP1610
327 REG_TC_EMIFS_CS1_ADVANCED: /* 32 bits */
331 /* MPU clock/reset/power mode control registers */
332 REG_ARM_CKCTL: /* 16 bits */
334 REG_ARM_IDLECT3: /* 16 bits */
336 REG_ARM_IDLECT2: /* 16 bits */
338 REG_ARM_IDLECT1: /* 16 bits */
340 REG_ARM_RSTCT2: /* 16 bits */
342 REG_ARM_SYSST: /* 16 bits */
345 /* DPLL control registers */
346 REG_DPLL1_CTL: /* 16 bits */
349 /* Watch Dog register */
350 /* secure watchdog stop */
353 /* watchdog write pending */
362 /* SDRAM config is: auto refresh enabled, 16 bit 4 bank,
363 counter @8192 rows, 10 ns, 8 burst */
368 REG_TC_EMIFF_DOUBLER: /* 32 bits */
371 /* Operation register */
375 /* Manual command register */
376 REG_SDRAM_MANUAL_CMD:
379 /* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
383 /* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
387 /* WRT DLL register */
391 .word 0x03f00002 /* Phase of 72deg, write offset +31 */
393 /* URD DLL register */
397 .word 0x00800002 /* Phase of 72deg, read offset +31 */
399 /* LRD DLL register */
403 .word 0x00800002 /* read offset +31 */
421 /* 96 MHz Samsung Mobile DDR */
422 /* Original setting for TMX device */
423 VAL_SDRAM_CONFIG_SDF0:
426 /* NEW_SYS_FREQ mode (valid only TMP/TMS devices) */
427 VAL_SDRAM_CONFIG_SDF1:
431 .word 0x2000 /* was: 0x3000, now use CLK_REF for timer input */
435 #ifdef CONFIG_OSK_OMAP5912
436 VAL_TC_EMIFS_CS0_CONFIG:
438 VAL_TC_EMIFS_CS1_CONFIG:
440 VAL_TC_EMIFS_CS2_CONFIG:
442 VAL_TC_EMIFS_CS3_CONFIG:
444 VAL_TC_EMIFS_DWS: /* Enable EMIFS.RDY for CS1 access (ether) */
446 VAL_DEVICE_ID_TMP: /* TMP/TMS=0xb65f, TMX=0xb58c */
450 #ifdef CONFIG_H2_OMAP1610
451 VAL_TC_EMIFS_CS0_CONFIG:
453 VAL_TC_EMIFS_CS1_CONFIG:
455 VAL_TC_EMIFS_CS2_CONFIG:
457 VAL_TC_EMIFS_CS3_CONFIG:
459 VAL_TC_EMIFS_CS1_ADVANCED:
471 .word CONFIG_SYS_INIT_SP_ADDR
474 .equ CMD_SDRAM_NOP, 0x00000000
475 .equ CMD_SDRAM_PRECHARGE, 0x00000001
476 .equ CMD_SDRAM_AUTOREFRESH, 0x00000002
477 .equ CMD_SDRAM_CKE_SET_HIGH, 0x00000007