3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
7 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
10 * Texas Instruments, <www.ti.com>
11 * Kshitij Gupta <Kshitij@ti.com>
13 * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
15 * See file CREDITS for list of people who contributed to this
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version.
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
36 #if defined(CONFIG_OMAP1610)
37 #include <./configs/omap1510.h>
40 DECLARE_GLOBAL_DATA_PTR;
42 #ifdef CONFIG_CS_AUTOBOOT
43 unsigned long omap_flash_base;
46 void flash__init (void);
47 void ether__init (void);
48 void set_muxconf_regs (void);
49 void peripheral_power_enable (void);
51 #define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
53 static inline void delay (unsigned long loops)
55 __asm__ volatile ("1:\n"
57 "bne 1b":"=r" (loops):"0" (loops));
61 * Miscellaneous platform dependent initialisations
66 /* adress of boot parameters */
67 gd->bd->bi_boot_params = 0x10000100;
69 /* Configure MUX settings */
71 peripheral_power_enable ();
73 /* this speeds up your boot a quite a bit. However to make it
74 * work, you need make sure your kernel startup flush bug is fixed.
85 int misc_init_r (void)
91 /******************************
94 ******************************/
95 void flash__init (void)
97 #define EMIFS_GlB_Config_REG 0xfffecc0c
100 #ifdef CONFIG_CS_AUTOBOOT
101 /* Check swapping of CS0 and CS3, set flash base accordingly */
102 omap_flash_base = ((*((u32 *)OMAP_EMIFS_CONFIG_REG) & 0x02) == 0) ?
103 PHYS_FLASH_1_BM0 : PHYS_FLASH_1_BM1;
105 regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG);
106 /* Turn off write protection for flash devices. */
107 regval = regval | 0x0001;
108 *((volatile unsigned int *) EMIFS_GlB_Config_REG) = regval;
110 /*************************************************************
112 Description: take the Ethernet controller out of reset and wait
113 for the EEPROM load to complete.
114 *************************************************************/
115 void ether__init (void)
117 #define ETH_CONTROL_REG 0x0400030b
119 #ifdef CONFIG_H2_OMAP1610
120 #define LAN_RESET_REGISTER 0x0400001c
122 /* The debug board on which the lan chip resides may not be powered
123 * ON at the same time as the OMAP chip. So wait in a loop until the
124 * lan reset register (on the debug board) is available (powered on)
125 * and reset the lan chip.
128 *((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000;
130 *((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0001;
132 } while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0001);
135 *((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000;
137 } while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0000);
140 *((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
144 /******************************
147 ******************************/
150 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
151 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
156 /******************************************************
157 Routine: set_muxconf_regs
158 Description: Setting up the configuration Mux registers
159 specific to the hardware
160 *******************************************************/
161 void set_muxconf_regs (void)
163 volatile unsigned int *MuxConfReg;
164 /* set each registers to its reset value; */
166 (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0);
167 /* setup for UART1 */
168 *MuxConfReg &= ~(0x02000000); /* bit 25 */
169 /* setup for UART2 */
170 *MuxConfReg &= ~(0x01000000); /* bit 24 */
171 /* Disable Uwire CS Hi-Z */
172 *MuxConfReg |= 0x08000000;
174 (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_3);
175 *MuxConfReg = 0x00000000;
177 (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_4);
178 *MuxConfReg = 0x00000000;
180 (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_5);
181 *MuxConfReg = 0x00000000;
183 (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_6);
184 /*setup mux for UART3 */
185 *MuxConfReg |= 0x00000001; /* bit3, 1, 0 (mux0 5,5,26) */
186 *MuxConfReg &= ~0x0000003e;
188 (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_7);
189 *MuxConfReg = 0x00000000;
191 (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_8);
192 /* Disable Uwire CS Hi-Z */
193 *MuxConfReg |= 0x00001200; /*bit 9 for CS0 12 for CS3 */
195 (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_9);
196 /* Need to turn on bits 21 and 12 in FUNC_MUX_CTRL_9 so the */
197 /* hardware will actually use TX and RTS based on bit 25 in */
198 /* FUNC_MUX_CTRL_0. I told you this thing was screwy! */
199 *MuxConfReg |= 0x00201000;
201 (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_A);
202 *MuxConfReg = 0x00000000;
204 (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_B);
205 *MuxConfReg = 0x00000000;
207 (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_C);
208 /* setup for UART2 */
209 /* Need to turn on bits 27 and 24 in FUNC_MUX_CTRL_C so the */
210 /* hardware will actually use TX and RTS based on bit 24 in */
211 /* FUNC_MUX_CTRL_0. */
212 *MuxConfReg |= 0x09000000;
214 (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_0);
215 *MuxConfReg = 0x00000000;
217 (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_1);
218 *MuxConfReg = 0x00000000;
219 /* mux setup for SD/MMC driver */
221 (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_2);
222 *MuxConfReg &= 0xFFFE0FFF;
224 (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_3);
225 *MuxConfReg = 0x00000000;
227 (volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
228 /* bit 13 for MMC2 XOR_CLK */
229 *MuxConfReg &= ~(0x00002000);
230 /* bit 29 for UART 1 */
231 *MuxConfReg &= ~(0x00002000);
233 (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0);
234 /* Configure for USB. Turn on VBUS_CTRL and VBUS_MODE. */
235 *MuxConfReg |= 0x000C0000;
237 (volatile unsigned int *) ((unsigned int)USB_TRANSCEIVER_CTRL);
238 *MuxConfReg &= ~(0x00000070);
239 *MuxConfReg &= ~(0x00000008);
240 *MuxConfReg |= 0x00000003;
241 *MuxConfReg |= 0x00000180;
243 (volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
244 /* bit 17, software controls VBUS */
245 *MuxConfReg &= ~(0x00020000);
246 /* Enable USB 48 and 12M clocks */
247 *MuxConfReg |= 0x00000200;
248 *MuxConfReg &= ~(0x00000180);
249 /*2.75V for MMCSDIO1 */
251 (volatile unsigned int *) ((unsigned int) VOLTAGE_CTRL_0);
252 *MuxConfReg = 0x00001FE7;
254 (volatile unsigned int *) ((unsigned int) PU_PD_SEL_0);
255 *MuxConfReg = 0x00000000;
257 (volatile unsigned int *) ((unsigned int) PU_PD_SEL_1);
258 *MuxConfReg = 0x00000000;
260 (volatile unsigned int *) ((unsigned int) PU_PD_SEL_2);
261 *MuxConfReg = 0x00000000;
263 (volatile unsigned int *) ((unsigned int) PU_PD_SEL_3);
264 *MuxConfReg = 0x00000000;
266 (volatile unsigned int *) ((unsigned int) PU_PD_SEL_4);
267 *MuxConfReg = 0x00000000;
269 (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_4);
270 *MuxConfReg = 0x00000000;
271 /* Turn on UART2 48 MHZ clock */
273 (volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
274 *MuxConfReg |= 0x40000000;
276 (volatile unsigned int *) ((unsigned int) USB_OTG_CTRL);
277 /* setup for USB VBus detection OMAP161x */
278 *MuxConfReg |= 0x00040000; /* bit 18 */
280 (volatile unsigned int *) ((unsigned int) PU_PD_SEL_2);
281 /* PullUps for SD/MMC driver */
282 *MuxConfReg |= ~(0xFFFE0FFF);
284 (volatile unsigned int *) ((unsigned int)COMP_MODE_CTRL_0);
285 *MuxConfReg = COMP_MODE_ENABLE;
288 /******************************************************
289 Routine: peripheral_power_enable
290 Description: Enable the power for UART1
291 *******************************************************/
292 void peripheral_power_enable (void)
294 #define UART1_48MHZ_ENABLE ((unsigned short)0x0200)
295 #define SW_CLOCK_REQUEST ((volatile unsigned short *)0xFFFE0834)
297 *SW_CLOCK_REQUEST |= UART1_48MHZ_ENABLE;
300 #ifdef CONFIG_CMD_NET
301 int board_eth_init(bd_t *bis)
304 #ifdef CONFIG_LAN91C96
305 rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);