1 // SPDX-License-Identifier: GPL-2.0+
3 * K2G: DDR3 initialization
6 * Texas Instruments Incorporated, <www.ti.com>
11 #include <asm/arch/ddr3.h>
12 #include <asm/arch/hardware.h>
15 /* K2G GP EVM DDR3 Configuration */
16 static struct ddr3_phy_config ddr3phy_800_2g = {
17 .pllcr = 0x000DC000ul,
18 .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
19 .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
25 .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
26 .dcr_val = ((1 << 10)),
27 .dtpr0 = 0x550F6644ul,
28 .dtpr1 = 0x328341E0ul,
29 .dtpr2 = 0x50022A00ul,
34 .pgcr2 = 0x00F03D09ul,
35 .zq0cr1 = 0x0001005Dul,
36 .zq1cr1 = 0x0001005Bul,
37 .zq2cr1 = 0x0001005Bul,
38 .pir_v1 = 0x00000033ul,
44 .datx8_4_val = ((1 << 0)),
45 .datx8_5_mask = DXEN_MASK,
47 .datx8_6_mask = DXEN_MASK,
49 .datx8_7_mask = DXEN_MASK,
51 .datx8_8_mask = DXEN_MASK,
53 .pir_v2 = 0x00000F81ul,
56 static struct ddr3_phy_config ddr3phy_1066_2g = {
57 .pllcr = 0x000DC000ul,
58 .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
59 .pgcr1_val = ((1 << 2) | (2 << 7) | (1 << 23)),
65 .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
66 .dcr_val = ((1 << 10)),
67 .dtpr0 = 0x6D147744ul,
68 .dtpr1 = 0x32845A80ul,
69 .dtpr2 = 0x50023600ul,
74 .pgcr2 = 0x00F05159ul,
75 .zq0cr1 = 0x0001005Dul,
76 .zq1cr1 = 0x0001005Bul,
77 .zq2cr1 = 0x0001005Bul,
78 .pir_v1 = 0x00000033ul,
84 .datx8_4_val = ((1 << 0)),
85 .datx8_5_mask = DXEN_MASK,
87 .datx8_6_mask = DXEN_MASK,
89 .datx8_7_mask = DXEN_MASK,
91 .datx8_8_mask = DXEN_MASK,
93 .pir_v2 = 0x00000F81ul,
96 static struct ddr3_emif_config ddr3_800_2g = {
97 .sdcfg = 0x62005662ul,
98 .sdtim1 = 0x0A385033ul,
99 .sdtim2 = 0x00001CA5ul,
100 .sdtim3 = 0x21ADFF32ul,
101 .sdtim4 = 0x533F067Ful,
102 .zqcfg = 0x70073200ul,
103 .sdrfc = 0x00000C34ul,
106 static struct ddr3_emif_config ddr3_1066_2g = {
107 .sdcfg = 0x62005662ul,
108 .sdtim1 = 0x0E4C6843ul,
109 .sdtim2 = 0x00001CC6ul,
110 .sdtim3 = 0x323DFF32ul,
111 .sdtim4 = 0x533F08AFul,
112 .zqcfg = 0x70073200ul,
113 .sdrfc = 0x00001044ul,
116 /* K2G ICE evm DDR3 Configuration */
117 static struct ddr3_phy_config ddr3phy_800_512mb = {
118 .pllcr = 0x000DC000ul,
119 .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
120 .pgcr1_val = ((1 << 2) | (2 << 7) | (1 << 23)),
121 .ptr0 = 0x42C21590ul,
122 .ptr1 = 0xD05612C0ul,
124 .ptr3 = 0x06C30D40ul,
125 .ptr4 = 0x06413880ul,
126 .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
127 .dcr_val = ((1 << 10)),
128 .dtpr0 = 0x550E6644ul,
129 .dtpr1 = 0x32834200ul,
130 .dtpr2 = 0x50022A00ul,
134 .dtcr = 0x710035C7ul,
135 .pgcr2 = 0x00F03D09ul,
136 .zq0cr1 = 0x0001005Dul,
137 .zq1cr1 = 0x0001005Bul,
138 .zq2cr1 = 0x0001005Bul,
139 .pir_v1 = 0x00000033ul,
140 .datx8_2_mask = DXEN_MASK,
142 .datx8_3_mask = DXEN_MASK,
144 .datx8_4_mask = DXEN_MASK,
146 .datx8_5_mask = DXEN_MASK,
148 .datx8_6_mask = DXEN_MASK,
150 .datx8_7_mask = DXEN_MASK,
152 .datx8_8_mask = DXEN_MASK,
154 .pir_v2 = 0x00000F81ul,
157 static struct ddr3_emif_config ddr3_800_512mb = {
158 .sdcfg = 0x62006662ul,
159 .sdtim1 = 0x0A385033ul,
160 .sdtim2 = 0x00001CA5ul,
161 .sdtim3 = 0x21ADFF32ul,
162 .sdtim4 = 0x533F067Ful,
163 .zqcfg = 0x70073200ul,
164 .sdrfc = 0x00000C34ul,
169 /* Reset DDR3 PHY after PLL enabled */
171 if (board_is_k2g_g1()) {
172 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1066_2g);
173 ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1066_2g);
174 } else if (board_is_k2g_gp()) {
175 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_800_2g);
176 ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_800_2g);
177 } else if (board_is_k2g_ice()) {
178 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_800_512mb);
179 ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_800_512mb);
185 inline int ddr3_get_size(void)