1 // SPDX-License-Identifier: GPL-2.0+
3 * Keystone2: DDR3 configuration
5 * (C) Copyright 2012-2014
6 * Texas Instruments Incorporated, <www.ti.com>
11 #include <asm/arch/ddr3.h>
14 struct ddr3_phy_config ddr3phy_1600_2g = {
15 .pllcr = 0x0001C000ul,
16 .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
17 .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
20 .ptr2 = 0, /* not set in gel */
23 .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
24 .dcr_val = ((1 << 10)),
25 .dtpr0 = 0x9D5CBB66ul,
26 .dtpr1 = 0x12868300ul,
27 .dtpr2 = 0x5002D200ul,
32 .pgcr2 = 0x00F07A12ul,
33 .zq0cr1 = 0x0001005Dul,
34 .zq1cr1 = 0x0001005Bul,
35 .zq2cr1 = 0x0001005Bul,
36 .pir_v1 = 0x00000033ul,
37 .pir_v2 = 0x0000FF81ul,
40 struct ddr3_emif_config ddr3_1600_2g = {
41 .sdcfg = 0x6200CE62ul,
42 .sdtim1 = 0x166C9855ul,
43 .sdtim2 = 0x00001D4Aul,
44 .sdtim3 = 0x435DFF53ul,
45 .sdtim4 = 0x543F0CFFul,
46 .zqcfg = 0x70073200ul,
47 .sdrfc = 0x00001869ul,