2 * K2G EVM : Board initialization
5 * Texas Instruments Incorporated, <www.ti.com>
7 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/clock.h>
11 #include <asm/ti-common/keystone_net.h>
12 #include <asm/arch/psc_defs.h>
13 #include <asm/arch/mmc_host_def.h>
15 #include "../common/board_detect.h"
17 #define SYS_CLK 24000000
19 unsigned int external_clk[ext_clk_count] = {
22 [tetris_clk] = SYS_CLK,
23 [ddr3a_clk] = SYS_CLK,
27 static int arm_speeds[DEVSPEED_NUMSPDS] = {
40 static int dev_speeds[DEVSPEED_NUMSPDS] = {
51 static struct pll_init_data main_pll_config[NUM_SPDS] = {
52 [SPD400] = {MAIN_PLL, 100, 3, 2},
53 [SPD600] = {MAIN_PLL, 300, 6, 2},
54 [SPD800] = {MAIN_PLL, 200, 3, 2},
55 [SPD900] = {TETRIS_PLL, 75, 1, 2},
56 [SPD1000] = {TETRIS_PLL, 250, 3, 2},
59 static struct pll_init_data tetris_pll_config[NUM_SPDS] = {
60 [SPD200] = {TETRIS_PLL, 250, 3, 10},
61 [SPD400] = {TETRIS_PLL, 100, 1, 6},
62 [SPD600] = {TETRIS_PLL, 100, 1, 4},
63 [SPD800] = {TETRIS_PLL, 400, 3, 4},
64 [SPD900] = {TETRIS_PLL, 75, 1, 2},
65 [SPD1000] = {TETRIS_PLL, 250, 3, 2},
68 static struct pll_init_data uart_pll_config = {UART_PLL, 64, 1, 4};
69 static struct pll_init_data nss_pll_config = {NSS_PLL, 250, 3, 2};
70 static struct pll_init_data ddr3_pll_config = {DDR3A_PLL, 133, 1, 16};
72 struct pll_init_data *get_pll_init_data(int pll)
75 struct pll_init_data *data = NULL;
79 speed = get_max_dev_speed(dev_speeds);
80 data = &main_pll_config[speed];
83 speed = get_max_arm_speed(arm_speeds);
84 data = &tetris_pll_config[speed];
87 data = &nss_pll_config;
90 data = &uart_pll_config;
93 data = &ddr3_pll_config;
103 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
106 #if defined(CONFIG_GENERIC_MMC)
107 int board_mmc_init(bd_t *bis)
109 if (psc_enable_module(KS2_LPSC_MMC)) {
110 printf("%s module enabled failed\n", __func__);
114 omap_mmc_init(0, 0, 0, -1, -1);
115 omap_mmc_init(1, 0, 0, -1, -1);
120 #ifdef CONFIG_BOARD_EARLY_INIT_F
122 static void k2g_reset_mux_config(void)
124 /* Unlock the reset mux register */
125 clrbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
127 /* Configure BOOTCFG_RSTMUX8 for WDT event to cause a device reset */
128 clrsetbits_le32(KS2_RSTMUX8, RSTMUX_OMODE8_MASK,
129 RSTMUX_OMODE8_DEV_RESET << RSTMUX_OMODE8_SHIFT);
131 /* lock the reset mux register to prevent any spurious writes. */
132 setbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
135 int board_early_init_f(void)
141 k2g_reset_mux_config();
143 /* deassert FLASH_HOLD */
144 clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET,
146 setbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_SETDATA_OFFSET,
153 #ifdef CONFIG_BOARD_LATE_INIT
154 int board_late_init(void)
156 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_TI_I2C_BOARD_DETECT)
159 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
160 CONFIG_EEPROM_CHIP_ADDRESS);
162 printf("ti_i2c_eeprom_init failed %d\n", rc);
164 board_ti_set_ethaddr(1);
171 #ifdef CONFIG_SPL_BUILD
172 void spl_init_keystone_plls(void)
178 #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
179 struct eth_priv_t eth_priv_cfg[] = {
181 .int_name = "K2G_EMAC",
185 .sgmii_link_type = SGMII_LINK_MAC_PHY,
186 .phy_if = PHY_INTERFACE_MODE_RGMII,
190 int get_num_eth_ports(void)
192 return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);